White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com

White Electronic Designs

WED2ZL236512S

B
B

ADV

DNC

DQP

DNC

DQP

E
E

DNC

F
F
F
F
F

DNC

J
J
J
J
J

DNC

K
K

CLK

L
L
L
L
L

CKE

P
P

DQP

R
R
R
R
R

DNC

LBO

T
T

DNC

VDD

January 2002, Rev. 4
ECO #14644

DESCRIPTION

The WEDC SyncBurst - SRAM family employs high-speed,
low-power CMOS designs that are fabricated using an ad-
vanced CMOS process. WEDC's 32Mb SyncBurst SRAMs
integrate two 512K x 36 SRAMs into a single BGA package
to provide 2 x 512K x 36 configuration. All synchronous
inputs pass through registers controlled by a positive-edge-
triggered single-clock input (CLK). The NBL or No Bus La-
tency Memory utilizes all the bandwidth in any combination
of operating cycles. Address, data inputs, and all control
signals except output enable and linear burst order are syn-
chronized to input clock. Burst order control must be tied
"High or Low." Asynchronous inputs include the sleep mode
enable (ZZ). Output Enable controls the outputs at any
given time. Write cycles are internally self-timed and initi-
ated by the rising edge of the clock input. This feature elimi-
nates complex off-chip write pulse generation and pro-
vides increased timing flexibility for incoming signals.

2 x 512K x 36 Synchronous Pipeline Burst NBL SR

2 x 512K x 36 Synchronous Pipeline Burst NBL SRAM

FIG. 1

BLOCK DIA

OCK DIA

OCK DIAGR

GRAM

PIN CONFIGUR

PIN CONFIGURA

ATION

TION

(TOP VIEW)

CLK

CKE

ADV

BWa
BWb
BWc
BWd

LBO

CEa

512K x 36

SSRAM

DQPa - DQP

512K x 36

SSRAM

CEb

FEA

FEATURES

TURES

Fast clock speed: 166, 150, 133, and 100MHz

Fast access times: 3.5ns, 3.8ns, 4.0ns, and 5.0ns

Fast OE access times: 3.5ns, 3.8ns, 4.0ns, and 5.0ns

Single +2.5V ± 5% power supply (VDD)

Snooze Mode for reduced-standby power

Individual Byte Write control

Clock-controlled and registered addresses, data I/Os

and control signals

Burst control (interleaved or linear burst)

Packaging:

· 119-bump BGA package

Low capacitive bus loading

Note:

Note:
DNC = Do Not Connect. Connections to these pins may cause the device to not function properly.

White Electronic Designs Corporation · Westborough, MA · (508) 366-5151

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WED2ZL236512S

(Linear Burst, LBO = Low)

Case 1

Case 2

Case 3

Case 4

LBO Pin

High

A 1

A 0

A 1

A 0

A 1

A 0

A 1

A 0

First Address

Fourth Address

and the data is latched in the output register. At the sec-
ond clock edge the data is driven out of the SRAM. During
read operation OE must be driven low for the device to
drive out the requested data.

Write operation occurs when WE is driven low at the rising
edge of the clock. BW[

] can be used for byte write

operation. The pipe-lined NBL SSRAM uses a late-late write
cycle to utilize 100% of the bandwidth. At the first rising
edge of the clock, WE and address are registered, and the
data associated with that address is required two cycle
later.

Subsequent addresses are generated by ADV High for the
burst access as shown below. The star ting point of the
burst seguence is provided by the external address. The
burst address counter wraps around to its initial state upon
completion. The burst sequence is determined by the state
of the LBO pin. When this pin is low, linear burst sequence
is selected. And when this pin is high, Interleaved burst
sequence is selected.

During normal operation, ZZ must be driven low. When ZZ
is driven high, the SRAM will enter a Power Sleep Mode
after 2 cycles. At this time, internal state of the SRAM is
preserved. When ZZ returns to low, the SRAM operates
after 2 cycles of wake up time.

BURST SEQUENCE TABLE

NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed.

(Interleaved Burst, LBO = High)

Case 1

Case 2

Case 3

Case 4

LBO Pin

High

A 1

A 0

A 1

A 0

A 1

A 0

A 1

A 0

First Address

Fourth Address

FUNCTION DESCRIPTION

The WED2ZL263512S is an NBL SSRAM designed to sus-
tain 100% bus bandwidth by eliminating turnaround cycle
when there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are syn-
chronized to rising clock edges.

All read, write and deselect cycles are initiated by the ADV
input. Subsequent burst addresses can be internally gen-
erated by the burst advance pin (ADV). ADV should be
driven to Low once the device has been deselected in
order to load a new address for next operation.

Clock Enable (CKE) pin allows the operation of the chip to
be suspended as long as necessary. When CKE is high, all
synchronous inputs are ignored and the internal device
registers will hold their previous values. NBL SSRAM latches
external address and initiates a cycle when CKE and ADV
are driven low at the rising edge of the clock.

Output Enable (OE) can be used to disable the output at
any given time. Read operation is initiated when at the ris-
ing edge of the clock, the address presented to the ad-
dress inputs are latched in the address register, CKE is driven
low, the write enable input signals WE are driven high, and
ADV driven low. The internal array is read between the
first rising edge and the second rising edge of the clock

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WED2ZL236512S

NOTES:
1. X means "Don't Care."
2. The rising edge of clock is symbolized by (

)

3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins (ZZ and OE).
6. CE

refers to both CE

and CE

with the exception that only one CE

or CE

can be active low at any time. Deselect requires both CE

and CE

to be high.

ADV

CKE

CLK

Address Accessed

Operation

N/A

Deselect

N/A

Continue Deselect

External Address

Begin Burst Read Cycle

Next Address

Continue Burst Read Cycle

External Address

NOP/Dummy Read

Next Address

Dummy Read

External Address

Begin Burst Write Cycle

Next Address

Continue Burst Write Cycle

N/A

NOP/Write Abort

Next Address

Write Abort

Current Address

Ignore Clock

TRUTH TABLES

YNCHRONOUS

RUTH

ABLE

RITE

RUTH

ABLE

B
B

Operation

Read

Write Byte

Write All Bytes

Write Abort/NOP

NOTES:
1. X means "Don't Care."
2. All inputs in this table must meet setup and hold time around the rising edge of CLK (

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White Electronic Designs

WED2ZL236512S

B
B

B
B SOL

SOL

SOLUTE

UTE

AXIMUM

ATINGS

TINGS

Voltage on V

Supply Relative to V

-0.3V to +3.6V

(DQ

)

-0.3V to +3.6V

(Inputs)

-0.3V to +3.6V

Storage Temperature (BGA)

-55°C to +125°C

Short Circuit Output Current

100mA

E
E

LECTRIC

LECTRICA L

A L

HAR

HARA

ACTERISTIC

CTERISTIC

CTERISTICS

(0°C - T

- 70°C)

*Stress greater than those listed under "Absolute Maximum Ratings: may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condtions for extended
periods may affect reliability.

Description

Symbol

Conditions

Min

Max

Units

Notes

Input High (Logic 1) Voltage

1.7

VDD +0.3

Input Low (Logic 0) Voltage

-0.3

0.7

Input Leakage Current

£ V

-5

µA

Output Leakage Current

Output(s) Disabled, 0V

£ V

-5

µA

Output High Voltage

= -1.0mA

2.0

Output Low Voltage

= 1.0mA

0.4

Supply Voltage

2.375

2.625

NOTES:
1. All voltages referenced to V

(GND)

2. ZZ pin has an internal pull-up, and input leakage = ± 10µA.

DC C

HAR

HARA

ACTERISTIC

CTERISTIC

CTERISTICS

NOTES:
1. I

is specified with no output current and increases with faster cycle times. I

increases with faster cycle times and greater output loading.

2. Typical values are measured at 2.5V, 25°C, and 10ns cycle time.

B
BG

GA C

A C

APA

ACIT

CIT

CITANCE

ANCE

NOTES:
1. This parameter is sampled.

Description

Symbol

Conditions

T
T

T
Typ

Max

Units

Notes

Control Input Capacitance

= 25°C; f = 1MHz

Input/Output Capacitance (DQ)

= 25°C; f = 1MHz

Address Capacitance

= 25°C; f = 1MHz

Clock Capacitance

= 25°C; f = 1MHz

2.5

166

150

133

100

Description

Symbol

Conditions

T
T

T
Typ

MHz

Units

Notes

Power Supply

Device Selected; All Inputs

£ VIL or ³ VIH; Cycle

390

360

330

290

1, 2

Current: Operating

Time = t

CYC

MIN; V

= MAX; Output Open

Power Supply

Device Deselected; V

= MAX; All Inputs

£ V

+ 0.2

Current: Standby

or V

- 0.2; All Inputs Static; CLK Frequency = 0;

£ VIL

Power Supply

Device Selected; All Inputs

£ V

³ V

; Cycle

Current: Current

Time = t

CYC

MIN; V

= MAX; Output Open;

³ VDD - 0.2V

Clock Running

Device Deselected; V

= MAX; All Inputs

140

120

100

Standby Current

£ VSS + 0.2 or VDD - 0.2; Cycle Time = t

CYC

MIN; ZZ

£ V

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WED2ZL236512S

AC C

C C

HAR

HARA

ACTERISTIC

CTERISTIC

CTERISTICS

NOTES:

NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CEx is sampled low.

All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low. A Read cycle is defined by WE High with ADV Low. Both cases

must meet setup and hold times.

UTPUT

OA D

A D

(A)

UTPUT

OA D

A D

(B)

(FOR

(FOR ttttt

LZC

, ttttt

LZOE

, ttttt

HZOE

, AND

, AND ttttt

HZC

))
))
)

Symbol

166MHz

150MHz

133MHz

100MHz

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Units

Clock Time

CYC

6.0

6.7

7.5

10.0

Clock Access Time

3.5

3.8

4.2

5.0

Output enable to Data Valid

3.5

3.8

4.2

5.0

Clock High to Output Low-Z

LZC

1.5

Output Hold from Clock High

1.5

Output Enable Low to output Low-Z

LZOE

0.0

Output Enable High to Output High-Z

HZOE

3.0

3.5

Clock High to Output High-Z

HZC

3.0

3.5

Clock High Pulse Width

2.2

2.5

3.0

Clock Low Pulse Width

2.2

2.5

3.0

Address Setup to Clock High

1.5

CKE Setup to Clock High

CES

1.5

Data Setup to Clock High

1.5

Write Setup to Clock High

1.5

Address Advance to Clock High

ADVS

1.5

Chip Select Setup to Clock High

CSS

1.5

Address Hold to Clock high

0.5

CKE Hold to Clock High

CEH

0.5

Data Hold to Clock High

0.5

Write Hold to Clock High

0.5

Address Advance to Clock High

ADVH

0.5

Chip Select Hold to Clock High

CSH

0.5

*Including Scope and Jig Capacitance

AC T

C T

EST

ONDITIONS

= 0 TO 70°C, V

= 2.5V ± 5%,

= 2.5V ± 5%, U

NLES

NLESS

THERWISE

PECIFIED

))
))
)

Parameter

Value

Input Pulse Level

0 to 2.5V

Input Rise and Fall Time (Measured at 20% to 80%)

1.0V/ns

Input and Output Timing Reference Levels

1.25V

Output Load

See Output Load (A)

Dout

Zo=50

RL=50

VL=1.25V

30pF*

Dout

1538

5pF*

+2.5V

1667

White Electronic Designs Corporation · Westborough, MA · (508) 366-5151

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WED2ZL236512S

SNOOZE MODE

SNOOZE MODE is a low-current, "power-down" mode in
which the device is deselected and current is reduced to
I

. The duration of SNOOZE MODE is dictated by the

length of time Z is in a HIGH state. After the device enters
SNOOZE MODE, all inputs except ZZ become gated in-
puts and are ignored. ZZ is an asynchronous, active HIGH
input that causes the device to enter SNOOZE MODE.

When ZZ becomes a logic HIGH, I

is guaranteed after

the setup time tZZ is met. Any READ or WRITE operation
pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore, SNOOZE
MODE must not be initiated until valid pending operations
are completed.

NOOZE

ODE

Description

Conditions

Symbol

Min

Max

Units

Notes

Current during SNOOZE MODE

³ VIH

ZZ active to input ignored

2(t

)

ZZ inactive to input sampled

RZZ

2(t

)

ZZ active to snooze current

ZZI

2(t

)

ZZ inactive to exit snooze current

RZZI

FIG. 2

FIG. 2 SNOOZE MODE TIMING DIAGRAM

SUPPLY

CLOCK

ALL INPUTS

(except ZZ)

Output (Q)

ZZI

RZZ

RZZI

HIGH-Z

DESELECT or READ Only

ISB2Z

DON'T CARE

1 2

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White Electronic Designs

WED2ZL236512S

Commercial T

Commercial Temp Range (0°C to 70°C)

emp Range (0°C to 70°C)

P
P

P
Par

art Number

t Number

Configuration

tCD

Clock

(ns)

(MHz)

WED2ZL236512S35BC

2 x 512K x 36

3.5

166

WED2ZL236512S38BC

2 x 512K x 36

3.8

150

WED2ZL236512S42BC

2 x 512K x 36

4.2

133

WED2ZL236512S50BC

2 x 512K x 36

5.0

100

ACK

CKA

AGE DIMENSION:

GE DIMENSION:

GE DIMENSION: 119 BUMP PBGA

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

2.79 (0.110)

MAX

0.711 (0.028)

MAX

1.27 (0.050)

TYP

1.27 (0.050) TYP

17.00 (0.669) TYP

A1
CORNER

32 (0.800)

TYP

23.00 (0.905)

TYP

7.62 (0.300)

TYP

R 1.52 (0.060)

MAX (4x)

ORDERING INFORMA

ORDERING INFORMATION

TION

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