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WED2ZL361MSJ

White Electronic Designs

1M x 36 Synchronous Pipeline Burst NBL SRAM

FIG. 1

BLOCK DIAGRAM

PIN CONFIGURATION

(TOP VIEW)

Address Bus
(SA

)

DQa, DQb
DQPa, DQPb

DQc, DQd
DQPc, DQPd

DQa DQd

DQPa DQPd

1M x 18

CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ

CLK
CKE

ADV

LBO

CE1
CE2
CE2

CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ

BWd

BWa

BWc

BWb

DDQ

CE2

ADV

CE2

DQP

CE1

DDQ

CLK

DDQ

CKE

DDQ

SA1

DQP

SA0

DQP

LBO

DDQ

FEATURES

Fast clock speed: 250, 225, 200, 166, 150, 133MHz

Fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns

Fast OE access times: 2.6, 2.8, 3.0, 3.5ns, 3.8ns, 4.2ns

Separate +2.5V ± 5% power supplies for core, I/O
(VDD, VDDQ)

n Snooze Mode for reduced-standby power

Individual Byte Write control

Clock-controlled and registered addresses, data I/Os
and control signals

Burst control (interleaved or linear burst)

Packaging:

· 119-bump BGA package

· JEDEC Pin Configuration

Low capacitive bus loading

DESCRIPTION

The WEDC SyncBurst - SRAM family employs high-speed,
low-power CMOS designs that are fabricated using an
advanced CMOS process. WEDC's 36Mb SyncBurst SRAMs
integrate two 1M x 18 SRAMs into a single BGA package
to provide 1M x 36 configuration. All synchronous inputs
pass through registers controlled by a positive-edge-
triggered single-clock input (CLK). The NBL or No Bus
Latency Memory utilizes all the bandwidth in any combi-
nation of operating cycles. Address, data inputs, and all
control signals except output enable and linear burst
order are synchronized to input clock. Burst order con-
trol must be tied "High or Low." Asynchronous inputs
include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are
internally self-timed and initiated by the rising edge of
the clock input. This feature eliminates complex off-chip
write pulse generation and provides increased timing
flexibility for incoming signals.

NOTE: NBL (No Bus Latency) is equivalent to ZBTTM.

October 2002 Rev. 1

ECO # 15465

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WED2ZL361MSJ

White Electronic Designs

Write operation occurs when WE is driven low at the
rising edge of the clock. BW[d:a] can be used for byte
write operation. The pipe-lined NBL SSRAM uses a late-
late write cycle to utilize 100% of the bandwidth. At the
first rising edge of the clock, WE and address are regis-
tered, and the data associated with that address is
required two cycles later.

Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of
the burst sequence is provided by the external address.
The burst address counter wraps around to its initial state
upon completion. The burst sequence is determined by
the state of the LBO pin. When this pin is low, linear burst
sequence is selected. When this pin is high, interleaved
burst sequence is selected.

During normal operation, ZZ must be driven low. When
ZZ is driven high, the SRAM will enter a Power Sleep
Mode after 2 cycles. At this time, internal state of the
SRAM is preserved. When ZZ returns to low, the SRAM
operates after 2 cycles of wake up time.

(Linear Burst, LBO = Low)

Case 1 Case 2 Case 3 Case 4

LBO Pin High A1 A0 A1 A0 A1 A0 A1 A0

First Address

Fourth Address

BURST SEQUENCE TABLE

NOTES
1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

2. LBO cannot change after initial power up.

(Interleaved Burst, LBO = High)

Case 1 Case 2 Case 3 Case 4

LBO Pin High A1 A0 A1 A0 A1 A0 A1 A0

First Address

Fourth Address

FUNCTION DESCRIPTION

The WED2ZL361MSJ is an NBL SSRAM designed to
sustain 100% bus bandwidth by eliminating turnaround
cycles when there is transition from Read to Write, or
vice versa. All inputs (with the exception of OE, LBO
and ZZ) are synchronized to rising clock edges.

All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be inter-
nally generated by the burst advance pin (ADV). ADV
should be driven to Low once the device has been
deselected in order to load a new address for next
operation.

The clock Enable (CKE) pin allows the operation of the
chip to be suspended as long as necessary. When CKE
is high, all synchronous inputs are ignored and the
internal device registers will hold their previous values.
NBL SSRAM latches external address and initiates a cycle
when CKE and ADV are driven low at the rising edge of
the clock.

Output Enable (OE) can be used to disable the output
at any given time. Read operation is initiated when at the
rising edge of the clock, the address presented to the
address inputs are latched in the address register, CKE is
driven low, the write enable input signals WE are driven
high, and ADV driven low. The internal array is read
between the first rising edge and the second rising edge
of the clock and the data is latched in the output register.
At the second clock edge the data is driven out of the
SRAM. During read operation OE must be driven low for
the device to drive out the requested data.

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WED2ZL361MSJ

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CEx ADV WE BWx OE

CKE CLK Address Accessed

Operation

N/A

Deselect

N/A

Continue Deselect

External Address

Begin Burst Read Cycle

Next Address

Continue Burst Read Cycle

External Address

NOP/Dummy Read

Next Address

Dummy Read

External Address

Begin Burst Write Cycle

Next Address

Continue Burst Write Cycle

N/A

NOP/Write Abort

Next Address

Write Abort

Current Address

Ignore Clock

NOTES:
1.

X means "Don't Care."

The rising edge of clock is symbolized by (

á )

A continue deselect cycle can only be entered if a deselect cycle is executed first.

WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

Operation finally depends on status of asynchronous input pins (ZZ and OE).

CEx refers to the combination of CE1, CE2 and CE2.

TRUTH TABLES

YNCHRONOUS

RUTH

ABLE

RITE

RUTH

ABLE

BWa

BWb

BWc

BWd

Operation

Read

Write Byte a

Write Byte b

Write Byte c

Write Byte d

Write All Bytes

Write Abort/NOP

NOTES:
1.

X means "Don't Care."

All inputs in this table must meet setup and hold time around the rising edge of CLK (

á).

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WED2ZL361MSJ

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BSOLUTE

AXIMUM

ATINGS

Voltage on V

Supply Relative to VSS

-0.3V to +3.6V

VIN (DQx)

-0.3V to +3.6V

VIN (Inputs)

-0.3V to +3.6V

Storage Temperature (BGA)

-55°C to +125°C

Shor t Circuit Output Current

100mA

ECOMMENDED

DC O

PERATING

ONDITIONS

OLTAGE

EFERENCED

: V

= OV, T

= 0°C

70°C; C

OMMERCIAL

= -40°C

+85°C; I

NDUSTRIAL

)

Stress greater than those listed under "Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability.

Description

Symbol

Conditions

Min

Max

Units

Notes

Input High (Logic 1) Voltage

1.7

+0.3

Input Low (Logic 0) Voltage

-0.3

0.7

Input Leakage Current

ILI

£ V

-5

µA

Output Leakage Current

Output(s) Disabled, 0V

£ V

-5

µA

Output High Voltage

= -1.0mA

2.0

---

Output Low Voltage

= 1.0mA

---

0.4

Supply Voltage

2.375

2.625

NOTES:
1. All voltages referenced to V

(GND)

2. ZZ pin has an internal pull-up, and input leakage is higher.

DC C

HARACTERISTICS

NOTES:
1.

is specified with no output current and increases with faster cycle times.

increases with faster cycle times and greater output loading.

Typical values are measured at 2.5V, 25°C, and 10ns cycle time.

BGA C

APACITANCE

NOTE:

1. This parameter is sampled.

Description

Symbol

Conditions

Typ

Max

Units

Notes

Control Input Capacitance

= 25°C; f = 1MHz

Input/Output Capacitance (DQ)

= 25°C; f = 1MHz

Address Capacitance

= 25°C; f = 1MHz

Clock Capacitance

= 25°C; f = 1MHz

250 200 166 133

Description

Symbol Conditions

Typ MHz MHz MHz MHz Units Notes

Power Supply

Device Selected; All Inputs

£ V

³ V

; Cycle

900

800

690

580

1, 2

Current: Operating

Time = T

CYC

MIN; V

= MAX; Output Open

Power Supply

SB2

Device Deselected; V

= MAX; All Inputs

Current: Standby

£ V

+ 0.2 or VDD - 0.2; All Inputs Static;

CLK Frequency = 0; ZZ

£ VIL

Power Supply

SB3

Device Selected; All Inputs

£ V

³ V

; Cycle

Current: Current

Time = T

CYC

MIN; V

= MAX; Output Open;

³ V

- 0.2V

Clock Running

SB4

Device Deselected; V

= MAX; All Inputs

150

140

130

100

Standby Current

£ V

+ 0.2 or V

- 0.2; Cycle Time = T

CYC

MIN; ZZ

£ V

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Symbol

250MHz

225MHz

200MHz

166MHz

150MHz

133MHz

Parameter

Min

Max

Min Max Min Max Min Max Min Max Min Max

Units

Clock Time

CYC

4.0

4.4

5.0

6.0

6.7

7.5

Clock Access Time

2.6

2.8

3.0

3.5

3.8

4.2

Output enable to Data Valid

2.6

2.8

3.0

3.5

3.8

4.2

Clock High to Output Low-Z

L Z C

1.5

Output Hold from Clock High

1.5

Output Enable Low to output Low-Z

LZOE

0.0

Output Enable High to Output High-Z

HZOE

2.6

2.8

3.0

3.5

Clock High to Output High-Z

HZC

2.6

2.8

3.0

3.5

Clock High Pulse Width

1.7

2.0

2.2

Clock Low Pulse Width

1.7

2.0

2.2

Address Setup to Clock High

1.2

1.4

1.5

CKE Setup to Clock High

CES

1.2

1.4

1.5

Data Setup to Clock High

1.2

1.4

1.5

Write Setup to Clock High

1.2

1.4

1.5

Address Advance to Clock High

ADVS

1.2

1.4

1.5

Chip Select Setup to Clock High

CSS

1.2

1.4

1.5

Address Hold to Clock high

0.3

0.4

0.5

CKE Hold to Clock High

CEH

0.3

0.4

0.5

Data Hold to Clock High

0.3

0.4

0.5

Write Hold to Clock High

0.3

0.4

0.5

Address Advance to Clock High

ADVH

0.3

0.4

0.5

Chip Select Hold to Clock High

CSH

0.3

0.4

0.5

ZZ High to Power Down

PDS

cycle

ZZ Low to Power Up

PUS

cycle

AC C

HARACTERISTICS

UTPUT

OAD

(A)

UTPUT

OAD

(B)

(

FOR

LZC

, t

LZOE

, t

HZOE

AND

HZC

)

Dout

Zo=50

RL=50

VL=1.25V

30pF*

Dout

1538

5pF*

+2.5V

1667

*Including Scope and Jig Capacitance

AC T

EST

ONDITIONS

= 0

70°C, VDD = 2.5V ± 5%; C

OMMERCIAL

= -40°C

+85°C, VDD = 2.5V ± 5%; I

NDUSTRIAL

)

Parameter

Value

Input Pulse Level

0 to 2.5V

Input Rise and Fall Time (Measured at 20% to 80%)

1.0V/ns

Input and Output Timing Reference Levels

1.25V

Output Load

See Output Load (A)

NOTES:
1.

All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CEx is sampled valid. All other

synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.

A write cycle is defined by WE low having been registered into the device at ADV Low.

A Read cycle is defined by WE High with ADV Low. Both cases must meet setup and hold times.

White Electronic Designs Corporation Westborough MA (508) 366-5151

WED2ZL361MSJ

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SNOOZE MODE

SNOOZE MODE is a low-current, "power-down" mode in
which the device is deselected and current is reduced to
I

SB2Z

. The duration of SNOOZE MODE is dictated by the

length of time Z is in a HIGH state. After the device enters
SNOOZE MODE, all inputs except ZZ and CLK are ignored.
ZZ is an asynchronous, active HIGH input that causes the
device to enter SNOOZE MODE.

When ZZ becomes a logic HIGH, I

SB2Z

is guaranteed after

the setup time tZZ is met. Any READ or WRITE operation
pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore, SNOOZE
MODE must not be initiated until valid pending opera-
tions are completed.

NOOZE

ODE

Description

Conditions

Symbol

Min

Max

Units

Notes

Current during SNOOZE MODE

³ VIH

SB2Z

ZZ active to input ignored

2(t

)

ZZ inactive to input sampled

RZZ

2(t

)

ZZ active to snooze current

ZZI

2(t

)

ZZ inactive to exit snooze current

RZZI

FIG. 2

SUPPLY

CLOCK

ALL INPUTS

(except ZZ)

Output (Q)

ZZI

RZZ

RZZI

HIGH-Z

DESELECT or READ Only

ISB2Z

DON'T CARE

SNOOZE MODE TIMING DIAGRAM

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PACKAGE DIMENSION: 119 BUMP PBGA

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

2.79 (0.110)

MAX

0.711 (0.028)

MAX

1.27 (0.050)

TYP

1.27 (0.050) TYP

17.00 (0.669) TYP

A1 CORNER

20.32 (0.800)

TYP

23.00 (0.905)

TYP

7.62 (0.300)

TYP

Ordering Information

Commercial Temp Range (0°C to 70°C)
Part Number

Configuration

Clock

(ns)

(MHz)

WED2ZL361MSJ26BC

1M x 36

2.6

250

WED2ZL361MSJ28BC

1M x 36

2.8

225

WED2ZL361MSJ30BC

1M x 36

3.0

200

WED2ZL361MSJ35BC

1M x 36

3.5

166

WED2ZL361MSJ38BC

1M x 36

3.8

150

WED2ZL361MSJ42BC

1M x 36

4.2

133

NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined.

Industrial Temp Range (-40°C to +85°C)
Part Number

Configuration

Clock

(ns)

(MHz)

WED2ZL361MSJ26BI*

1M x 36

2.6

250

WED2ZL361MSJ28BI

1M x 36

2.8

225

WED2ZL361MSJ30BI

1M x 36

3.0

200

WED2ZL361MSJ35BI

1M x 36

3.5

166

WED2ZL361MSJ38BI

1M x 36

3.8

150

WED2ZL361MSJ42BI

1M x 36

4.2

133

* consult factory for availability

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