White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZL361MV

June 2004
Rev. 3

DESCRIPTION

The WEDC SyncBurst -- SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDC's 32Mb
SyncBurst SRAMs integrate two 1M x 18 SRAMs into a
single BGA package to provide 1M x 36 confi guration. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single-clock input (CLK). The
NBL or No Bus Latency Memory utilizes all the bandwidth
in any combination of operating cycles. Address, data
inputs, and all control signals except output enable and
linear burst order are synchronized to input clock. Burst
order control must be tied "High or Low." Asynchronous
inputs include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are
internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip write
pulse generation and provides increased timing fl exibility
for incoming signals.

1Mx36 Synchronous Pipeline Burst NBL SRAM

FIGURE 1 PIN CONFIGURATION

Block Diagram

Address Bus
(SA

- SA

)

DQa, DQb
DQPa, DQPb

DQc, DQd
DQPc, DQPd

DQa - DQd

DQPa - DQPd

1M x 18

CLK
CKE#
ADV#
LBO#
CS1#
CS2
CS2#
OE#
WE#
ZZ

CLK

CKE#
ADV#
LBO#

CE1#

CE2

CE2#

OE#

WE#

BWd#

BWc#

BWb#

FEATURES

Fast clock speed: 166, 150, 133, and 100MHz

Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns

Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and
5.0ns

Single +3.3V ± 5% power supply (V

)

Snooze Mode for reduced-standby power

Individual Byte Write control

Clock-controlled and registered addresses, data
I/Os and control signals

Burst control (interleaved or linear burst)

Packaging:

119-bump BGA package

Low capacitive bus loading

This product is subject to change without notice.

CE2

ADV#

VCC

DQC

DQPC

DQPB

DQB

DQC

DQB

DQC

OE#

DQB

DQC

DQB

DQC

WE#

DQB

DQD

CLK

DQA

DQD

DQA

DQD

CKE#

DQA

DQD

SA1

DQA

DQD

DQPD

SA0

DQPA

DQA

LBO

(Top View)

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZL361MV

June 2004
Rev. 3

The WED2ZL361MV is an NBL SSRAM designed to
sustain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or vice
versa. All inputs (with the exception of OE#, LBO and ZZ)
are synchronized to rising clock edges.

All read, write and deselect cycles are initiated by the
ADV# input. Subsequent burst addresses can be internally
generated by the burst advance pin (ADV#). ADV# should
be driven to Low once the device has been deselected in
order to load a new address for next operation.

Clock Enable (CKE) pin allows the operation of the chip to
be suspended as long as necessary. When CKE is high,
all synchronous inputs are ignored and the internal device
registers will hold their previous values. NBL SSRAM
latches external address and initiates a cycle when CKE
and ADV are driven low at the rising edge of the clock.

Output Enable (OE) can be used to disable the output at
any given time. Read operation is initiated when at the
rising edge of the clock, the address presented to the
address inputs are latched in the address register, CKE is
driven low, the write enable input signals WE# are driven
high, and ADV# driven low. The internal array is read
between the fi rst rising edge and the second rising edge
of the clock and the data is latched in the output register.
At the second clock edge the data is driven out of the
SRAM. During read operation OE# must be driven low for
the device to drive out the requested data.

BURST SEQUENCE TABLE

NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed.

Write operation occurs when WE# is driven low at the rising
edge of the clock. BW#[d:a] can be used for byte write
operation. The pipe-lined NBL SSRAM uses a late-late
write cycle to utilize 100% of the bandwidth. At the fi rst
rising edge of the clock, WE# and address are registered,
and the data associated with that address is required two
cycle later.

Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of the
burst seguence is provided by the external address. The
burst address counter wraps around to its initial state upon
completion. The burst sequence is determined by the state
of the LBO pin. When this pin is low, linear burst sequence
is selected. And when this pin is high, Interleaved burst
sequence is selected.

During normal operation, ZZ must be driven low. When ZZ
is driven high, the SRAM will enter a Power Sleep Mode
after 2 cycles. At this time, internal state of the SRAM is
preserved. When ZZ returns to low, the SRAM operates
after 2 cycles of wake up time.

(Interleaved Burst, LBO = High)

LBO Pin

High

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

FUNCTION DESCRIPTION

(Linear Burst, LBO = Low)

LBO Pin

High

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZL361MV

June 2004
Rev. 3

TRUTH TABLES

Synchronous Truth Table

CEx#

ADV#

WE#

BWx#

OE#

CKE#

CLK

Address Accessed

Operation

N/A

Deselect

N/A

Continue Deselect

External Address

Begin Burst Read Cycle

Next Address

Continue Burst Read Cycle

External Address

NOP/Dummy Read

Next Address

Dummy Read

External Address

Begin Burst Write Cycle

Next Address

Continue Burst Write Cycle

N/A

NOP/Write Abort

Next Address

Write Abort

Current Address

Ignore Clock

NOTES:
1. X means "Don't Care."
2. The rising edge of clock is symbolized by ( )
3. A continue deselect cycle can only be entered if a deselect cycle is executed fi rst.
4. WRITE# = L means Write operation in WRITE TRUTH TABLE.

WRITE# = H means Read operation in WRITE TRUTH TABLE.

5. Operation fi nally depends on status of asynchronous input pins (ZZ and OE#).
6. CEx# refers to the combination of CE

#, CE

# and CE

Write Truth Table

WE#

BWa#

BWb#

BWc#

BWd#

Operation

Read

Write Byte a

Write Byte b

Write Byte c

Write Byte d

Write All Bytes

Write Abort/NOP

NOTES:
1. X means "Don't Care."
2. All inputs in this table must meet setup and hold time around the rising edge of CLK ( ).

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZL361MV

June 2004
Rev. 3

Absolute Maximum Ratings*

Voltage on V

Supply Relative to V

-0.3V to +4.6V

(DQx)

-0.3V to +4.6V

(Inputs)

-0.3V to +4.6V

Storage Temperature (BGA)

-65°C to +150°C

Short Circuit Output Current

100mA

* Stress greater than those listed under "Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions greater than those indicated in the operational sections of this specifi cation is not implied. Exposure to absolute maximum rating condtions for extended
periods may affect reliability.

Recommended DC Operating Conditions Voltage Referenced to:

= 0V, = 0°C T

+70°C; Commercial or -40°C T

+85°C; Industrial

Description

Symbol

Conditions

Min

Max

Units

Notes

Input High (Logic 1) Voltage

2.0

+0.5

Input Low (Logic 0) Voltage

-0.3

0.8

Input Leakage Current

0V V

-5

µA

Output Leakage Current

Output(s) Disabled, 0V V

-5

µA

Output High Voltage

= -4.0mA

2.4

Output Low Voltage

= 8.0mA

0.4

Supply Voltage

3.135

3.465

NOTES:
1. All voltages referenced to V

(GND)

2. ZZ pin has an internal pull-up, and input leakage = ± 10µA.

DC Characteristics

Description

Symbol

Conditions

Typ

166

150

133

100

Units

Notes

MHz

Power Supply
Current: Operating

Device Selected; All Inputs V

or V

; Cycle Time =

CYC

MIN; V

= MAX; Output Open

840

800

760

640

1, 2

Power Supply
Current: Standby

SB2

Device Deselected; V

= MAX; All Inputs V

+ 0.2 or

- 0.2; All Inputs Static; CLK Frequency = 0; ZZ V

Power Supply
Current: Current

SB3

Device Selected; All Inputs V

or V

; Cycle Time =

CYC

MIN; V

= MAX; Output Open; ZZ V

- 0.2V

Clock Running
Standby Current

SB4

Device Deselected; V

= MAX; All Inputs V

+ 0.2 or

- 0.2; Cycle Time = T

CYC

MIN; ZZ V

240

220

180

160

NOTES:
1. I

is specifi ed with no output current and increases with faster cycle times.

increases with faster cycle times and greater output loading.

2. Typical values are measured at 3.3V, 25°C, and 10ns cycle time.

BGA Capacitance

Description

Symbol

Conditions

Typ

Max

Units

Notes

Control Input Capacitance

= 25°C; f = 1MHz

Input/Output Capacitance (DQ)

= 25°C; f = 1MHz

Address Capacitance

= 25°C; f = 1MHz

Clock Capacitance

= 25°C; f = 1MHz

NOTES: 1. This parameter is sampled.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZL361MV

June 2004
Rev. 3

AC Characteristics

Parameter

Symbol

166MHz

150MHz

133MHz

100MHz

Units

Min

Max

Min

Max

Min

Max

Min

Max

Clock Time

CYC

6.0

6.7

7.5

10.0

Clock Access Time

3.5

3.8

4.2

5.0

Output enable to Data Valid

3.5

3.8

4.2

5.0

Clock High to Output Low-Z

LZC

1.5

Output Hold from Clock High

1.5

Output Enable Low to output Low-Z

LZOE

0.0

Output Enable High to Output High-Z

HZOE

3.0

3.5

Clock High to Output High-Z

HZC

3.0

3.5

Clock High Pulse Width

2.2

2.5

3.0

Clock Low Pulse Width

2.2

2.5

3.0

Address Setup to Clock High

1.5

CKE Setup to Clock High

CES

1.5

Data Setup to Clock High

1.5

Write Setup to Clock High

1.5

Address Advance to Clock High

ADVS

1.5

Chip Select Setup to Clock High

CSS

1.5

Address Hold to Clock high

0.5

CKE Hold to Clock High

CEH

0.5

Data Hold to Clock High

0.5

Write Hold to Clock High

0.5

Address Advance to Clock High

ADVH

0.5

Chip Select Hold to Clock High

CSH

0.5

NOTES:
1. All Address inputs must meet the specifi ed setup and hold times for all rising clock

(CLK) edges when ADV# is sampled low and CEx# is sampled valid. All other
synchronous inputs must meet the specifi ed setup and hold times whenever this
device is chip selected.

2. Chip enable must be valid at each rising edge of CLK (when ADV# is Low) to remain

enabled.

3. A write cycle is defi ned by WE# low having been registered into the device at ADV

Low. A Read cycle is defi ned by WE# High with ADV# Low. Both cases must meet
setup and hold times.

Output Load (A)

OUT

Zo=50

RL=50

VL=1.5V

30pF*

OUT

353

5pF*

+3.3V

3.9

*Including Scope and Jig Capacitance

AC Test Conditions

= 0V, = 0°C T

+70°C, V

= 3.3V ± 5%; Commercial or -40°C T

+85°C, V

= 3.3V ± 5%; Industrial

Parameter

Value

Input Pulse Level

0 to 3.0V

Input Rise and Fall Time (Measured at 20% to 80%)

1.0V/ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Output Load (A)

Output Load (B)

for a t

LZC

, t

LZOE

, t

HZOE

, and t

HZC

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZL361MV

June 2004
Rev. 3

SNOOZE MODE

SNOOZE MODE is a low-current, "power-down" mode in
which the device is deselected and current is reduced to
I

. The duration of SNOOZE MODE is dictated by the

length of time Z is in a HIGH state. After the device enters
SNOOZE MODE, all inputs except ZZ become gated inputs
and are ignored. ZZ is an asynchronous, active HIGH input
that causes the device to enter SNOOZE MODE.

When ZZ becomes a logic HIGH, I

is guaranteed after

the setup time t

is met. Any READ or WRITE operation

pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore, SNOOZE
MODE must not be initiated until valid pending operations
are completed.

SNOOZE MODE

Description Conditions

SYMBOL

Min

Max

Units

Notes

Current during SNOOZE MODE

ZZ V

SB2Z

10 mA

ZZ active to input ignored

2(t

)

ns 1

ZZ inactive to input sampled

RZZ

2(t

) ns

ZZ active to snooze current

ZZI

2(t

)

ns 1

ZZ inactive to exit snooze current

RZZI

SUPPLY

CLOCK

ALL INPUTS

(except ZZ)

Output (Q)

ZZI

RZZ

RZZI

HIGH-Z

DESELECT or READ Only

ISB2Z

DON'T CARE

FIGURE 2 SNOOZE MODE TIMING DIAGRAM

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZL361MV

June 2004
Rev. 3

Commercial Temp Range (0°C to 70°C)

Part Number

Confi guration

(ns)

Clock
(MHz)

WED2ZL361MV35BC

1M x 36

3.5

166

WED2ZL361MV38BC

1M x 36

3.8

150

WED2ZL361MV42BC

1M x 36

4.2

133

WED2ZL361MV50BC

1M x 36

5.0

100

PACKAGE DIMENSION: 119 BUMP PBGA

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

1.90 (0.075)

MAX

0.711 (0.028)

MAX

1.27 (0.050)

TYP

1.27 (0.050) TYP

17.00 (0.669) TYP

A1
CORNER

20.32 (0.800)

TYP

23.00 (0.905)

TYP

7.62 (0.300)

TYP

ORDERING INFORMATION

NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defi ned.

Industrial Temp Range (-40°C to +85°C)

Part Number

Confi guration

(ns)

Clock
(MHz)

WED2ZL361MV35BI

1M x 36

3.5

166

WED2ZL361MV38BI

1M x 36

3.8

150

WED2ZL361MV42BI

1M x 36

4.2

133

WED2ZL361MV50BI

1M x 36

5.0

100

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