1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED2ZL362MSJ
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDCs 72Mb
SyncBurst SRAMs integrate two 2M x 18 SRAMs into a
single BGA package to provide a 2M x 36 configuration.
All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single-clock input
(CLK). The NBL or No Bus Latency Memory utilizes all
the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except
output enable and linear burst order are synchronized
to input clock. Burst order control must be tied High or
Low. Asynchronous inputs include the sleep mode en-
able (ZZ) and Output Enable (OE). Write cycles are in-
ternally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip
write pulse generation and provides increased timing
flexibility for incoming signals.
72Mb, 2M x 36 Synchronous Pipeline Burst NBL SRAM
FIG. 1 PIN CONFIGURATION
BLOCK DIAGRAM
(TOP VIEW)
Address Bus
(SA
0
SA
20
)
DQ
A
, DQ
B
DQP
A
, DQP
B
DQ
C
, DQ
D
DQP
C
, DQP
D
DQ
A
DQ
D
DQP
A
DQP
D
2M x 18
2M x 18
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CE1
CE2
CE2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
BW
D
BW
A
BW
C
BW
B
FEATURES
n
Fast clock speed: 225, 200, 166 and 150MHz
n
Fast access times: 2.8, 3.0, 3.5 and 3.8ns
n
Fast OE access times: 2.8, 3.0, 3.5 and 3.8ns
n
Separate Core and I/O Power Supply
n
Snooze Mode for reduced-standby power
n
Individual Byte Write control
n
Clock-controlled and registered addresses, data I/Os
and control signals
n
Burst control (interleaved or linear burst)
n
Packaging:
119-bump BGA package, JEDEC Pin Definition
n
Low capacitive bus loading
July 2002 Rev 0
ECO # 15239
1
2
3
4
5
6
7
A
V
DDQ
SA
SA
SA
SA
SA
V
DDQ
B
NC
CE
2
SA
ADV
SA
CE
2
NC
C
NC
SA
SA
V
DD
SA
SA
NC
D
DQ
C
DQP
C
V
SS
NC
V
SS
DQP
B
DQ
B
E
DQ
C
DQ
C
V
SS
CE
1
V
SS
DQ
B
DQ
B
F
V
DDQ
DQ
C
V
SS
OE
V
SS
DQ
B
V
DDQ
G
DQ
C
DQ
C
BW
C
SA
BW
B
DQ
B
DQ
B
H
DQ
C
DQ
C
V
SS
WE
V
SS
DQ
B
DQ
B
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
DQ
D
DQ
D
V
SS
CLK
V
SS
DQ
A
DQ
A
L
DQ
D
DQ
D
BW
D
NC
BW
A
DQ
A
DQ
A
M
V
DDQ
DQ
D
V
SS
CKE
V
SS
DQ
A
V
DDQ
N
DQ
D
DQ
D
V
SS
SA
1
V
SS
DQ
A
DQ
A
P
DQ
D
DQP
D
V
SS
SA
0
V
SS
DQP
A
DQ
A
R
NC
SA
LBO
V
DD
NC
SA
NC
T
NC
SA
SA
SA
SA
SA
ZZ
U
V
DDQ
RFU
RFU
RFU
RFU
NC
V
DDQ
Advanced
2
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White Electronic Designs
WED2ZL362MSJ
BURST SEQUENCE TABLE
NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed.
Write operation occurs when WE is driven low at the ris-
ing edge of the clock. BW[d:a] can be used for byte write
operation. The pipe-lined NBL SSRAM uses a late-late
write cycle to utilize 100% of the bandwidth. At the first
rising edge of the clock, WE and address are registered,
and the data associated with that address is required two
cycle later.
Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of
the burst seguence is provided by the external address.
The burst address counter wraps around to its initial state
upon completion. The burst sequence is determined by
the state of the LBO pin. When this pin is low, linear burst
sequence is selected. And when this pin is high, Inter-
leaved burst sequence is selected.
During normal operation, ZZ must be driven low. When
ZZ is driven high, the SRAM will enter a Power Sleep
Mode after 2 cycles. At this time, internal state of the
SRAM is preserved. When ZZ returns to low, the SRAM
operates after 2 cycles of wake up time.
(Interleaved Burst, LBO = High)
Case 1
Case 2
Case 3
Case 4
LBO Pin
High
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
0
First Address
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
Fourth Address
1
1
1
0
0
1
0
0
(Linear Burst, LBO = Low)
Case 1
Case 2
Case 3
Case 4
LBO Pin
High
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
0
First Address
0
0
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address
1
1
0
0
0
1
1
0
FUNCTION DESCRIPTION
The WED2ZL362MSJ is an NBL SSRAM designed to
sustain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or vice
versa. All inputs (with the exception of OE, LBO and ZZ)
are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be inter-
nally generated by the burst advance pin (ADV). ADV
should be driven to Low once the device has been dese-
lected in order to load a new address for next operation.
Clock Enable (CKE) pin allows the operation of the chip
to be suspended as long as necessary. When CKE is
high, all synchronous inputs are ignored and the internal
device registers will hold their previous values. NBL
SSRAM latches external address and initiates a cycle
when CKE and ADV are driven low at the rising edge of
the clock.
Output Enable (OE) can be used to disable the output at
any given time. Read operation is initiated when at the
rising edge of the clock, the address presented to the
address inputs are latched in the address register, CKE
is driven low, the write enable input signals WE are driven
high, and ADV driven low. The internal array is read be-
tween the first rising edge and the second rising edge of
the clock and the data is latched in the output register. At
the second clock edge the data is driven out of the SRAM.
During read operation OE must be driven low for the
device to drive out the requested data.
3
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White Electronic Designs
WED2ZL362MSJ
TRUTH TABLES
S
YNCHRONOUS
T
RUTH
T
ABLE
W
RITE
T
RUTH
T
ABLE
WE
BWaBWb
BWc
BWd
Opera
tion
H
XXXX
Read
L
L
H
H
H
Write Byte a
L
H
L
H
H
Write Byte b
L
H
H
L
H
Write Byte c
L
H
H
H
L
Write Byte d
L
L
L
L
L
Write All Bytes
L
H
H
H
H
Write Abort/NOP
NOTES:
1. X means Dont Care.
2. All inputs in this table must meet setup and hold time around the rising edge of
CLK ( ).
CEx
ADV
WE
BWx
OE
CKE
CLK
Address Accessed
Operation
H
L
X
X
X
L
N/A
Deselect
X
H
X
X
X
L
N/A
Continue Deselect
L
L
H
X
L
L
External Address
Begin Burst Read Cycle
X
H
X
X
L
L
Next Address
Continue Burst Read Cycle
L
L
H
X
H
L
External Address
NOP/Dummy Read
X
H
X
X
H
L
Next Address
Dummy Read
L
L
L
L
X
L
External Address
Begin Burst Write Cycle
X
H
X
L
X
L
Next Address
Continue Burst Write Cycle
L
L
L
H
X
L
N/A
NOP/Write Abort
X
H
X
H
X
L
Next Address
Write Abort
X
X
X
X
X
H
Current Address
Ignore Clock
NOTES:
1. X means Dont Care.
2. The rising edge of clock is symbolized by ( )
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins (ZZ and OE).
6. CEx refers to the combination of CE1, CE2 and CE2.
4
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White Electronic Designs
WED2ZL362MSJ
A
BSOLUTE
M
AXIMUM
R
ATINGS
*
Voltage on V
DD
Supply Relative to V
SS
-0.3V to +3.6V
V
IN
(DQx)
-0.3V to +3.6V
V
IN
(Inputs)
-0.3V to +3.6V
Storage Temperature (BGA)
-55C to +125C
Short Circuit Output Current
100mA
E
LECTRICAL
C
HARACTERISTICS
*Stress greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating condtions for extended periods may affect reliability.
Description
Symbol
Conditions
Min
Max
Units
Notes
Input High (Logic 1) Voltage
V
IH
1.7
V
DD
+0.3
V
1
Input Low (Logic 0) Voltage
V
IL
-0.3
0.7
V
1
Input Leakage Current
I
LI
0V V
IN
V
DD
-5
5
A
2
Output Leakage Current
I
LO
Output(s) Disabled, 0V V
IN
V
DD
-5
5
A
Output High Voltage
V
OH
I
OH
= -1.0mA
2.0
V
1
Output Low Voltage
V
OL
I
OL
= 1.0mA
0.4
V
1
Supply Voltage
V
DD
2.375
2.625
V
1
NOTES:
1. All voltages referenced to V
SS
(GND)
2. ZZ pin has an internal pull-up, and input leakage is higher.
DC C
HARACTERISTICS
NOTES:
1. IDD is specified with no output current and increases with faster cycle times.
2. Typical values are measured at 2.5V, 25C, and 10ns cycle time.
3. Typical values are measured at 2.5V, 25C.
BGA C
APACITANCE
NOTES:
1. This parameter is sampled.
Description
Symbol
Conditions
Typ
Max
Units
Notes
Control Input Capacitance
C
I
T
A
= 25C; f = 1MHz
5
7
pF
1
Input/Output Capacitance (DQ)
C
O
T
A
= 25C; f = 1MHz
6
8
pF
1
Address Capacitance
C
A
T
A
= 25C; f = 1MHz
5
7
pF
1
Clock Capacitance
C
CK
T
A
= 25C; f = 1MHz
3
5
pF
1
225
200
166
150
Description
Symbol
Conditions
Typ MHz MHz MHz MHz
Units
Notes
Power Supply
I
DD
Device Selected; All Inputs V
IL
or V
IH
; Cycle
800
740
690
640
mA
1, 2
Current: Operating
Time = t
CYC
MIN; V
DD
= MAX; Output Open
Power Supply
I
SB2
Device Deselected; V
DD
= MAX; All Inputs V
SS
+ 0.2
30
60
60
60
60
mA
3
Current: Standby
or V
DD
- 0.2; All Inputs Static; CLK Frequency = 0;
ZZ V
IL
Power Supply
I
SB3
Device Selected; All Inputs V
IL
or V
IH
; Cycle
20
40
40
40
40
mA
2
Current: Current
Time = t
CYC
MIN; V
DD
= MAX; Output Open;
ZZ V
DD
- 0.2V
Clock Running
I
SB4
Device Deselected; V
DD
= MAX; All Inputs
160
148
135
125
mA
2
Standby Current
V
SS
+ 0.2 or V
DD
- 0.2; Cycle Time = t
CYC
MIN; ZZ V
IL
5
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White Electronic Designs
WED2ZL362MSJ
AC C
HARACTERISTICS
NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CEx is
sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.
3. A WRITE cycle is defined by WE low having been registered into the device at ADV Low.
A READ cycle is defined by WE High with ADV Low. Both cases must meet setup and hold times.
O
UTPUT
L
OAD
(A)
O
UTPUT
L
OAD
(B)
(
FOR
t
LZC
, t
LZOE
, t
HZOE
,
AND
t
HZC
)
Symbol
225MHz
200MHz
166MHz
150MHz
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Units
Clock Time
t
CYC
4.4
5.0
6.0
6.7
ns
Clock Access Time
t
CD
2.8
3.0
3.5
3.8
ns
Output enable to Data Valid
t
OE
2.8
3.0
3.5
3.8
ns
Clock High to Output Low-Z
t
LZC
1.5
1.5
1.5
1.5
ns
Output Hold from Clock High
t
OH
1.5
1.5
1.5
1.5
ns
Output Enable Low to output Low-Z
t
LZOE
0.0
0.0
0.0
0.0
ns
Output Enable High to Output High-Z
t
HZOE
2.5
2.5
3.0
3.0
ns
Clock High to Output High-Z
t
HZC
2.5
2.5
3.0
3.0
ns
Clock High Pulse Width
t
CH
1.8
2.0
2.2
2.5
ns
Clock Low Pulse Width
t
CL
1.8
2.0
2.2
2.5
ns
Address Setup to Clock High
t
AS
1.5
1.5
1.5
1.5
ns
CKE Setup to Clock High
t
CES
1.5
1.5
1.5
1.5
ns
Data Setup to Clock High
t
DS
1.5
1.5
1.5
1.5
ns
Write Setup to Clock High
t
WS
1.5
1.5
1.5
1.5
ns
Address Advance to Clock High
t
ADVS
1.5
1.5
1.5
1.5
ns
Chip Select Setup to Clock High
t
CSS
1.5
1.5
1.5
1.5
ns
Address Hold to Clock high
t
AH
0.5
0.5
0.5
0.5
ns
CKE Hold to Clock High
t
CEH
0.5
0.5
0.5
0.5
ns
Data Hold to Clock High
t
DH
0.5
0.5
0.5
0.5
ns
Write Hold to Clock High
t
WH
0.5
0.5
0.5
0.5
ns
Address Advance to Clock High
t
ADVH
0.5
0.5
0.5
0.5
ns
Chip Select Hold to Clock High
t
CSH
0.5
0.5
0.5
0.5
ns
Dout
Zo=50
RL=50
VL=1.25V
30pF*
Dout
1538
5pF*
+2.5V
1667
*Including Scope and Jig Capacitance
AC T
EST
C
ONDITIONS
(V
DD
= 2.5V 5%, U
NLESS
O
THERWISE
S
PECIFIED
)
Parameter
Value
Input Pulse Level
0 to 2.5V
Input Rise and Fall Time (Measured at 20% to 80%)
1.0V/ns
Input and Output Timing Reference Levels
1.25V
Output Load
See Output Load (A)
6
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED2ZL362MSJ
SNOOZE MODE
SNOOZE MODE is a low-current, power-down mode in
which the device is deselected and current is reduced to
I
SB
2
Z
. The duration of SNOOZE MODE is dictated by the
length of time Z is in a HIGH state. After the device en-
ters SNOOZE MODE, all inputs except ZZ become gated
inputs and are ignored. ZZ is an asynchronous, active
HIGH input that causes the device to enter SNOOZE
MODE.
When ZZ becomes a logic HIGH, I
SB
2
Z
is guaranteed af-
ter the setup time t
ZZ
is met. Any READ or WRITE op-
eration pending when the device enters SNOOZE MODE
is not guaranteed to complete successfully. Therefore,
SNOOZE MODE must not be initiated until valid pend-
ing operations are completed.
S
NOOZE
M
ODE
Description
Conditions
Symbol
Min
Max
Units
Notes
Current during SNOOZE MODE
ZZ VIH
I
SB2Z
10
mA
ZZ active to input ignored
t
ZZ
2(t
KC
)
ns
1
ZZ inactive to input sampled
t
RZZ
2(t
KC
)
ns
1
ZZ active to snooze current
t
ZZI
2(t
KC
)
ns
1
ZZ inactive to exit snooze current
t
RZZI
ns
1
FIG. 2 SNOOZE MODE TIMING DIAGRAM
ZZ
I
SUPPLY
CLOCK
ALL INPUTS
(except ZZ)
Output (Q)
t
ZZ
t
ZZI
t
RZZ
t
RZZI
HIGH-Z
DESELECT or READ Only
I
ISB2Z
DON'T CARE
7
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White Electronic Designs
WED2ZL362MSJ
Clock
CKE
Address
WRITE
ADV
OE
Data Out
t
CH
t
CL
t
CES
t
CEH
t
AS
t
AH
A1
A2
A3
t
WS
t
WH
t
CSS
t
CSH
t
OE
t
HZOE
t
LZOE
t
CD
t
OH
t
HZC
Q3-4
Q3-3
Q3-2
Q3-1
Q2-4
Q2-3
Q2-2
Q2-1
Q1-1
Don't Care
Undefined
t
CYC
t
ADVS
t
ADVH
CEx
NOTES:
WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
FIG. 3 TIMING WAVEFORM OF READ CYCLE
8
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White Electronic Designs
WED2ZL362MSJ
FIG. 4 TIMING WAVEFORM OF WRITE CYCLE
Clock
Address
WRITE
ADV
Data In
t
CH
t
CL
A2
A3
D2-1
D1-1
D2-2
D2-3
D2-4
D3-1
D3-2
D3-3
OE
Data Out
t
DS
t
DH
Don't Care
Undefined
t
CYC
CKE
A1
D3-4
t
CES
t
CEH
Q0-4
t
HZOE
Q0-3
CEx
NOTES:
WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
9
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WED2ZL362MSJ
FIG. 5 TIMING WAVEFORM OF SINGLE READ/WRITE
Cloc
Address
WRITE
ADV
OE
Data In
t
CH
t
CL
t
DS
t
DH
Data Out
A2
A4
A5
D2
t
OE
t
LZOE
Q1
Don't Care
Undefined
t
CYC
CKE
t
CES
t
CEH
A1
A3
A7
A6
Q3
Q4
Q7
Q6
D5
A9
A8
CEx
k
NOTES:
WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
10
White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED2ZL362MSJ
FIG. 6 TIMING WAVEFORM OF CKE OPERATION
Clock
Address
WRITE
ADV
OE
Data In
t
CH
t
CL
Data Out
A1
A2
A3
A4
A5
t
CES
t
CEH
Don't Care
Undefined
t
CYC
CKE
t
DS
t
DH
D2
Q4
Q1
t
CD
t
LZC
t
HZC
Q3
A6
CEx
NOTES:
WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
11
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White Electronic Designs
WED2ZL362MSJ
Clock
Address
WRITE
ADV
OE
Data In
t
CH
t
CL
Data Out
A1
A2
A3
A4
A5
Don't Care
Undefined
t
CYC
CKE
D5
Q4
t
CES
t
CEH
Q1
Q2
t
OE
t
LZOE
D3
t
CD
t
LZC
t
HZC
t
DH
t
DS
CEx
NOTES:
WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
FIG. 7 TIMING WAVEFORM OF CE OPERATION
12
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WED2ZL362MSJ
PACKAGE DIMENSION: 119 BUMP PBGA
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
2.50 (0.099)
MAX
0.600 (0.024)
MAX
1.27 (0.050)
TYP
1.27 (0.050) TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
14.00 (0.551) TYP
A1
CORNER
20.32 (0.800)
TYP
22.00 (0.866)
TYP
7.62 (0.300)
TYP
R 1.52 (0.060)
MAX (4x)
7
6
5
4
3
2
1
ORDERING INFORMATION
Commercial Temp Range (0C to 70C), Industrial Temp. Range (-40 to 85C)
Part Number
Configuration
t
CD
Clock
Operating
(ns)
(MHz)
Range
WED2ZL362MSJ35ES
2M x 36
3.5
166
Engineering Samples
WED2ZL362MSJ38ES
2M x 36
3.8
150
Engineering Samples
WED2ZL362MSJ28BC
2M x 36
2.8
225
Commercial
WED2ZL362MSJ30BC
2M x 36
3.0
200
Commercial
WED2ZL362MSJ35BC
2M x 36
3.5
166
Commercial
WED2ZL362MSJ38BC
2M x 36
3.8
150
Commercial
WED2ZL362MSJ30BI
2M x 36
3.0
200
Industrial
WED2ZL362MSJ35BI
2M x 36
3.5
166
Industrial
WED2ZL362MSJ38BI
2M x 36
3.8
150
Industrial
NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined.
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