WED3DG6435V-D1
-JD1
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2005
Rev. 5
256MB 32Mx64 SDRAM UNBUFFERED
PC100 and PC133 compatible
Burst
Mode
Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3V 0.3V Power Supply
144 Pin SO-DIMM JEDEC
Package height Option:
JD1: 31.75mm (1.25")
The WED3DG6435V is a 32Mx64 synchronous DRAM
module which consists of eight 32Mx8 SDRAM components
in TSOP II package, and one 2Kb EEPROM in an 8
pin TSOP package for Serial Presence Detect which
are mounted on a 144 pin SO-DIMM multilayer FR4
Substrate.
* This product is subject to change without notice.
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
DESCRIPTION
FEATURES
A0 A12
Address Input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CK0, CK1
Clock Input
CKE0
Clock Enable Input
CS0
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQMB0-7
DQM
V
CC
Power Supply (3.3V)
V
SS
Ground
SDA
Serial Data I/O
SCL
Serial Clock
DNU
Do Not Use
NC
No Connect
PIN NAMES
** These pins should be NC in the system which
does not support SPD.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PINOUT
PIN
FRONT
PIN
BACK
PIN
FRONT
PIN
BACK
PIN
BACK
PIN
BACK
1
V
SS
2
V
SS
49
DQ13
50
DQ45
97
DQ22
98
DQ54
3
DQ0
4
DQ32
51
DQ14
52
DQ46
99
DQ23
100
DQ55
5
DQ1
6
DQ33
53
DQ15
54
DQ47
101
V
CC
102
V
CC
7
DQ2
8
DQ34
55
V
SS
56
V
SS
103
A6
104
A7
9
DQ3
10
DQ35
57
NC
58
NC
105
A8
106
BA0
11
V
CC
12
V
CC
59
NC
60
NC
107
V
SS
108
V
SS
13
DQ4
14
DQ36
61
CK0
62
CKE0
109
A9
110
BA1
15
DQ5
16
DQ37
63
V
CC
64
V
CC
111
A10
112
A11
17
DQ6
18
DQ38
65
RAS#
66
CAS#
113
V
CC
114
V
CC
19
DQ7
20
DQ39
67
WE#
68
NC
115
DQMB2
116
DQMB6
21
V
SS
22
V
SS
69
CS0#
70
A12
117
DQMB3
118
DQMB7
23
DQMB0
24
DQMB4
71
NC
72
NC
119
V
SS
120
V
SS
25
DQMB1
26
DQMB5
73
NC
74
CK1
121
DQ24
122
DQ56
27
V
CC
28
V
CC
75
V
SS
76
V
SS
123
DQ25
124
DQ57
29
A0
30
A3
77
NC
78
NC
125
DQ26
126
DQ58
31
A1
32
A4
79
NC
80
NC
127
DQ27
128
DQ59
33
A2
34
A5
81
V
CC
82
V
CC
129
V
CC
130
V
CC
35
V
SS
36
V
SS
83
DQ16
84
DQ48
131
DQ28
132
DQ60
37
DQ8
38
DQ40
85
DQ17
86
DQ49
133
DQ29
134
DQ61
39
DQ9
40
DQ41
87
DQ18
88
DQ50
135
DQ30
136
DQ62
41
DQ10
42
DQ42
89
DQ19
90
DQ51
137
DQ31
138
DQ63
43
DQ11
44
DQ43
91
V
SS
92
V
SS
139
V
SS
140
V
SS
45
V
CC
46
V
CC
93
DQ20
94
DQ52
141
SDA
142
SCL
47
DQ12
48
DQ44
95
DQ21
96
DQ53
143
V
CC
144
V
CC
WED3DG6435V-D1
-JD1
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2005
Rev. 5
FUNCTIONAL BLOCK DIAGRAM
DQMB0
WE#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
S0#
DQM
WE#
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
WE#
DQM
S0#
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
WE#
DQM
S0#
WE#
DQM
S0#
DQ62
DQ63
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ47
DQ51
DQ55
DQ54
DQ53
DQ52
DQ49
DQ50
DQ48
DQ43
DQ45
DQ46
DQ44
DQ41
DQ42
DQ40
DQ39
DQ37
DQ38
DQ35
DQ36
DQ33
DQ34
DQ32
WE#
WE#
DQM
S0#
DQM
S0#
WE#
S0#
DQM
WE#
DQM
S0#
S0#
DQMB1
DQMB2
DQMB3
DQMB7
DQMB6
DQMB5
DQMB4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NOTE: DQ writing may differ than described in this drawing,
however DQ/DQMB/CKE/S relationships must be
maintained as shown.
V
SS
V
CC
A0
SCL
SDA
A2
A1
SERIAL PD
SDRAM
SDRAM
*CLOCK WIRING
CLOCK
INPUT
SDRAMS
*CK0
*CK1
4 - SDRAMS
4 - SDRAMS
*Wire per Clock Loading Table/Wiring Diagrams
CAS#
RAS#
CKE0
CKE0: SDRAM
CAS#: SDRAM
RAS#: SDRAM
A0-A12: SDRAM
A0-A12
BA0-BA1
BA0-BA1: SDRAM
Note: All resister values are 10 unless otherwise specifi ed.
WED3DG6435V-D1
-JD1
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2005
Rev. 5
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 ~ 4.6
V
Storage Temperature
T
STG
-55 ~ +150
C
Power Dissipation
P
D
9 W
Short Circuit Current
I
OS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
V
CC
3.0
3.3 3.6
V
Input High Voltage
V
IH
2.0
3.0
V
CCQ+0.3
V
1
Input Low Voltage
V
IL
-0.3
--
0.8
V
2
Output High Voltage
V
OH
2.4
--
--
V
I
OH
= -2mA
Output Low Voltage
V
OL
--
--
0.4
V
I
OL
= -2mA
Input Leakage Current
I
LI
-10
--
10
A
3
Note: 1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is 3ns.
2.
V
IL
(min)= -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V V
IN
V
CCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
T
A
= 25C, f = 1MHz, V
CC
= 3.3V, V
REF
= 1.4V 200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
36
pF
Input Capacitance (RAS#,CAS#,WE#)
C
IN2
36
pF
Input Capacitance (CKE0)
C
IN3
36
pF
Input Capacitance (CK0)
C
IN4
16
pF
Input Capacitance (CS0#)
C
IN5
36
pF
Input Capacitance (DQM0-DQM7)
C
IN6
7
pF
Input Capacitance (BA0-BA1)
C
IN7
36
pF
Data Input/Output Capacitance (DQ0-DQ63)
C
OUT
10
pF
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, T
A
= 0C to +70C
WED3DG6435V-D1
-JD1
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2005
Rev. 5
OPERATING CURRENT CHARACTERISTICS
V
CC
= 3.3V, T
A
= 0C to +70C
Version
Parameter
Symbol
Conditions
100/133
Units
Note
Operating Current
(One bank active)
I
CC1
Burst Length = 1
t
RC
t
RC
(min)
I
OL
= 0mA
1080
mA
1
Precharge Standby Current
in Power Down Mode
I
CC2P
CKE
V
IL
(max), t
CC
= 10ns
16
mA
Active Standby Current in
Non-Power Down Mode
I
CC3N
CKE
V
IH
(min), CS
V
IH
(min), tcc = 10ns Input
signals are changed one time during 20ns
360
mA
Operating Current (Burst mode)
I
CC4
Io = mA
Page burst
4 Banks activated
t
CCD
= 2CK
1,200
mA
1
Refresh Current
I
CC5
t
RC
t
RC
(min)
2,280
mA
2
Self Refresh Current
I
CC6
CKE
0.2V
24
mA
Notes:
1.
Measured with outputs open.
2.
Refresh period is 64ms.
WED3DG6435V-D1
-JD1
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2005
Rev. 5
AC TIMING PARAMETERS
Symbol
Parameter
Speed Grade
100MHz
Speed Grade
133MHz
Units
Notes
Min
Max
Min
Max
t
CK
Clock Period
10
7.5
ns
t
CH
Clock High Time Rated @1.5V
3
2.5
ns
t
CL
Clock Low Time
3
2.5
ns
t
IS
Input Setup Times
Address/ Command & CKE
2
1.5
ns
Data
2
1.5
ns
t
IH
Input Hold Times
Address/Command & CKE
1
0.8
ns
Data
1
0.8
ns
t
AC
Output Valid From Clock
CAS# Latency = 2 or 3,
LVTTL levels, Rated @ 50
pF all outputs switching
6.0
(tco = 5.2)
5.4
(tco = 4.6)
ns
1
t
OH
Output Hold From Clock Rated @ 50 pF (1.8 ns @ 0 pf)
3
2.7
ns
t
OHZ
Output Valid to Z
3
9
2.7
7
ns
t
CCD
CAS to CAS Delay
1
1
t
CK
t
CBD
CAS Bank Delay
1
1
t
CK
t
CKE
CKE to Clock Disable
1
1
t
CK
t
RP
RAS Precharge Time
20
20
ns
t
RAS
RAS Active Time
50
45
ns
t
RCD
Activate to Command Delay (RAS to CAS Delay)
20
20
ns
t
RRD
RAS to RAS Bank Activate Delay
20
15
ns
t
RC
RAS Cycle Time
70
67.5
ns
t
DQD
DQM to Input Data Delay
0
0
t
CK
t
DWD
Write Cmd. to Input Data Delay
0
0
t
CK
t
MRD
Mode Register set to Active delay
3
3
t
CK
t
ROH
Precharge to O/P in High Z
CL
CL
t
CK
2
t
DQZ
DQM to Data in High Z for read
2
2
t
CK
t
DQM
DQM to Data mask for write
0
0
t
CK
3
t
DPL
Data-in to PRE Command Period
20
15
ns
t
DAL
Data-in to ACT (PRE) Command period (Auto precharge)
5
5
t
CK
t
SB
Power Down Mode Entry
1
1
t
CK
t
SRX
Self Refresh Exit Time
10
10
ns
4
t
PDE
Power Down Exit Set up Time
1
1
t
CK
5
t
CKSTP
Clock Stop During Self Refresh or Power Down
200
200
t
CK
6
t
REF
Refresh Period
64
64
ms
t
RFC
Row Refresh Cycle Time
80.0
75.0
ns
1.
Access times to be measured w/input signals of 1 V/ns edge rate, 0.8 V to 2.0 V, tCO is clock to output with no load.
2.
CL = CAS Latency
3.
Data Masked on the same clock
4.
Self refresh Exit is asynchronous, requiring 10 ns to ensure initiation. Self refresh exit is complete in 10 ns + tRC.
5.
Timing is asynchronous. If tIS is not met by rising edge of CK then CKE is assumed latched on next cycle.
6.
If the clock is stopped during self refresh or power down, 200 clocks are required before CKE is high.
WED3DG6435V-D1
-JD1
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2005
Rev. 5
ORDERING INFORMATION FOR D1
Ordering Information
Speed
CAS Latency
Height*
WED3DG6435V10D1
100MHz
CL=2
31.75 (1.250")
WED3DG6435V7D1
133MHz
CL=2
31.75 (1.250")
WED3DG6435V75D1
133MHz
CL=3
31.75 (1.250")
NOTES:
Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
ORDERING INFORMATION FOR JD1
Ordering Information
Speed
CAS Latency
Height*
WED3DG6435V10JD1
100MHz
CL=2
31.75 (1.250")
WED3DG6435V7JD1
133MHz
CL=2
31.75 (1.250")
WED3DG6435V75JD1
133MHz
CL=3
31.75 (1.250")
NOTES:
Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
3.99
(0.157)
2.01 (0.079 Min)
67.72
(2.661 Max)
32.79
(1.291)
4.60 (0.181)
1.50 (0.059)
28.2
(1.112)
23.14
(0.913)
19.99
(0.787)
31.75
(1.250)
Max
3.81
(0.150)
MAX.
0.99
(0.039)
( 0.004)
PACKAGE DIMENSIONS FOR D1 AND JD1
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
WED3DG6435V-D1
-JD1
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2005
Rev. 5
Document Title
256MB 32Mx64 SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date
Status
Rev 0
Created Data sheet
6-4-03
Advanced
Rev 1
1.1 Updated Data sheet
3-3-04
Preliminary
Rev 2
2.1 Removed AD1 package option
2.2 Added JD1 package option
9-04
Preliminary
Rev 3
3.1 Added timing parameters
3.2 Moved from Preliminary to Final
3.3 Added D1 package option "Not Recommended for New
Designs"
9-04
Final
Rev 4
4.1 Added RoHS compliant notifi cation
4.2 Indicated vendor source options
4.3 Added industrial temperature option
7-05
Final
Rev 5
5.1 Added "ED" to part number
7-05
Final
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