1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DG6466V-D2
May 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
512MB 64Mx64, SDRAM UNBUFFERED
DESCRIPTION
The WED3DG6466V is a 64Mx64 synchronous DRAM
module which consists of eight 64Mx8 SDRAM com po nents
in TSOP II package and one 2K EEPROM in an 8 Pin
TSSOP package for Serial Presence Detect which are
mounted on a 168 Pin DIMM mul ti lay er FR4 Substrate.
* This product is subject to change without notice.
NOTE: Consult factory for availability of:
Lead-Free or RoHS Products
Vendor source control options
Industrial temperature option
FEATURES
PC100 and PC133 compatible
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
Available with "WP" Write Protect on Pin 81 option
WED3DG6366V-D2
3.3V 0.3V Power Supply
168 Pin DIMM JEDEC
PCB: 30.48 (1.20") MAX
PIN NAMES
A0 - A12
Address input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CBO-7
Check bit (Data-in/Data-out)
CK0,CK2
Clock input
CKE0#
Clock Enable input
CS0# - CS2#
Chip select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQM0-7
DQM
V
DD
Power Supply (3.3V)
V
SS
Ground
SDA
Serial data I/O
SCL
Serial clock
DNU
Do not use
NC
No Connect
WP
Write Protect
* These pins are not used in this module.
** These pins should be NC in the system which does not
support SPD.
*** WP available on the WED3DG6364V-D2 only
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
V
SS
29
DQM1
57
DQ18
85
V
SS
113
DQM5
141
DQ50
2
DQ0
30
CS0#
58
DQ19
86
DQ32
114
*CS1#
142
DQ51
3
DQ1
31
DNU
59
V
DD
87
DQ33
115
RAS#
143
V
DD
4
DQ2
32
V
SS
60
DQ20
88
DQ34
116
V
SS
144
DQ52
5
DQ3
33
A0
61
NC
89
DQ35
117
A1
145
NC
6
V
DD
34
A2
62
*VREF
90
NC
118
A3
146
*VREF
7
DQ4
35
A4
63
*CKE1
91
DQ36
119
A5
147
DNU
8
DQ5
36
A6
64
V
SS
92
DQ37
120
A7
148
V
SS
9
DQ6
37
A8
65
DQ21
93
DQ38
121
A9
149
DQ53
10
DQ7
38
A10/AP
66
DQ22
94
DQ39
122
BA0
150
DQ54
11
DQ8
39
BA1
67
DQ23
95
DQ40
123
A11
151
DQ55
12
V
SS
40
V
DD
68
V
SS
96
V
SS
124
V
DD
152
V
SS
13
DQ9
41
V
DD
69
DQ24
97
DQ41
125
*CK1
153
DQ56
14
DQ10
42
CK0
70
DQ25
98
DQ42
126
A12
154
DQ57
15
DQ11
43
V
SS
71
DQ26
99
DQ43
127
V
SS
155
DQ58
16
DQ12
44
DNU
72
DQ27
100
DQ44
128
CKE0
156
DQ59
17
DQ13
45
CS2#
73
V
DD
101
DQ45
129
CS3#
157
V
DD
18
V
DD
46
DQM2
74
DQ28
102
V
DD
130
DQM6
158
DQ60
19
DQ14
47
DQM3
75
DQ29
103
DQ46
131
DQM7
159
DQ61
20
DQ15
48
DNU
76
DQ30
104
DQ47
132
*A13
160
DQ62
21
*CBO
49
V
DD
77
DQ31
105
*CB4
133
V
DD
161
DQ63
22
*CB1
50
NC
78
V
SS
106
*CB5
134
NC
162
V
SS
23
Vss
51
NC
79
CK2
107
V
SS
135
NC
163
*CK3
24
NC
52
*CB2
80
NC
108
NC
136
*CB6
164
NC
25
NC
53
*CB3
81
***WP
109
NC
137
*CB7
165
**SA0
26
V
DD
54
V
SS
82
**SDA
110
V
DD
138
V
SS
166
**SA1
27
WE#
55
DQ16
83
**SCL
111
CAS#
139
DQ48
167
**SA2
28
DQM0
56
DQ17
84
V
DD
112
DQM4
140
DQ49
168
V
DD
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DG6466V-D2
May 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FUNCTIONAL BLOCK DIAGRAM
DQM1
DQM5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM
CS#
DQM0
CS0#
DQM4
DQM3
DQM2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM
CS#
CS2#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
CS#
DQM6
DQM7
V
CC
Vss
Two 0.1uF and one 0.22 uF Cap.
per each SDRAM
To all SDRAMs
DQn
Every DQpin of SDRAM
A0 ~ A12, BA0 & 1
CKE0
RAS#
CAS#
WE#
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDA
SCL
A1
A2
A0
SA1 SA2
SA0
WP
WP
CK1/3
10
10pF
SDRAM
SDRAM
10
10
CK0/2
SDRAM
SDRAM
1.5 pF
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DG6466V-D2
May 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 ~ 4.6
V
Storage Temperature
TSTG
-55 ~ +150
C
Power Dissipation
PD
8
W
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, 0C
T
A
+70C
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
V
CC
3.0
3.3 3.6
V
Input High Voltage
V
IH
2.0
3.0
V
CCQ
+0.3
V
1
Input Low Voltage
V
IL
-0.3
--
0.8
V
2
Output High Voltage
V
OH
2.4
--
--
V
I
OH
= -2mA
Output Low Voltage
V
OL
--
--
0.4
V
I
OL
= -2mA
Input Leakage Current
I
LI
-10
--
10
A
3
Note:
1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is 3ns.
2. V
IL
(min)= -2.0V AC. The undershoot voltage duration is 3ns.
3.
Any input 0V V
IN
V
CC
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
T
A
= 25C, f = 1MHz, V
CC
= 3.3V, V
REF
=1.4V
200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
40
pF
Input Capacitance (RAS#,CAS#,WE#)
C
IN2
40
pF
Input Capacitance (CKE0-CKE1)
C
IN3
40
pF
Input Capacitance (CK0-CK3)
C
IN4
30
pF
Input Capacitance (CS0#-CS3#)
C
IN5
25
pF
Input Capacitance (DQM0-DQM7)
C
IN6
10
pF
Input Capacitance (BA0-BA1)
C
IN7
40
pF
Data input/output capacitance (DQ0-DQ63)
C
OUT
10
pF
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DG6466V-D2
May 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
I
DD
SPECIFICATIONS AND CONDITIONS
V
CC
, V
CCQ
= +3.3V 0.3V; SDRAM component values only
PARAMETER/CONDITION
SYMBOL
MAX
UNITS
NOTES
7
7.5 & 10
OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; t
RC
= t
RC
(MIN)
I
DD1
1,600
1,440
mA
1
STANDBY CURRENT: Power-Down Mode; All device devicebanks idle; CKE = LOW
I
DD2
56
50
mA
STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active
after t
RCD
met; No accesses in progress
I
DD3
720
280
mA
OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device
banks active
I
DD4
1,600
1,360
mA
1
AUTO REFRESH CURRENT
t
RFC
= t
RFC
(MIN)
I
DD5
2,640
2,480
mA
2
CKE = HIGH; CS# = HIGH
t
RFC
= 7.8125s
I
DD6
96
96
mA
SELF REFRESH CURRENT: CKE < 0.2V
I
DD7
60
mA
Notes:
1. Measured with outputs open.
2. Refresh
period
is
64ms.
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DG6466V-D2
May 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
V
CC
, V
CCQ
= +3.3V 0.3V
AC CHARACTERISTICS
SYMBOL
7
7.5
10
UNITS
NOTE
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
Access timefrom CLK (pos.edge)
CL = 3
t
AC(3)
5.4
5.4
6
ns
27
CL = 2
t
AC(2)
5.4
6
6
ns
Address hold time
t
AH
0.8
0.8
1
ns
Address setup time
t
AS
1.5
1.5
2
ns
CLK high-level width
t
CH
2.5
2.5
3
ns
CLK low-level width
t
CL
2.5
2.5
3
ns
Clock cycle time
CL = 3
t
CK(3)
7
7.5
8
ns
23
CL = 2
t
CK(2)
7.5
10
10
ns
23
CKE hold time
t
CKH
0.8
0.8
1
ns
CKE setup time
t
CKS
1.5
1.5
2
ns
CS#, RAS#, CAS#, WE#, DQM hold time
t
CMH
0.8
0.8
1
ns
CS#, RAS#, CAS#, WE#, DQM setup time
t
CMS
1.5
1.5
2
ns
Data-in hold time
t
DH
0.8
0.8
1
ns
Data-in setup time
t
DS
1.5
1.5
2
ns
Data-out high-impedance time
CL = 3
t
HZ(3)
5.4
5.4
6
ns
10
CL = 2
t
HZ(2)
5.4
6
6
ns
10
Data-out low-impedance time
t
LZ
1
1
1
ns
Data-out hold time (load)
t
OH
2.7
2.7
2.7
ns
Data-out hold time (no load)
t
OHN
1.8
1.8
1.8
ns
28
ACTIVE to PRECHARGE command
t
RAS
37
120,000
44
120,000
50
120,000
ns
ACTIVE to ACTIVE command period
t
RC
60
66
66
ns
ACTIVE to READ or WRITE delay
t
RCD
15
20
20
ns
Refresh period
t
REF
64
64
64
ms
AUTOREFRESH period
t
RFC
66
66
66
ns
PRECHARGE command period
t
RP
15
20
20
ns
ACTIVE bank a to ACTIVE bank b command
t
RRD
14
15
15
ns
Transition time
t
T
0.3
1.2
0.3
1.2
0.3
1.2
ns
7
WRITE recovery time
t
WR
1 CLK
+
7ns
1 CLK
+
7.5ns
1 CLK
+
7.5ns
24
14
15
15
ns
25
Exit SELF REFRESH to ACTIVE command
t
XSR
67
75
80
ns
20
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DG6466V-D2
May 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
AC FUNCTIONAL CHARACTERISTICS
V
CC
, V
CCQ
= +3.3V 0.3V
PARAMETER
SYMBOL
7
7.5
10
UNITS
NOTES
READ/WRITE command to READ/WRITE command
t
CCD
1
1
1
t
CK
17
CKE to clock disable or power-down entry mode
t
CKED
1
1
1
t
CK
14
CKE to clock enable or power-down exit setup mode
t
PED
1
1
1
t
CK
14
DQM to input data delay
t
DQD
0
0
0
t
CK
17
DQM to data mask during WRITEs
t
DQM
0
0
0
t
CK
17
DQMto data high-impedance during READs
t
DQZ
2
2
2
t
CK
17
WRITE command to input data delay
t
DWD
0
0
0
t
CK
17
Data-into ACTIVE command
t
DAL
4
5
5
t
CK
15, 21
Data-into PRECHARGE command
t
DPL
2
2
2
t
CK
16, 21
Last data-in to burst STOP command
t
BDL
1
1
1
t
CK
17
Last data-in to new READ/WRITE command
t
CDL
1
1
1
t
CK
17
Lastdata-into PRECHARGE command
t
RDL
2
2
2
t
CK
16, 21
LOADMODEREGISTER command to ACTIVE or REFRESH command
t
MRD
2
2
2
t
CK
26
Data-out to high-impedance from PRECHARGE command
CL = 3
t
ROH(3)
3
3
3
t
CK
17
CL = 2
t
ROH(2)
2
2
2
t
CK
17
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DG6466V-D2
May 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
Notes
1.
All voltages referenced to V
SS
.
2.
This parameter is sampled. V
CC
, V
CCQ
= +3.3V; T
A
= 25C; pin under test biased
at 1.4V; f = 1 MHz.
3. I
DD
is dependent on output loading and cycle rates. Specifi ed values are obtained
with mini-mum cycle time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifi cations are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
6.
An initial pause of 100s is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (V
CC
and V
CCQ
must be powered up simultaneously. V
SS
and V
SSQ
must be at same potential.)
The two AUTO REFRESH command wake-ups should be repeated any time the
tREF refresh requirement is exceeded.
7.
AC characteristics assume t
T
= 1ns.
8.
In addition to meeting the transition rate specifi cation, the clock and CKE must
transit between V
IH
and V
IL
(or between V
IL
and V
IH
) in a mono-tonic manner.
9.
Outputs measured at 1.5V with equivalent load:
Q
50pF
10. t
HZ
defi nes the time at which the output achieves the open circuit condition; it is
not a reference to V
OH
or V
OL
. The last valid data element will meet t
OH
before
going High-Z.
11.
AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3V with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is
referenced at V
IL
(MAX) and V
IH
(MIN) and no longer at the 1.5V crossover point.
12.
Other input signals are allowed to transition no more than once every two clocks
and are other-wise at valid V
IH
or V
IL
levels.
13. I
DD
specifi cations are tested after the device is properly initialized.
14.
Timing actually specifi ed by t
CKS
; clock(s) specifi ed as a reference only at
minimum cycle rate.
15.
Timing actually specifi ed by t
WR
plus t
RP
; clock(s) specifi ed as a reference only at
minimum cycle rate.
16.
Timing actually specifi ed by t
WR
.
17.
Required clocks are specifi ed by JEDEC functionality and are not dependent on
any timing parameter.
18. The
I
DD
current will increase or decrease proportionally according to the amount
of frequency alteration for the test condition.
19.
Address transitions average one transition every two clocks.
20.
CLK must be toggled a minimum of two times during this period.
21.
Based on t
CK
= 10ns for 10, and t
CK
= 7.5ns for 7 and 7.5.
22. V
IH
overshoot: V
IH
(MAX) = V
CCQ
+ 2V for a pulse width 3ns, and the pulse
width cannot be greater than one third of the cycle rate. V
IL
under-shoot: V
IL
(MIN) = -2V for a pulse width 3ns.
23.
The clock frequency must remain constant (stable clock is defi ned as a signal
cycling within timing constraints specifi ed for the clock pin) during access or
precharge states (READ, WRITE, including t
WR
, and PRECHARGE commands).
CKE may be used to reduce the data rate.
24.
Auto precharge mode only. The precharge timing budget (t
RP
) begins 7ns for 7;
7.5ns for 7.5 and 7.5ns for 10 after the fi rst clock delay, after the last WRITE is
executed. May not exceed limit set for precharge mode.
25. Precharge
mode
only.
26.
JEDEC and PC133, PC100 specify three clocks.
27. t
AC
for 7/7.5 at CL = 3 with no load is 4.6ns and is guaranteed by design.
28.
Parameter guaranteed by design.
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DG6466V-D2
May 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
*ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
PACKAGE DIMENSIONS
ORDERING INFORMATION
Part Number
Speed
CAS Latency
Height*
WED3DG6366V10D2
100MHz
CL=2
30.48 (1.20")
WED3DG6366V7D2
133MHz
CL=2
30.48 (1.20")
WED3DG6366V75D2
133MHz
CL=3
30.48 (1.20")
NOTE: Available with "WP" Write Protect on pin 81.
Part Number
Speed
CAS Latency
Height*
WED3DG6466V10D2
100MHz
CL=2
30.48 (1.20")
WED3DG6466V7D2
133MHz
CL=2
30.48 (1.20")
WED3DG6466V75D2
133MHz
CL=3
30.48 (1.20")
NOTES:
Consult Factory for availability of Lead-Free or RoHS products. (F = Lead-Free,
G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components
source control. The place holder for this is shown as lower case "x" in the
part numbers above and is to be replaced with the respective vendors code.
Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung &
consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
3.99
(0.157)
(2X)
8.89
(0.350)
6.35
(0.250)
P1
11.43
(0.450)
3.18
(0.125) (2X)
133.48
(5.255 MAX.)
115.57
(4.550)
6.35
(0.250)
54.61
(2.150)
1.27 0.10
(0.050 0.004)
3.99
(0.157)
MIN.
2.54
(0.100)
MAX.
30.48
(1.200)
MAX.
17.78
(0.700)
42.16
(1.660)
36.83
(1.450)
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DG6466V-D2
May 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
Document Title
512MB 64Mx64, SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date
Status
Rev A
Created
4-10-02
Advanced
Rev B
Corrected mechanical drawing
5-1-02
Advanced
Rev 0
Changed from Advanced to Final
8-19-02
Final
Rev 1
1.1 Updated I
DD
specs
1.2 Added AC and notes
1.3 Added lead-free and RoHS notes
1.4 Added source control notes
1.5 Added industrial temperature options
5-05
Final
PDF 
ZIP