1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15460
WED3DG72127V-D2
1GB- 128Mx72 SDRAM W/ PLL, REGISTER AND SPD
n Burst Mode Operation
n Auto and Self Refresh capability
n LVTTL compatible inputs and outputs
n Serial Presence Detect with EEPROM
n Fully synchronous: All signals are registered on the positive
edge of the system clock
n Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
n 3.3 volt 6 0.3v Power Supply
n 168- Pin DIMM JEDEC
The WED3DG72127V is a 128Mx72 synchronous DRAM module
which consists of eighteen 128Mx4 SDRAM components in TSOP-
11 package, two 18- bit Drive ICs for input control signal and one
2K EEPROM in an 8- pin TSSOP package for Serial Presence
Detect which are mounted on a 168 Pin DIMM multilayer FR4
Substrate.
DESCRIPTION
FEATURES
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
VSS
29
DQM1
57
DQ18
85
VSS
113
DQM5
141
DQ50
2
DQ0
30
CS0
58
DQ19
86
DQ32
114
CS1
142
DQ51
3
DQ1
31
DNU
59
VDD
87
DQ33
115
RAS
143
VDD
4
DQ2
32
VSS
60
DQ20
88
DQ34
116
VSS
144
DQ52
5
DQ3
33
A0
61
NC
89
DQ35
117
A1
145
NC
6
VDD
34
A2
62
*VREF
90
VDD
118
A3
146
*VREF
7
DQ4
35
A4
63
*CKE1
91
DQ36
119
A5
147
REGE
8
DQ5
36
A6
64
VSS
92
DQ37
120
A7
148
VSS
9
DQ6
37
A8
65
DQ21
93
DQ38
121
A9
149
DQ53
10
DQ7
38
A10/AP
66
DQ22
94
DQ39
122
BA0
150
DQ54
11
DQ8
39
BA1
67
DQ23
95
DQ40
123
A11
151
DQ55
12
VSS
40
VDD
68
VSS
96
VSS
124
VDD
152
VSS
13
DQ9
41
VDD
69
DQ24
97
DQ41
125
*CLK1
153
DQ56
14
DQ10
42
CLK0
70
DQ25
98
DQ42
126
A12
154
DQ57
15
DQ11
43
VSS
71
DQ26
99
DQ43
127
VSS
155
DQ58
16
DQ12
44
DNU
72
DQ27
100
DQ44
128
CKE0
156
DQ59
17
DQ13
45
CS2
73
VDD
101
DQ45
129
CS3
157
VDD
18
VDD
46
DQM2
74
DQ28
102
VDD
130
DQM6
158
DQ60
19
DQ14
47
DQM3
75
DQ29
103
DQ46
131
DQM7
159
DQ61
20
DQ15
48
DNU
76
DQ30
104
DQ47
132
*A13
160
DQ62
21
CB0
49
VDD
77
DQ31
105
CB4
133
VDD
161
DQ63
22
CB1
50
NC
78
VSS
106
CB5
134
NC
162
VSS
23
VSS
51
NC
79
*CLK2
107
VSS
135
NC
163
*CLK3
24
NC
52
CB2
80
NC
108
NC
136
CB6
164
NC
25
NC
53
CB3
81
NC
109
NC
137
CB7
165
**SA0
26
VDD
54
VSS
82
**SDA
110
VDD
138
VSS
166
**SA1
27
WE
55
DQ16
83
**SCL
111
CAS
139
DQ48
167
**SA2
28
DQM0
56
DQ17
84
VDD
112
DQM4
140
DQ49
168
VDD
A0 A12
Address input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CB0-7
Check bit (Data-in/data-out)
CLK0
Clock input
CKE0
Clock Enable input
CS0,CS2
Chip select Input
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
DQM0-7
DQM
VDD
Power Supply (3.3V)
VSS
Ground
*VREF
Power supply for reference
REGE
Register enable
SDA
Serial data I/O
SCL
Serial clock
SA0-2
Address in EEPROM
DNU
Do not use
NC
No Connect
* These pins are not used in this module.
** These pins should be NC in the system which
does not support SPD.
* This datasheet describes a product that may or may not be under development
and is subject to change or cancellation without notice.
2
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15460
WED3DG72127V-D2
FUNCTIONAL BLOCK DIAGRAM
REGE
PCK
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
0
I/O
DQM CS
1
I/O
2
I/O
3
I/O
D0
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
CS0
D1
D2
D3
DQMB0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
D9
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
D10
D11
D12
DQMB4
DQMB1
DQMB5
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
D5
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
D6
D7
D8
DQMB2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
D14
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
D15
D16
D17
DQMB6
DQMB3
DQMB7
VCC
VSS
D0 - D35
D0 - D35
CB0
CB1
CB2
CB3
DQM CS
I/O 0
I/O 1
I/O 2
I/O 3
D4
CB4
CB5
CB6
CB7
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
D13
# NOTE: ALL RESISTOR VALUES ARE 10 OHMS.
NOTE: DQ wiring may differ than described in
this drawing, however DQ/DQMB/CKE/S
relationships must be maintained as shown.
RAS: SDRAMS D0 - D35
CAS: SDRAMS D0 - D35
CKE: SDRAMS D0 - D17
WE: SDRAMS D0 - D35
CS0-CS2
DQMB0 to DQMB7
BA0-BA1
A0-A12
RAS
CAS
CKE0
WE
RS0-RS2
RDQMB0 - RDQMB7
RRAS
RCAS
RCKE0
RWE
CS2
RBA0 - RBAN
RA0-RAN
BA0-BAN: SDRAMS D0-D35
A0-AN: SDRAMS D0-D35
A0
SERIAL PD
A1
A2
SA0
SA1
SA2
SCL
SDA
E
G
I
S
T
E
R
R
CK1-CK3
PLL
12pF
CK0
SDRAM
REGISTER
12pF
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15460
WED3DG72127V-D2
(Voltage Referenced to: V
SS
= 0V, T
A
= 0C to +70C)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
V
IN
, Vout
-1.0 ~ 4.6
V
Voltage on VDD supply relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Storage Temperature
TSTG
-55 ~ +150 C
Power Dissipation
PD
36
W
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
VDD
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
3.0 VDDQ+0.3 V
1
Input Low Voltage
VIL
-0.3
0.8
V
2
Output High Voltage
VOH
2.4
V
IOH= -2mA
Output Low Voltage
VOL
0.4
V
IOL= -2mA
Input Leakage Current
ILI
-10
10
A
3
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is 3ns.
2. VIL (min)= -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V VIN VDDQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State
outputs.
CAPACITANCE
(T
A
= 23C, f = 1MHz, V
DD
= 3.3V, VREF=1.4V 6200mV)
Parameter
Symbol
Min
Max
Unit
Input Capacitance (A0-A12)
CIN1
-
15
pF
Input Capacitance (RAS,CAS,WE)
CIN2
-
15
pF
Input Capacitance (CKE0)
CIN3
-
15
pF
Input Capacitance (CLK0)
CIN4
-
20
pF
Input Capacitance (CS0,CS2)
CIN5
-
15
pF
Input Capacitance (DQM0-DQM7)
CIN6
-
15
pF
Input Capacitance (BA0-BA1)
CIN7
-
15
pF
Data input/output capacitance (DQ0-DQ63)
Cout
-
22
pF
Data input/output capacitance (CB0-CB7)
Cout1
-
22
pF
4
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15460
WED3DG72127V-D2
OPERATING CURRENT CHARACTERISTICS
(V
CC
= 3.3V, T
A
= 0C to +70C)
Notes: 1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1 PLL & 2 Drive ICs.
Version
Parameter
Symbol
Conditions
133
100
Units Note
Operating Current
ICC1
Burst Length = 1
2,880
2,700
mA
1
(One bank active)
tRC tRC(min)
IOL = 0mA
Precharge Standby Current
ICC2P
CKE VIL(max), tCC = 10ns
110
mA
3
in Power Down Mode
ICC2PS
CKE & CLK VIL(max), tCC =
90
Icc2N
CKE VIH(min), CS VIH(min), tcc = 10ns
Precharge Standby Current
Input signals are charged one time during 20
540
in Non-Power Down Mode
Icc2NS
CKE VIH(min), CLK VIL(max), tcc =
mA
3
Input signals are stable
180
Active standby current in
ICC3P
CKE VIL(max), tCC = 10ns
180
mA
3
power-down mode
ICC3PS
CKE & CLK VIL(max), tcc =
145
ICC3N
CKE VIH(min), CS VIH(min), tcc = 10ns
Active standby current in
Input signals are changed one time during 20ns 900
mA
3
non power-down mode
ICC3NS
CKE VIH(min), CLK VIL(max), tcc =
input signals are stable
630
mA
3
Io = mA
Operating current (Burst mode)
ICC4
Page burst
3,420
2,880
mA
1
4 Banks activated
tCCD = 2CLK
Refresh current
ICC5
tRC tRC(min)
5,940
5,580
mA
2
Self refresh current
ICC6
CKE 0.2V
130
mA
3
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15460
WED3DG72127V-D2
ALL DIMENSIONS ARE IN INCHES
PACKAGE DIMENSIONS
ORDERING INFORMATION
Part Number
Speed
CAS Latency
WED3DG72127V10D2
100MHz
CL=2
WED3DG72127V7D2
133MHz
CL=2
WED3DG72127V75D2
133MHz
CL=3
6
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15460
WED3DG72127V-D2
REV.
DATE
REQUESTED BY
DETAILS
A
3-26-02
PAUL MARIEN
CREATED
0
9-19-02
PAUL MARIEN
-CHANGED FROM ADVANCED
TO FINAL
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