1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED7PxxxATA70xxI25
July 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FEATURES
ATA
Compatibility
3.3V or 5.0V single power supply.
68 pin two piece connector with Type-2 form
factor (5mm thickness)
Support for CIS implementation with 256 bytes of
attribute memory
Interface
modes
PC card memory mode
PC card I/O mode
True IDE mode
High
performance
Interface Transfer speed in PIO mode 4 or Multi
Word DMA mode 2 cycle timing, 16.6 Mbytes/
second (theoretical)
Sustained write: max 6.0 Mbytes/s in ATA PIO
mode 4 cycle timing
Sustained read: max 6.5 Mbytes/s in ATA PIO
mode 4 cycle timing
W/E Endurance: 100,000cycles
1
/300,000cycles
2
Notes:
1.
T
A
= -40 to 85C
2. T
A
= 0 to 70C
DESCRIPTION
The WED7PxxxATA70xxI25 series ATA card is an ATA
interface fl ash memory card based on fl ash technology.
The ATA card is constructed with a fl ash disk controller
chip and NAND-type fl ash memory device. Operates
from a single 5-Volt or 3.3-Volt power source. The card is
available in ATA type-2 form factor with 128MB, 256MB,
128MB to 1GB Industrial ATA Flash
512MB and 1.02GB unformatted capacity. Being able
to emulate IDE hard disk drives, WEDC's ATA card is a
perfect choice for solid-state mass-storage in industrial
applications and applications that require performance
and extended environmental tolerances.
Dimensions:
Type 2 card: 85.6mm(L) x 54.0mm (W) x 5.03mm (H)
Lead free and RoHS compliant
Storage
Capacities:
128MB, 256MB, 512MB and 1.02GB (unformatted)
Operating
Voltage:
3.3V
5%
5.0V 0.5V
Power
consumption:
5V operation
Active
mode:
Write operation: 28 mA (Typ.)
Read operation: 23 mA (Typ.)
Power down mode: 1.2mA (Typ.) 2.0mA (max.)
3.3V operation
Active
mode:
Write operation: 25 mA (Typ.)
Read operation: 21 mA (Typ.)
Power down mode: 1.0mA (Typ.) 1.5mA (max.)
Environment
conditions:
Operating temperature: -40C to 85C
Storage temperature: -45C to 90C
Storage humidity: 95% (max) (No condensation)
* This product is subject to change without notice.
PRODUCT TYPES
Card Density
Model No.
Cylinder
Head
Sector
Memory capacity
1
128MB
7P128ATA70xxI25
978
8
32
128,188,416 Byte
256MB
7P256ATA70xxI25
978
16
32
256,376,832 Byte
512MB
7P512ATA70xxI25
993
16
63
512,483,328 Byte
1.02GB
7P1G0ATA70xxI25
1985
16
63
1024,450,560 Byte
1: It is the logical address capacity including the area used for File System.
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED7PxxxATA70xxI25
July 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
PIN ASSIGNMENTS AND PIN TYPE
Pin #
Memory card mode
I/O Card Mode
True IDE Mode
Signal Name
I/O
Signal Name
I/O
Signal Name
I/O
1
GND
GND
GND
2
D3
I/O
D3
I/O
D3
I/O
3
D4
I/O
D4
I/O
D4
I/O
4
D5
I/O
D5
I/O
D5
I/O
5
D6
I/O
D6
I/O
D6
I/O
6
D7
I/O
D7
I/O
D7
I/O
7
CE1#
I
CE1#
I
CE1#
I
8
A10
I
A10
I
A10
I
9
OE#
I
OE#
I
ATASEL#
I
10
N.C.
N.C.
N.C.
11
A9
I
A9
I
A9
I
12
A8
I
A8
I
A8
I
13
N.C.
N.C.
N.C.
14
N.C.
N.C.
N.C.
15
WE#
I
WE#
I
WE#
I
16
RDY/BSY
O
IREQ#
O
INTRQ
O
17
Vcc
Vcc
Vcc
18
N.C.
N.C.
N.C.
19
N.C.
N.C.
N.C.
20
N.C.
N.C.
N.C.
21
N.C.
N.C.
N.C.
22
A7
I
A7
I
A7
I
23
A6
I
A6
I
A6
I
24
A5
I
A5
I
A5
I
25
A4
I
A4
I
A4
I
26
A3
I
A3
I
A3
I
27
A2
I
A2
I
A2
I
28
A1
I
A1
I
A1
I
29
A0
I
A0
I
A0
I
30
D0
I/O
D0
I/O
D0
I/O
31
D1
I/O
D1
I/O
D1
I/O
32
D2
I/O
D2
I/O
D2
I/O
33
WP
O
IOIS16#
O
IOIS16#
O
34
GND
GND
GND
Pin #
Memory card mode
I/O Card Mode
True IDE Mode
Signal Name
I/O
Signal Name
I/O
Signal Name
I/O
35
GND
GND
GND
36
CD1#
O
CD1#
O
CD1#
O
37
D11
I/O
D11
I/O
D11
I/O
38
D12
I/O
D12
I/O
D12
I/O
39
D13
I/O
D13
I/O
D13
I/O
40
D14
I/O
D14
I/O
D14
I/O
41
D15
I
D15
I
D15
I
42
CE2#
I
CE2#
I
CE2#
I
43
VS1
O
VS1
O
VS1
O
44
IORD#
I
IORD#
I
IORD#
I
45
IOWR#
I
IOWR#
I
IOWR#
I
46
NC
NC
NC
47
NC
NC
NC
48
NC
NC
NC
49
NC
NC
NC
50
NC
NC
NC
51
Vcc
Vcc
Vcc
52
NC
NC
NC
53
NC
NC
NC
54
NC
NC
NC
55
NC
NC
NC
56
CSEL#
I
CSEL#
I
CSEL#
I
57
VS2
O
VS2
O
VS2
O
58
RESET
I
RESET
I
RESET#
I
59
Wait#
O
Wait#
O
IORDY
O
60
INPACK#
O
INPACK#
O
INPACK#
O
61
REG#
I
REG#
I
REG#
I
62
BVD2
I/O
SPKR#
I/O
DASP
I/O
63
BVD1
I/O
STSCHG#
I/O
PDIAG#
I/O
64
D8
I/O
D8
I/O
D8
I/O
65
D9
I/O
D9
I/O
D9
I/O
66
D10
O
D10
O
D10
O
67
CD2#
O
CD2#
O
CD2#
O
68
GND
GND
GND
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED7PxxxATA70xxI25
July 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ACCESS SPECIFICATIONS
1. Attribute access specifi cations
When CIS-ROM region or Confi guration register region is accessed, read and write operations are executed under the
condition of REG# = "L" as follows. That region can be accessed by Byte/Word/Odd-byte modes, which are defi ned by
PC card standard specifi cations.
Attribute Read Access Mode
Mode
REG#
CE2#
CE1#
A0
OE#
WE#
D8 to D15
D0 to D7
Standby mode
X
H
H
X
X
X
High-Z
High-Z
Byte access (8bit)
L
H
L
L
L
H
High-Z
even byte
L
H
L
H
L
H
High-Z
Invalid
Word access (16bit)
L
L
L
X
L
H
invalid
even byte
Odd byte access (8bit)
L
L
H
X
L
H
invalid
High-Z
Note: X L or H
Attribute Write Access Mode
Mode
REG#
CE2#
CE1#
A0
OE#
WE#
D8 to D15
D0 to D7
Standby mode
X
H
H
X
X
X
Don't care
Don't care
Byte access (8bit)
L
H
L
L
H
L
Don't care
even byte
L
H
L
H
H
L
Don't care
Don't care
Word access (16bit)
L
L
L
X
H
L
Don't care
even byte
Odd byte access (8bit)
L
L
H
X
H
L
Don't care
Don't care
Note: X L or H
Write CIS-ROM region is invalid.
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED7PxxxATA70xxI25
July 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
2. Task File register access specifi cations
There are two types of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address
area. Each type of Task File register read and write operation is executed under the condition as follows. That area can
be accessed by Byte/Word/Odd Byte modes, which are defi ned by PC card standard specifi cations.
(1) I/O address map Task File Register Read Access Mode (1)
Mode
REG#
CE2#
CE1#
A0
IORD#
IOWR#
OE#
WE#
D8 to D15
D0 to D7
Standby mode
X
H
H
X
X
X
X
X
High-Z
High-Z
Byte access (8bit)
L
H
L
L
L
H
H
H
High-Z
even byte
L
H
L
H
L
H
H
H
High-Z
odd byte
Word access (16bit)
L
L
L
X
L
H
H
H
odd byte
even byte
Odd byte access (8bit)
L
L
H
X
L
H
H
H
odd byte
High-Z
Note: X L or H
Task File Register Write Access Mode (1)
Mode
REG#
CE2#
CE1#
A0
IORD#
IOWR#
OE#
WE#
D8 to D15
D0 to D7
Standby mode
X
H
H
X
X
X
X
X
Don't care
Don't care
Byte access (8bit)
L
H
L
L
H
L
H
H
Don't care
even byte
L
H
L
H
H
L
H
H
Don't care
odd byte
Word access (16bit)
L
L
L
X
H
L
H
H
odd byte
even byte
Odd byte access (8bit)
L
L
H
X
H
L
H
H
odd byte
Don't care
Note: X L or H
(2) Memory address map Task File Register Read Access Mode (2)
Mode
REG#
CE2#
CE1#
A0
OE#
WE#
IORD#
IOWR#
D8 to D15
D0 to D7
Standby mode
X
H
H
X
X
X
X
X
High-Z
High-Z
Byte access (8bit)
H
H
L
L
L
H
H
H
High-Z
even byte
H
H
L
H
L
H
H
H
High-Z
odd byte
Word access (16bit)
H
L
L
X
L
H
H
H
odd byte
even byte
Odd byte access (8bit)
H
L
H
X
L
H
H
H
odd byte
High-Z
Note: X L or H
Task File Register Write Access Mode (2)
Mode
REG#
CE2#
CE1#
A0
OE#
WE#
IORD#
IOWR#
D8 to D15
D0 to D7
Standby mode
X
H
H
X
X
X
X
X
Don't care
Don't care
Byte access (8bit)
H
H
L
L
H
L
H
H
Don't care
even byte
H
H
L
H
H
L
H
H
Don't care
odd byte
Word access (16bit)
H
L
L
X
H
L
H
H
odd byte
even byte
Odd byte access (8bit)
H
L
H
X
H
L
H
H
odd byte
Don't care
Note: X L or H
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED7PxxxATA70xxI25
July 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
3. TRUE IDE MODE
The card can be confi gured in a True IDE. This card is confi gured in this mode only when the OE# input signal is asserted
to GND by the host during power on . In this True IDE mode Attribute Registers are not accessible from the host. Only
I/O operation to the task fi le and data register is allowed. If this card is confi gured during power on sequence, data
register is accessed in word (16-bit). The card permits 8-bit accesses if the user issues a Set Feature Command to put
the device in 8-bit mode.
True IDE Mode Read I/O Function
Mode
CE2#
CE1#
A0~A2
DMACK#
DIOR#
DIOW#
D8~D15
D0~D7
Invalid mode
L
L
X
X
X
X
High-Z
High-Z
Standby mode
H
H
X
H
X
X
High-Z
High-Z
PIO Data register access
H
L
0
H
L
H
Odd byte
even byte
Multiword DMA Data register access
H
H
X
L
L
H
Odd byte
even byte
Alternate status access
L
H
6H
H
L
H
High-Z
Status out
Other task fi le access
H
L
1~7H
H
L
H
High-Z
Data
Note: X L or H
True IDE Mode Write I/O Function
Mode
CE2#
CE1#
A0~A2
DMACK#
DIOR#
DIOW#
D8~D15
D0~D7
Invalid mode
L
L
X
X
X
X
Don't care
Don't care
Standby mode
H
H
X
H
X
X
Don't care
Don't care
PIO Data register access
H
L
0
H
H
L
Odd byte
even byte
Multiword DMA Data register access
H
H
X
L
H
L
Odd byte
even byte
Control register access
L
H
6H
H
H
L
Don't care
Control in
Other task fi le access
H
L
1~7H
H
H
L
Don't care
Data
Note: X L or H
CARD SYSTEM PERFORMANCE
ITEM
PERFORMANCE
Set up time (Reset to Ready)
250 ms (max.)
Set up time (Power down to Ready)
5.5 ms (max.)
Data transfer rate to / from host
16.6 M byte / s burst (max.), theoretically
Sustained read transfer rate
6.5 M byte / s (max.), actually *1
Sustained write transfer rate
6.0 M byte / s (max.), actually *1
Command to DRQ (Sector Re ad at Ready state)
4 ms (max.)
Command to DRQ (Sector Write at Ready state)
700 ms (max.)
Data transfer cycle end to ready (Sector write)
2 ms (typ.), 200 ms (max.)
Auto Power down time
1.5s (min.), 1.8s (typ.)
Notes:
1. The actual transfer rate is measured under ATA PIO mode 4 with single cycle time as 120ns.
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