1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED8L24513V
Aug. 2002 Rev. 0A
ECO #15432
FIG. 1
P
IN
N
AMES
BLOCK DIAGRAM
PIN SYMBOLS
PIN CONFIGURATION
Asynchronous SRAM, 3.3V, 512Kx24
FEATURES
n 512Kx24 bit CMOS Static
n Random Access Memory Array
Fast Access Times: 10, 12, and 15ns
Master Output Enable and Write Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
n Surface Mount Package
119 Lead BGA (JEDEC MO-163), No. 391
Small Footprint, 14mmx22mm
Multiple Ground Pins for Maximum Noise Immunity
n Single +3.3V (5%) Supply Operation
n DSP Memory Solution
Motorola DSP5630x
Analog Devices SHARC
TM
DESCRIPTION
The WED8L24513VxxBC is a 3.3V, twelve megabit SRAM con-
structed with three 512Kx8 die mounted on a multi-layer laminate
substrate. With 10 to 15ns access times, x24 width and a 3.3V
operating voltage, the WED8L24513V is ideal for creating a single
chip memory solution for the Motorola DSP5630x (Figure 8) or a
two chip solution for the Analog Devices SHARC
TM
DSP (Figure
9).
The single or dual chip memory solutions offer improved system
performance by reducing the length of board traces and the
number of board connections compared to using multiple mono-
lithic devices.
The JEDEC Standard 119 lead BGA provides a 61% space
savings over using three 512Kx8, 400 mil wide SOJs and the BGA
package has a maximum height of 110 mils compared to 148 mils
for the SOJ packages.
A
0-18
Address Inputs
E
Chip Enable
W
Master Write Enable
G
Master Output Enable
DQ
0-23
Common Data Input/Output
VCC
Power (3.3V 5%)
GND
Ground
NC
No Connection
1
2
3
4
5
6
7
A
NC
AO
A1
A2
A3
A4
NC
B
NC
A5
A6
E
A7
A8
NC
C
I/012
NC
NC
NC
NC
NC
I/00
D
I/013
VCC
GND
GND
GND
VCC
I/01
E
I/014
GND
VCC
GND
VCC
GND
I/02
F
I/015
VCC
GND
GND
GND
VCC
I/03
G
I/016
GND
VCC
GND
VCC
GND
I/04
H
I/017
VCC
GND
GND
GND
VCC
I/05
J
NC
GND
VCC
GND
VCC
GND
NC
K
I/018
VCC
GND
GND
GND
VCC
I/06
L
I/019
GND
VCC
GND
VCC
GND
I/07
M
I/020
VCC
GND
GND
GND
VCC
I/08
N
I/021
GND
VCC
GND
VCC
GND
I/09
P
I/022
VCC
GND
GND
GND
VCC
I/010
R
I/023
A18
NC
NC
NC
A17
I/011
T
NC
A9
A10
W
A11
A12
NC
UNC
A13
A14
G
A15
A16
NC
512K x 24
Memory
Array
19
A
0
-A
18
G
W
E
DQ
0
-
7
DQ
8-15
DQ
16-23
2
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Aug. 2002 Rev. 0A
ECO #15432
WED8L24513V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
NOTE: For TEHQZ,TGHQZ and TWLQZ, Figure 3
ABSOLUTE MAXIMUM RATINGS
AC TEST CONDITIONS
RECOMMENDED DC OPERATING CONDITIONS
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
Figure 2
Voltage on any pin relative to VSS
-0.5V to 4.6V
Operating Temperature TA (Ambient)
Commercial
0C to + 70C
Industrial
-40C to +85C
Storage Temperature
-55C to +125C
Power Dissipation
1.5 Watts
Output Current.
50 mA
Parameter
Sym
Min
Typ
Max Units
Supply Voltage
VCC
3.135
3.3
3.465
V
Supply Voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.2
-- VCC+0.3 V
Input Low Voltage
VIL
-0.3
--
0.8
V
FIG. 2
FIG. 3
(f=1.0MHz, VIN=VCC or VSS)
These parameters are sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
TRUTH TABLE
CAPACITANCE
G
E
W
Mode
Output
Power
X
H
X
Standby
High Z
ICC2,ICC3
H
L
H
Output Deselect
High Z
ICC1
L
L
H
Read
DOUT
ICC1
X
L
L
Write
DIN
ICC1
353
5 pF
D
OUT
319
VCC
R
L
= 50
V
L
= 1.5V
Q
Z0 = 50
Z
0
= 50
65 pF
Parameter
Sym
Conditions
Min
Max
Units
10ns
12-15ns
Operating Power Supply Current
ICC1
W= VIL, II/O = 0mA,
450
350
mA
Min Cycle
Standby (TTL) Supply Current
ICC2
E > VIH, VIN < VIL or
150
150
mA
VIN > VIH, f=MHz
Full Standby CMOS
ICC3
E > VCC-0.2V
90
90
mA
Supply Current
VIN > VCC-0.2V or
VIN < 0.2V
Input Leakage Current
ILI
VIN = 0V to VCC
10
10
A
Output Leakage Current
ILO
V I/O = 0V to VCC
10
10
A
Output High Volltage
VOH
IOH = -4.0mA
2.4
V
Output Low Voltage
VOL
IOL = 4.0mA
0.4
0.4
V
Parameter
Sym
Max
Unit
Address Lines
CA
8
pF
Data Lines
CD/Q
10
pF
Write & Output Enable Lines
W, G
8
pF
Chip Enable Lines
E-E2
8
pF
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED8L24513V
Aug. 2002 Rev. 0A
ECO #15432
AC CHARACTERISTICS READ CYCLE
Symbol
10ns
12ns
15ns
Parameter
JEDEC
Alt.
Min Max
Min Max
Min Max
Units
Read Cycle Time
TAVAV
TRC
10
12
15
ns
Address Access Time
TAVQV
TAA
10
12
15
ns
Chip Enable Access Time
TELQV
TACS
10
12
15
ns
Chip Enable to Output in Low Z (1)
TELQX
TCLZ
3
3
3
ns
Chip Disable to Output in High Z (1)
TEHQZ
TCHZ
5
6
7
ns
Output Hold from Address Change
TAVQX
TOH
3
3
3
ns
Output Enable to Output Valid
TGLQV
TOE
5
6
7
ns
Output Enable to Output in Low Z (1)
TGLQX
TOLZ
0
0
0
ns
Output Disable to Output in High Z(1) TGHQZ
TOHZ
5
6
7
ns
FIG. 4
READ CYCLE 1 - W HIGH, G, E LOW
FIG. 5
READ CYCLE 2 - W HIGH
A
Q
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
AVAV
t
EHQZ
t
GHQZ
G
E
NOTE 1: Parameter is guaranteed, but not tested.
A
Q
t
AVQX
t
AVQV
t
AVAV
DATA 2
ADDRESS 1
ADDRESS 2
DATA 1
4
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Aug. 2002 Rev. 0A
ECO #15432
WED8L24513V
NOTE 1: Parameter is guaranteed, but not tested.
AC CHARACTERISTICS WRITE CYCLE
FIG. 6
WRITE CYCLE 1 - W CONTROLLED
A
D
t
AVWH
t
ELWH
t
WHAX
t
WLWH
t
DVWH
t
WLQZ
t
WHQX
t
AVWL
t
WHDX
t
AVAV
DATA VALID
HIGH Z
W
E
Q
Symbol
10ns
12ns
15ns
Parameter
JEDEC
Alt.
Min
Max
Min Max
Min Max Units
Write Cycle Time
TAVAV
TWC
10
12
15
ns
Chip Enable to End of Write
TELWH
TCW
8
9
9
ns
TELEH
TCW
8
9
9
ns
Address Setup Time
TAVWL
TAS
0
0
0
ns
TAVEL
TAS
0
0
0
ns
Address Valid to End of Write
TAVWH
TAW
8
9
10
ns
TAVEH
TAW
8
9
10
ns
Write Pulse Width
TWLWH
TWP
8
10
11
ns
TWLEH
TWP
8
10
11
ns
Write Recovery Time
TWHAX
TWR
0
0
0
ns
TEHAX
TWR
0
0
0
ns
Data Hold Time
TWHDX
TDH
0
0
0
ns
TEHDX
TDH
0
0
0
ns
Write to Output in High Z (1)
TWLQZ TWHZ
0
5
0
6
0
7
ns
Data to Write Time
TDVWH
TDW
6
6
7
ns
TDVEH
TDW
6
6
7
ns
Output Active from End of Write (1)TWHQX TWLZ
3
3
3
ns
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED8L24513V
Aug. 2002 Rev. 0A
ECO #15432
FIG. 7
WRITE CYCLE 2 - E CONTROLLED
Commercial (0C to +70C)
Industrial (-40C to +85C)
ORDERING INFORMATION
Part Number
Speed
Package
(ns)
No.
WED8L24513V10BC
10
391
WED8L24513V12BC
12
391
WED8L24513V15BC
15
391
Part Number
Speed
Package
(ns)
No.
WED8L24513V12BI
12
391
WED8L24513V15BI
15
391
PACKAGE NO. 391
119 LEAD BGA
JEDEC MO-163
A
D
t
AVEH
t
ELEH
t
EHAX
t
DVEH
t
EHDX
t
AVAV
DATA VALID
HIGH Z
W
t
WLEH
E
Q
t
AVEL
0.110 MAX
0.711 (0.028)
MAX
1.27 (0.050)
TYP
1.27 (0.050) TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
14.00 (0.551) TYP
A1
CORNER
20.32 (0.800)
TYP
22.00 (0.866)
TYP
7.62 (0.300)
TYP
R 1.52 (0.062)
MAX (4x)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
6
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Aug. 2002 Rev. 0A
ECO #15432
WED8L24513V
FIG. 8
INTERFACING THE MOTOROLA DSP5630x DSP FAMILY WITH THE WED8L24513V (512K x 24)
Address Bus
A
23-0
Databus
D
23-0
Motorola
DSP5630x
WED8L24513V
(512K x 24)
AA
0
AA
1
AA
2
AA
3
WR
RD
A
18-0
E
W
G
DQ
0-23
WED8L24513V
(512K x 24)
A
18-0
E
W
G
DQ
0-23
WED8L24513V
(512K x 24)
A
18-0
E
W
G
DQ
0-23
Notes:
1. In this example three 512K x 24 external memory
arrays are shown, one for X data, one for Y data and
one for Program. Specific applications may require
one, two, or all three arrays.
2. Any combination of AA0-AA3 may be used as chip
selects. However, each chip select may only be used
to select one memory array.
Address Bus
A
31-0
Databus
D
47-0
Analog
ADSP-2106xL
WED8L24513V
(512K x 24)
MS
X
WR
RD
A
18-0
E
W
G
DQ
16-23
DQ
8-15
DQ
0-7
WED8L24513V
(512K x 24)
A
18-0
E
W
G
DQ
16-23
DQ
8-15
DQ
0-7
FIG. 9
INTERFACING THE ANALOG DEVICES 2106xL DSP FAMILY WITH THE WED8L24513V (512K x
24)
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