1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED8L24514V
1
2
3
4
5
6
7
A
NC
A
O
A
1
A
2
A
3
A
4
NC
B
NC
A
5
A
6
E
0
A
7
A
8
NC
C
I/0
12
NC
E
2
NC
E
3
NC
I/0
0
D
I/0
13
V
CC
GND
GND
GND
V
CC
I/0
1
E
I/0
14
GND
V
CC
GND
V
CC
GND
I/0
2
F
I/0
15
V
CC
GND
GND
GND
V
CC
I/0
3
G
I/0
16
GND
V
CC
GND
V
CC
GND
I/0
4
H
I/0
17
V
CC
GND
GND
GND
V
CC
I/0
5
J
NC
GND
V
CC
GND
V
CC
GND
NC
K
I/0
18
V
CC
GND
GND
GND
V
CC
I/0
6
L
I/0
19
GND
V
CC
GND
V
CC
GND
I/0
7
M
I/0
20
V
CC
GND
GND
GND
V
CC
I/0
8
N
I/0
21
GND
V
CC
GND
V
CC
GND
I/0
9
P
I/0
22
V
CC
GND
GND
GND
V
CC
I/0
10
R
I/0
23
A
18
NC
NC
NC
A
17
I/0
11
T
NC
A
9
A
10
W
A
11
A
12
NC
U
NC
A
13
A
14
G
A
15
A
16
NC
September 2001 Rev. 2
ECO #14670
FIG. 1
PIN N
AMES
BLOCK DIAGRAM
P
IN
S
YMBOLS
PIN CONFIGURATION
Asynchronous SR
Asynchronous SR
Asynchronous SR
Asynchronous SR
Asynchronous SRAM, 3.3V
AM, 3.3V
AM, 3.3V
AM, 3.3V
AM, 3.3V, 512Kx24
, 512Kx24
, 512Kx24
, 512Kx24
, 512Kx24
FEATURES
n
512Kx24 bit CMOS Static
n
Random Access Memory Array
Fast Access Times: 10, 12, and 15ns
Master Output Enable and Write Control
Three Chip Enables for Byte Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
n
Surface Mount Package
119 Lead BGA (JEDEC MO-163), No. 391
Small Footprint, 14mmx22mm
Multiple Ground Pins for Maximum Noise Immunity
n
Single +3.3V (5%) Supply Operation
n
DSP Memory Solution
Motorola DSP5630x
Analog Devices SHARC
TM
DESCRIPTION
The WED8L24514VxxBC is a 3.3V, twelve megabit SRAM
constructed with three 512Kx8 die mounted on a multi-
layer laminate substrate. With 10 to 15ns access times, x24
width and a 3.3V operating voltage, the WED8L24514V is
ideal for creating a single chip memory solution for the
Motorola DSP5630x or a two chip solution for the Analog
Devices SHARC
TM
DSP.
The single or dual chip memory solutions offer improved
system per formance by reducing the length of board
traces and the number of board connections compared
to using multiple monolithic devices.
The JEDEC Standard 119 lead BGA provides a 61%
space savings over using three 512Kx8, 400 mil wide
SOJs and the BGA package has a maximum height of 110
mils compared to 148 mils for the SOJ packages.
A
0-18
Address Inputs
E
Chip Enable
W
Master Write Enable
G
Master Output Enable
DQ
0-23
Common Data Input/Output
V
CC
Power (3.3V 5%)
GND
Ground
NC
No Connection
512K x 24
Memory
Array
19
A
0
-A
18
G
W
E
0
E
2
E
3
DQ
0
-
7
DQ
8-15
DQ
16-23
2
White Electronic Designs Corporation Westborough, MA (508) 366-5151
WED8L24514V
Parameter
Sym
Max
Unit
Address Lines
CA
8
pF
Data Lines
CD/Q
10
pF
Write & Output Enable Lines
W, G
8
pF
Chip Enable Lines
E
, E
2
, E
3
8
pF
*Stress greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
NOTE: For t
EHQZ
,t
GHQZ
and t
WLQZ
, Figure 3
ABSOLUTE
MAXIMUM
RATINGS
AC
TEST
CONDITIONS
RECOMMENDED
DC
OPERATING
CONDITIONS
Input Pulse Levels
V
SS
to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
Figure 2
Voltage on any pin relative to V
SS
-0.5V to 4.6V
Operating Temperature T
A
(Ambient)
Commercial
0C to + 70C
Industrial
-40C to +85C
Storage Temperature
-55C to +125C
Power Dissipation
1.5 Watts
Output Current.
50 mA
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
V
CC
3.135
3.3
3.465
V
Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
--
V
CC
+0.3
V
Input Low Voltage
V
IL
-0.3
--
0.8
V
FIG. 2
FIG. 3
(f=1.0MH
Z
, V
IN
=V
CC
OR
V
SS
)
These parameters are sampled, not 100% tested.
DC
ELECTRICAL
CHARACTERISTICS
T
RUTH
T
ABLE
C
APACITANCE
G
E0
E2
E3
W
Mode
Output
Power
X
H
H
H
X
Standby
High Z
I
CC
2
,I
CC
3
H
L
L
L
H
Output Deselect
High Z
I
CC
1
L
L
L
L
H
Read (24 bit)
D
OUT
I
CC
1
L
L
H
H
H
Read
DQ
0-7
I
CC
1
L
H
L
H
H
Read
DQ
8-15
I
CC
1
L
H
H
L
H
Read
DQ
16-23
I
CC
1
X
L
L
L
L
Write (24 bit)
D
IN
I
CC
1
X
L
H
H
L
Write
DQ
0-7
I
CC
1
X
H
L
H
L
Write
DQ
8-15
I
CC
1
X
H
H
L
L
Write
DQ
16-23
I
CC
1
353
5 pF
D
OUT
319
VCC
R
L
= 50
V
L
= 1.5V
Q
Z0 = 50
Z
0
= 50
65 pF
Parameter
Sym
Conditions
Min
Max
Units
10ns
12 - 15ns
Operating Power Supply Current
I
CC
1
W= V
IL
, II/O = 0mA,
450
350
mA
Min Cycle
Standby (TTL) Supply Current
I
CC
2
E > V
IH
, V
IN
< V
IL
or
150
150
mA
V
IN
> V
IH
, f=MHz
Full Standby CMOS
I
CC
3
E > V
CC
- 0.2V
90
90
mA
Supply Current
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V
Input Leakage Current
I
LI
VIN = 0V to V
CC
10
10
A
Output Leakage Current
I
LO
V I/O = 0V to V
CC
10
10
A
Output High Volltage
V
OH
I
OH
= -4.0mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 4.0mA
0.4
0.4
V
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED8L24514V
AC CHARACTERISTICS READ CYCLE
Symbol
10ns
12ns
15ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
t
AVAV
t
RC
10
12
15
ns
Address Access Time
t
AVQV
t
AA
10
12
15
ns
Chip Enable Access Time
t
ELQV
t
ACS
10
12
15
ns
Chip Enable to Output in Low Z
1
t
ELQX
t
CLZ
3
3
3
ns
Chip Disable to Output in High Z
1
t
EHQZ
t
CHZ
5
6
7
ns
Output Hold from Address Change
t
AVQX
t
OH
3
3
3
ns
Output Enable to Output Valid
t
GLQV
t
OE
5
6
7
ns
Output Enable to Output in Low Z
1
t
GLQX
t
OLZ
0
0
0
ns
Output Disable to Output in High Z
1
t
GHQZ
t
OHZ
5
6
7
ns
FIG. 4 READ CYCLE 1 - W HIGH, G, E LOW
FIG. 5 READ CYCLE 2 - W HIGH
A
Q
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
AVAV
t
EHQZ
t
GHQZ
G
E
A
Q
t
AVQX
t
AVQV
t
AVAV
DATA 2
ADDRESS 1
ADDRESS 2
DATA 1
NOTE 1: Parameter is guaranteed, but not tested.
4
White Electronic Designs Corporation Westborough, MA (508) 366-5151
WED8L24514V
NOTE 1: Parameter is guaranteed, but not tested.
AC CHARACTERISTICS WRITE CYCLE
FIG. 6 WRITE CYCLE 1 - W CONTROLLED
A
D
t
AVWH
t
ELWH
t
WHAX
t
WLWH
t
DVWH
t
WLQZ
t
WHQX
t
AVWL
t
WHDX
t
AVAV
DATA VALID
HIGH Z
W
E
Q
Symbol
10ns
12ns
15ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
t
AVAV
t
WC
10
12
15
ns
Chip Enable to End of Write
t
ELWH
t
CW
8
9
9
ns
t
ELEH
t
CW
8
9
9
ns
Address Setup Time
t
AVWL
t
AS
0
0
0
ns
t
AVEL
t
AS
0
0
0
ns
Address Valid to End of Write
t
AVWH
t
AW
8
9
10
ns
t
AVEH
t
AW
8
9
10
ns
Write Pulse Width
t
WLWH
t
WP
8
10
11
ns
t
WLEH
t
WP
8
10
11
ns
Write Recovery Time
t
WHAX
t
WR
0
0
0
ns
t
EHAX
t
WR
0
0
0
ns
Data Hold Time
t
WHDX
t
DH
0
0
0
ns
t
EHDX
t
DH
0
0
0
ns
Write to Output in High Z
1
t
WLQZ
t
WHZ
0
5
0
6
0
7
ns
Data to Write Time
t
DVWH
t
DW
5
6
7
ns
t
DVEH
t
DW
5
6
7
ns
Output Active from End of Write
1
t
WHQX
t
WLZ
3
3
3
ns
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED8L24514V
FIG. 7 WRITE CYCLE 2 - E CONTROLLED
Commercial (0C to +70C)
Industrial (-40C to +85C)
ORDERING INFORMATION
Part Number
Speed
Package
(ns)
No.
WED8L24514V10BC
10
391
WED8L24514V12BC
12
391
WED8L24514V15BC
15
391
Part Number
Speed
Package
(ns)
No.
WED8L24514V12BI
12
391
WED8L24514V15BI
15
391
PACKAGE NO. 391
119 LEAD BGA
JEDEC MO-163
A
D
t
AVEH
t
ELEH
t
EHAX
t
DVEH
t
EHDX
t
AVAV
DATA VALID
HIGH Z
W
t
WLEH
E
Q
t
AVEL
PDF 
ZIP