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Электронный компонент: WED9LAPC2C16V8BC

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1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
July, 2000
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
The WED9LAPC2C16V8BC is a 3.3V, 512K x 32
Synchronous Pipeline SRAM and a 1M x 64 Synchronous
DRAM array packaged in a 21mm x 21mm 192 lead
BGA.
The WED9LAPC2C16V8BC provides the memory
required for the CRAM (Control Memory) and VCRAM
(Virtual Connection Memory) memory ports for Lucent's
LUCTAPC640 ATM port controller. When used in conjunction
with the WED9LAPC2B16P8BC, which provides memory for
the BRAM (Buffer Memory) and PRAM (Pointer Memory)
memory ports, the entire memory requirement of the
LUCTAPC640 can be met using these 2 BGA devices.
The WED9LAPC2C16V8BC is 100% tested to the timing
requirements of the LUCTAPC640's memory interface
timing for both Commercial and Industrial temperature
ranges.
512K x 32 SSRAM / 1M x 64 SDRAM
EXTERNAL MEMORY SOLUTION FOR LUCENT'S LUCTAPC640 ATM PORT CONTROLLER
Clock speeds:
SSRAM: 100 MHz
SDRAM: 100 MHz
100% tested to timing requirements of
LUCTAPC640's memory interface
Packaging:
192 pin BGA, 21mm x 21mm
3.3V Operating supply voltage
Direct control interface to both the CRAM and
VCRAM ports on the LUCTAPC640
62% space savings vs. monolithic solution
Reduced system inductance and capacitance
PIN CONFIGURATION
PINOUT CRAM AND VCRAM MCM -- TOP VIEW
July 2000 Rev. 0
ECO #15168
FEATURES
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
CADDR
CADDR
V
CC
CDATA
CDATA
V
SS
CDATA
CDATA
V
CC
CDATA
CDATA
V
SS
CDATA
CDATA
V
CC
CADDR
B
CWE#
CADDR
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CADDR
CADDR
C
COE#
CADDR
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CADDR
CADDR
D
V
SS
CADDR
CADDR
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
CC
V
CC
V
CC
V
SS
CADDR
CADDR
CADDR
E
GCK
V
SS
NC
V
CC
V
SS
CADDR
CADDR
CADDR
F
V
SS
VCDATA_b
VCDATA_b
V
CC
V
CC
CADDR0
CADDR1
V
SS
G
VCDATA_b
VCDATA_b
VCDATA_b
V
SS
V
CC
VCDATA_a VCDATA_a VCDATA_a
H
VCDATA_b
VCDATA_b
VCDATA_b
V
SS
V
SS
VCDATA_a VCDATA_a VCDATA_a
J
V
CC
VCDATA_b
VCDATA_b
V
SS
V
SS
VCDATA_a VCDATA_a
V
CC
K
VCDATA_b
VCDATA_b
VCDATA_b
V
CC
V
SS
VCDATA_a VCDATA_a VCDATA_a
L
VCDATA_b
VCDATA_b
VCDATA_b
V
CC
V
CC
VCDATA_a VCDATA_a VCDATA_a
M
V
SS
VCDATA_b
VCDATA_b
V
CC
V
CC
VCDATA_a VCDATA_a
V
SS
N
VCDATA_b
VCDATA_b
VCDATA_b
V
SS
V
SS
V
SS
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
CC
V
CC
VCDATA_a VCDATA_a
P
VCDATA_b
VCDATA_b
VCDATA_b
VCDATA_b
VCDATA_b
V
SS
VCADDR0 VCADDR2
VCADDR10
VCADDR6
V
SS
VCDATA_a
VCDATA_a VCDATA_a VCDATA_a VCDATA_a
R
V
CC
VCDATA_b
VCDATA_b
VCDATA_b
VCBS
VCADDR8 VCADDR1 VCADDR3
VCADDR4
VCADDR7
VCDATA_a
VCDATA_a
VCDATA_a VCDATA_a VCDATA_a
V
CC
T
VCDATA_b
VCDATA_b
V
SS
VCDATA_b
VCDQM
VCCAS#
VCWE#
VCRAS#
VCADDR5
VCADDR9/AP
V
CC
VCDATA_a
VCDATA_a
V
SS
VCDATA_a VCDATA_a
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
July, 2000
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
FIG. 1 BLOCK DIAGRAM 512K X 32 SSRAM / 1M X 64
CDATA0-31
CADDR0-18
GCLK
CWE#
COE#
VCADDR0-10
VCBS
VCDQM
VCRAS#
VCCAS#
VCWE#
512K x 32 SBSRAM
ADDR0-18
CK
GW#
OE#
DQ0-7
DQ8-15
DQ16-23
DQ24-31
512K x 32 x 2 SDRAM
ADDR
DQM0#
DQM1#
DQM2#
DQ0-15
DQ16-31
DQM3#
RAS#
CAS#
WE#
CK
BA
512K x 32 x 2 SDRAM
ADDR
DQM0#
DQM1#
DQM2#
DQ0-15
DQ16-31
DQM3#
RAS#
CAS#
WE#
CK
BA
VCDATA32-63
VCDATA0-63
VCDATA0-31
PIN CONFIGURATION (CONTINUED)
PIN DESCRIPTION
Symbol
Pin Name
Description
CADDR
CRAM Address
Address pins for the SSRAM that serves as the control RAM (CRAM)
CDATA
CRAM Data
Data I/O pins for the SSRAM control memory (CRAM)
CWE#
CRAM write enable
Write enable control for the SSRAM control memory (CRAM)
COE#
CRAM output enable
Output enable control pin for the SSRAM control memory (CRAM)
VCADDR
VCRAM address
Address pins for the SDRAM memory that serves as the virtual connection memory (VCRAM)
VCDATA
VCRAM data
Data I/O pins for the SDRAM virtual connection memory (VCRAM)
VCBS
VCRAM bank select
Bank address pin for the SDRAM virtual connection memory (VCRAM)
VCDQM
VCRAM DQM
DQM (data mask) pin for the SDRAM virtual conection memory (VCRAM)
VCRAS#
VCRAM row address strobe
RAS# pin for the SDRAM virtual connection memory (VCRAM)
VCCAS#
VCRAM column address strobe
CAS# pin for the SDRAM virtual connection memory (VCRAM)
VCWE#
VCRAM write enable
Write enable pin for the SDRAM virtual connection memory (VCRAM)
GCK
Global clock
Common clock pin for both the CRAM and VCRAM memory arrays
V
CC
Power supply
Power supply pins
V
SS
Ground
Ground Pins
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
July, 2000
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Voltage on V
CC
Relative to V
SS
-0.5V to +4.6V
Vin (DQx)
-0.5V to Vcc +0.5V
Storage Temperature (BGA)
-55C to +125C
Junction Temperature
+125C
Short Circuit Output Current
50 mA
DC ELECTRICAL CHARACTERISTICS
BGA CAPACITANCE
Description
Conditions
Symbol
Typ
Max
Units
Operating Current
CRAM and VCRAM active
I
CC1
400
500
mA
Operating Current
CRAM active/VCRAM inactive
I
CC2
350
390
mA
Operating Current
CRAM inactive/VCRAM active
I
CC3
270
330
mA
Operating Current
CRAM inactive/VCRAM inactive
I
CC4
150
180
mA
SSRAM AC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
Clock Cycle Time
t
KHKH
7.5
ns
Clock HIGH Time
t
KLKH
3.0
ns
Clock LOW Time
t
KHKL
3.0
ns
Clock to output valid
t
KHQV
4.2
ns
Clock to output invalid
t
KHQX
1.5
ns
Clock to output in Low-Z
t
KQLZ
1.5
ns
Clock to output in High-Z
t
KQHZ
1.5
3.5
ns
Output Enable to output valid
t
OELQV
4.2
ns
Output Enable to output in Low-Z
t
OELZ
0
ns
Output Enable to output in High-Z
t
OEHZ
3.5
ns
Address, Control, Data-in Setup Time to Clock
t
S
1.5
ns
Address, Control, Data-in Hold Time to Clock
t
H
0.5
ns
Parameter
Symbol
Min
Max
Units
Supply Voltage (1)
V
CC
3.135
3.465
V
Input High Voltage (1,2)
V
IH
2.0
V
CC
+0.3
V
Input Low Voltage (1,2)
V
IL
-0.3
0.8
V
Input Leakage Current
0 - V
IN
- Vcc
I
LI
-10
10
A
Output Leakage (Output Disabled)
0 - V
IN
- Vcc
I
LO
-10
10
A
CRAM Output High (I
OH
= -4mA) (1)
V
OH
2.4
--
V
CRAM Output Low (I
OL
= 8mA) (1)
V
OL
--
0.4
V
VCRAM Output High (I
OH
= -2mA) (1)
V
OH
2.4
--
V
VCRAM Output Low (I
OL
= 2mA) (1)
V
OL
--
0.4
V
Description
Conditions
Symbol
Typ
Max
Units
Address Input Capacitance
1
T
A
= 25C; f = 1MHz
C
I
5
8
pF
Input/Output Capacitance (DQ)
1
T
A
= 25C; f = 1MHz
C
O
8
10
pF
Control Input Capacitance
1
T
A
= 25C; f = 1MHz
C
A
5
8
pF
Clock Input Capacitance
1
T
A
= 25C; f = 1MHz
C
CK
4
6
pF
(0C T
A
70C; V
CC
= 3.3V 5% unless otherwise noted)
NOTES:
1.
All voltages referenced to V
SS
(GND).
2.
Overshoot: V
IH
+6.0V for t t
KC/2
Undershoot: V
IL
-2.0V for t t
KC/2
NOTE:
1.
This parameter is sampled.
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
July, 2000
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
FIG. 2 SSRAM READ TIMING
GCK
CADDR
COE#
CWE#
CDATA
A1
A2
A3
A4
A5
t
KHKH
t
KHKL
t
KLKH
t
S
t
H
t
OELQV
t
OEHQZ
t
KQLZ
t
KHQX
t
KHQV
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Q(A5)
SSRAM OPERATION TRUTH TABLE
Operation
Address Used
CWE#
COE#
CDATA
WRITE Cycle, Begin Burst
External
L
X
D
READ Cycle, Begin Burst
External
H
L
Q
READ Cycle, Begin Burst
External
H
H
High-Z
NOTE:
1.
X means "don't care", H means logic HIGH. L means logic LOW.
2.
All inputs except SSOE# must meet setup and hold times around the rising edge (LOW to
HIGH) of SSCLK.
3.
For a write operation following a read operation, SSOE# must be HIGH before the input data
required setup time plus High-Z time for SSOE# and staying HIGH thoughout the input data
hold time.
4.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
July, 2000
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
FIG. 3 SSRAM WRITE TIMING
GCK
CADDR
COE#
CWE#
CDATA
A1
A2
A3
A4
A5
D(A1)
D(A2)
D(A3)
D(A4)
D(A5)
t
KHKH
t
KHKL
t
KLKH
t
S
t
H
t
S
t
H
t
S
t
H
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
July, 2000
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
CLOCK FREQUENCY AND LATENCY PARAMETERS
(Unit = number of clock)
R
EFRESH
C
YCLE
P
ARAMETERS
SDRAM AC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
Clock Cycle Time
1
CL = 3
t
CC
8
1000
ns
CL = 2
t
CC
10
1000
ns
Clock to valid Output delay
1,2
t
SAC
6
ns
Output Data Hold Time
2
t
OH
2.5
ns
Clock HIGH Pulse Width
3
t
CH
3
ns
Clock LOW Pulse Width
3
t
CL
3
ns
Input Setup Time
3
t
SS
2
ns
Input Hold Time
3
t
SH
1
ns
CK to Output Low-Z
2
t
SLZ
1
ns
CK to Output High-Z
t
SHZ
6
ns
Row Active to Row Active Delay
4
t
RRD
16
ns
RAS# to CAS# Delay
4
t
RCD
20
ns
Row Precharge Time
4
t
RP
20
ns
Row Active Time
4
t
RAS
48
10,000
ns
Row Cycle Time - Operation
4
t
RC
70
ns
Row Cycle Time - Auto Refresh
4,8
t
RFC
70
ns
Last Data in to New Column Address Delay
5
t
CDL
1
CK
Last Data in to Row Precharge
5
t
RDL
2
CK
Last Data in to Burst Stop
5
t
BDL
1
CK
Column Address to Column Address Delay
6
t
CCD
1
CK
Number of Valid Output Data
7
2
ea
1
ea
Parameter
Symbol
Min
Max
Units
Refresh Period
1,2
t
REF
--
64
ms
Cycle
Time
CAS
Latency
t
RC
t
RAS
t
RP
t
RRD
t
RCD
t
CCD
t
CDL
t
RDL
70ns
48ns
20ns
16ns
20ns
10ns
10ns
10ns
8.0ns
3
9
6
3
2
3
1
1
2
10.0ns
2
7
5
2
2
2
1
1
2
NOTES:
1.
Parameters depend on programmed CAS latency.
2.
If clock rise time is longer than 1ns (t
RISE
/2 -0.5)ns should be added to the parameter.
3.
Assumed input rise and fall time = 1ns. If trise of t
FALL
are longer than 1ns. [(t
RISE
= t
FALL
)/2] - 1ns should be added to the parameter.
4.
The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer.
5.
Minimum delay is required to complete write.
6.
All devices allow every cycle column address changes.
7.
In case of row precharge interrupt, auto precharge and read burst stop.
8.
A new command may be given t
RFC
after self-refresh exit.
NOTES:
1.
1024 cycles
2.
Any time that the Refresh Period has been exceeded, a minimum of two
Auto (CBR) Refresh commands must be given to "wake-up" the device.
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
July, 2000
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
SDRAM COMMAND TRUTH TABLE
NOTES:
1. All of the SDRAM operations are defined by states of VCWE#, VCRAS#, VCCAS#, and VCDQM# at the positive rising edge of the clock.
2. Bank Select (VCBS), if VCBS = 0 then bank A is selected, if VCBS = 1 then bank B is selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The VCDQM# has two functions for the data DQ Read and Write operations. During a Read cycle, when VCDQM# goes high at a clock timing the
data outputs are disabled and become high impedance after a two clock delay. VCDQM# also provides a data mask function for Write cycles. When
it activates, the Write operation at the clock is prohibited (zero clock latency).
FUNCTION
VCRAS# VCCAS#
VCWE#
VCDQM#
VCBS
VCADDR
NOTES
Mode Register Set
L
L
L
X
OP CODE
Auto Refresh (CBR)
L
L
H
X
X
X
Precharge
Single Bank
L
H
L
X
BA
L
2
Precharge all Banks
L
H
L
X
X
H
Bank Activate
L
H
H
X
BA
Row Address
2
Write
H
L
L
X
BA
L
2
Write with Auto Precharge
H
L
L
X
BA
H
2
Read
H
L
L
X
BA
L
2
Read with Auto Precharge
H
L
H
X
BA
H
2
Burst Termination
H
H
L
X
X
X
3
No Operation
H
H
H
X
X
X
Data Write/Output Disable
X
X
X
L
X
X
4
Data Mask/Output Disable
X
X
X
H
X
X
4
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
July, 2000
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Current State
Command
Action
Notes
VCRAS# VCCAS# VCWE# VCBS
VCADDR
Description
Idle
L
L
L
OP Code
Mode Register Set
Set the Mode Register
1
L
L
H
X
X
Auto or Self Refresh
Start Auto
1
L
H
L
X
X
Precharge
No Operation
L
H
H
BA
Row Address
Bank Activate
Activate the specified bank and row
H
L
L
BA
Column
Write w/o Precharge
ILLEGAL
2
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
1
H
H
L
X
X
Burst Termination
No Operation
1
H
H
H
X
X
No Operation
No Operation
Row Active
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
X
Precharge
Precharge
3
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
1
H
L
L
BA
Column
Write
Start Write; Determine if Auto Precharge
4,5
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
4,5
H
H
L
X
X
Burst Termination
No Operation
H
H
H
X
X
No Operation
No Operation
Read
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
L
BA
Column
Write
Terminate Burst; Start the Write cycle
5,6
H
L
H
BA
Column
Read
Terminate Burst; Start a new Read cycle
5,6
H
H
L
X
X
Burst Termination
Terminate the Burst
H
H
H
X
X
No Operation
Continue the Burst
Write
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
L
BA
Column
Write
Terminate Burst; Start a new Write cycle
5,6
H
L
H
BA
Column
Read
Terminate Burst; Start the Read cycle
5,6
H
H
L
X
X
Burst Termination
Terminate the Burst
H
H
H
X
X
No Operation
Continue the Burst
Read with
Auto Precharge
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
X
Precharge
ILLEGAL
2
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
L
BA
Column
Write
ILLEGAL
H
L
H
BA
Column
Read
ILLEGAL
H
H
L
X
X
Burst Termination
ILLEGAL
H
H
H
X
X
No Operation
Continue the Burst
SDRAM CURRENT STATE TRUTH TABLE
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
July, 2000
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Current State
Command
Action
Notes
VCRAS# VCCAS#
VCWE#
VCBS
VCADDR
Description
Write with
Auto Precharge
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
X
Precharge
ILLEGAL
2
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
L
BA
Column
Write
ILLEGAL
H
L
H
BA
Column
Read
ILLEGAL
H
H
L
X
X
Burst Termination
ILLEGAL
H
H
H
X
X
No Operation
Continue the Burst
Precharging
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
X
Precharge
No Operation; Bank(s) idle after t
RP
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
L
BA
Column
Write w/o Precharge
ILLEGAL
2
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
20
H
H
L
X
X
Burst Termination
No Operation; Bank(s) idle after t
RP
H
H
H
X
X
No Operation
No Operation; Bank(s) idle after t
RP
Row Activating
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
X
Precharge
ILLEGAL
2
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
L
BA
Column
Write
ILLEGAL
2
H
L
H
BA
Column
Read
ILLEGAL
2
H
H
L
X
X
Burst Termination
No Operation; Row active after t
RCD
H
H
H
X
X
No Operation
No Operation; Row active after t
RCD
Write Recovering
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
X
Precharge
ILLEGAL
2
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
L
BA
Column
Write
Start Write; Determine if Auto Precharge
6
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
6
H
H
L
X
X
Burst Termination
No Operation; Row active after t
DPL
H
H
H
X
X
No Operation
No Operation; Row active after t
DPL
Write Recovering
with Auto
Precharge
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
X
Precharge
ILLEGAL
2
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
H
L
L
BA
Column
Write
ILLEGAL
2,6
H
L
H
BA
Column
Read
ILLEGAL
2,6
H
H
L
X
X
Burst Termination
No Operation; Precharge after t
DPL
H
H
H
X
X
No Operation
No Operation; Precharge after t
DPL
SDRAM CURRENT STATE TRUTH TABLE (CONT.)
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Current State
Command
Action
Notes
VCRAS# VCCAS#
VCWE#
VCBS
VCADDR
Description
Refreshing
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
X
Precharge
ILLEGAL
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
H
L
L
BA
Column
Write
ILLEGAL
H
L
H
BA
Column
Read
ILLEGAL
H
H
L
X
X
Burst Termination
No Operation; Idle after t
RC
H
H
H
X
X
No Operation
No Operation; Idle after t
RC
Mode Register
Accessing
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
X
Precharge
ILLEGAL
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
H
L
L
BA
Column
Write
ILLEGAL
H
L
H
BA
Column
Read
ILLEGAL
H
H
L
X
X
Burst Termination
ILLEGAL
H
H
H
X
X
No Operation
No Operation; Idle after two clock cycles
SDRAM CURRENT STATE TRUTH TABLE (CONT.)
Notes:
1.
Both Banks must be idle otherwise it is an illegal action.
2.
The Current State refers only refers to one of the banks, if VCBS selects this bank then the action is illegal. If VCBS selects the bank not being referenced by the Current State
then the action may be legal depending on the state of that bank.
3.
The minimum and maximum Active time (t
RAS
) must be satisfied.
4.
The VCRAS# to VCCAS# Delay (t
RCD
) must occur before the command is given.
5.
Address VCADDR9/AP is used to determine if the Auto Precharge function is activated.
6.
The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank-to-bank delay time (t
RRD
) is not
satisfied.
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FIG. 4 SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @CAS LATENCY = 3,
BURST LENGTH = 1
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
Row Active
Read
Write
Read
Precharge
Row Active
DON' T CARE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
t
CC
t
CH
t
CL
t
RCD
t
SS
t
SH
t
SS
t
SH
t
SS
t
SH
t
SS
t
SH
t
SS
t
SH
t
SS
t
SH
t
SS
t
SH
t
RCD
t
RAS
t
RP
t
CCD
t
RAC
t
SAC
t
SLZ
t
OH
Ra
Ra
Ca
BS
BS
BS
BS
BS
BS
Rb
Qc
Qa
Db
Cb
Cc
Rb
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FIG. 5 SDRAM POWER UP SEQUENCE
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
t
RP
t
RFC
t
RFC
Key
RAa
RAa
HIGH-Z
High level is necessary
Precharge
(All Banks)
Auto Refresh
Auto Refresh
Mode Register Set
Row Active
(A-Bank)
DON'T CARE
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FIG. 6 SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
CL = 2
CL = 3
Row Active
(A-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
t
RC
t
RCD
Note 1
Ra
Ca0
Cb0
Rb
Rb
Ra
t
RAC
t
RAC
Note 3
Note 3
t
SAC
t
SAC
t
OH
t
OH
t
SHZ Note 4
t
SHZ Note 4
t
RDL
t
RDL
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Db0
Db1
Db2
Db3
Qa0
Qa1
Qa2
Qa3
Notes:
1.
Minimum row cycle times are required to complete internal DRAM operation.
2.
Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (t
SHZ
)
after the clock.
3.
Access time from Row active command. t
CC
*(t
RCD
+ CAS Latency - 1) + t
SAC
.
4.
Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
14
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FIG. 7 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
CL = 2
CL = 3
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
t
RCD
Note 2
Ra
Ca0
Cb0
Cd0
Cc0
Ra
Note 3
t
CDL
Note 1
t
RDL
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb2
Qb1
Qb2
Notes:
1.
To write data before burst read ends. VCDQM# should be asserted three cycle prior to write command to avoid bus contention.
2.
Row precharge will interrupt writing. Last data input, t
RDL
before Row precharge will be written.
3.
VCDQM# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be
masked internally.
15
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FIG. 8 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
CL = 2
CL = 3
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(B-Bank)
Precharge
(A-Bank)
DON'T CARE
Note 1
RAa
CAa
CBb
CBd
CAc
CAe
RBb
RBb
RAa
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
Note:
1.
To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
16
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FIG. 9 SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Write
(A-Bank)
Write
(B-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
DON'T CARE
Note 2
RAa
CAa
RBb
CBb
CBd
CAc
RAa
RBb
Note 1
t
RDL
t
CDL
DBb0
DBb1
DBb2
DBb3
DAc0
DAc1
DBd0
DBd1
DAa0
DAa1
DAa2
DAa3
NOTES:
1. To interrupt burst write by Row precharge, VCDQM# should be asserted to mask invalid input data.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
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FIG. 10 SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
Note:
1.
t
CDL
should be met to complete write.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
CL = 2
CL = 3
Row Active
(A-Bank)
Row Active
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(B-Bank)
Precharge
(A-Bank)
DON'T CARE
RAa
CAa
RBb
RBb
RAc
RAc
CBb
CAc
RAa
Note 1
t
CDL
QAa0
QAa1
QAa2
QAa3
QAa0
QAa1
QAa2
QAa3
DBb0
DBb1
DBb2
DBb3
QAc0
QAc1
QAc0
QAc1
QAc2
DBb0
DBb1
DBb2
DBb3
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FIG. 11 SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @BURST LENGTH = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
CL = 2
CL = 3
Row Active
(A-Bank)
Row Active
(B-Bank)
Read with
Auto Precharge
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(A-Bank)
Auto Precharge
Start Point
(B-Bank)
DON'T CARE
Ra
Ca
Cb
Rb
Rb
Ra
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Db0
Db1
Db2
Db3
Qa0
Qa1
Qa2
Qa3
Note:
1.
t
CDL
should be controlled to meet minimum t
RAS
before internal precharge start.
(In the case of Burst Length = 1 & 2 and BRSW mode)
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FIG. 12 SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP
@ BURST LENGTH = FULL PAGE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
CL = 2
CL = 3
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Burst Stop
Precharge
(A-Bank)
DON'T CARE
RAa
CAa
CAb
RAa
Note 2
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
QAa0
QAa1
QAa2
QAa3
QAa4
1
2
2
1
Notes:
1.
At full page mode, burst is end at the end of burst. So auto precharge is possible.
2.
About the valid VCDATAs after burst stop, it is the same as the case of VCRAS# interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on
each of them. But at burst write, burst stop and VCRAS# interrupt should be compared carefully. Refer to the timing diagram of "Full page write burst stop cycle."
3.
Burst stop is valid at every burst length.
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FIG. 13 SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP
@ BURST LENGTH = FULL PAGE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
Row Active
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Burst Stop
Precharge
(A-Bank)
DON'T CARE
RAa
CAa
CAb
RAa
t
RDL
Note 2
t
BDL
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
DAa0
DAa1
DAa2
DAa3
DAa4
Notes:
1.
At full page mode, burst is end at the end of burst. So auto precharge is possible.
2.
Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of t
RDL
.
VCDQM# at write interrupt by precharge command is needed to prevent invalid write.
VCDQM# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be
masked internally.
3.
Burst stop is valid at every burst length.
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FIG. 14 SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
CL = 2
CL = 3
Row Active
(A-Bank)
Row Active
(B-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Read with
Auto Precharge
(A-Bank)
Precharge
(Both Banks)
DON'T CARE
Note 2
RAa
CAa
CBc
CAd
RAc
RAa
DAa0
RBb
CAb
DBc0
DBc0
RAc
QAd0
QAd1
QAd0
QAd1
DAa0
RBb
QAb0
QAb1
QAb0
QAb1
Notes:
1.
BRSW modes enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at Write is fixed to "1" regardless of programmed burst length.
2.
When BRSW write command with auto precharge is executed, keep it in mind that t
RAS
should not be violated. Auto precharge is executed at the burst-end cycle, so in
the case of BRSW write command, the next cycle starts the precharge.
22
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FIG. 15 SDRAM MODE REGISTER SET CYCLE
0 1 2 3 4 5 6
GCK
VCRAS#
VCCAS#
VCADDR
VCDATA
VCWE#
VCDQM#
MRS
New
Command
DON'T CARE
Note 2
HI-Z
Note 1
Note 3
Key
Ra
*Both banks precharge should be completed before Mode Register Set cycle.
NOTES:
MODE REGISTER SET CYCLE
1.
VCRAS#, VCCAS# & VCWE# activation at the same clock cycle with address key will set internal mode register.
2.
Minimum 2 clock cycles should be met before new VCRAS# activation.
3.
Please refer to Mode Register Set table.
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Test Mode
CAS Latency
Burst Type
Burst Length
A10
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT = 0
BT = 1
0
0
Mode Register Set
0
0
0
Reserved 0 Sequential
0
0
0
1
1
0
1
Reserved
0
0
1
Reserved 1
Interleave
0
0
1
2
2
1
0
Reserved
0
1
0
2
0
1
0
4
4
1
1
Reserved
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved Reserved
A9
Length
1
0
1
Reserved
1
0
1
Reserved Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
Full Page Reserved
MODE REGISTER FIELD TABLE TO PROGRAM MODES
REGISTER PROGRAMMED WITH MRS
Note:
1.
If A8 is high during MRS cycle, "Burst Read Single Bit Write" function will be
enabled.
2.
RFU (Reserved for future use) shuld stay "0" during MRS cycle.
SDRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
1.
Apply power and start clock. Must maintain
CKE= "H",DQM = "H" and the other pins are
NOP condition at the inputs.
2.
Maintain stable power, stable clock and NOP
input condition for a minimum of 200s.
3.
Issue precharge commandes for all banks of
the devices.
4.
Issue 2 or more auto-refresh commands.
5.
Issue a mode register set command to initialize
the mode register.
cf.)
Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
POWER UP SEQUENCE
Full Page Length: x32 (256)
Address BA0
A9/AP
A8
A10
A7
A6
A5
A4
A3
A2
A1
A2
Function RFU
RFU
W.B.L.
TM
CAS Latency
BT
Burst Length
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PACKAGE DESCRIPTION: 192 LEAD BGA 21MM X 21MM
ORDERING INFORMATION
WED9LAPC2C16V8BC
Commercial Temperature:
0C to +70C
WED9LAPC2C16V8BI
Industrial Temperature:
-40C to +85C
PIN #A1 CORNER
8.00 REF
(4X)
21.00 0.10
8.00 REF
21.00 0.10
OPTION
PIN #A1 IDENTIFIER
1.00 0.10
INK OR LASER MARKING
d 0.10
A
B
MAX 1.85
0.70 0.05
0.36 0.04
0.60 0.10
TOP VIEW
SEATING PLANE
3
f 0.10
d 0.15 C
C
BOTTOM VIEW
2
0.75 0.05
0.30m C A B
0.10m C
j
0.98 REF
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0.98 REF
PIN #A1 CORNER
19.05
1.27
19.05
1.27
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
NOTE
1. ALL DIMENSIONS AND TOLERANCE CONFORM TO ASME Y 14.5M-1994.
2. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO PRIMARY DATUM C .
3. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDIER BALLS.
4. THE SURFACE FINISH OF THE PACKAGE SHALL BE EDM
CHARMILLE #24 - #27
5. UNLESS OTHERWISE SPECIFIED TOLERANCE : DECIMAL 0.05
ANGULAR 2