WEDPN16M64VR-XB2X

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 0

GENERAL DESCRIPTION

The 128MByte (1Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
268,435,456 bits. Each chip is internally confi gured as a
quad-bank DRAM with a synchronous interface. Each of
the chip's 67,108,864-bit banks is organized as 8,192 rows
by 512 columns by 16 bits. The MCP also incorporates
two 16-bit universal bus drivers for input control signals
and addresses.

Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.

The 1Gb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.

The 1Gb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along
with a power-saving, power-down mode.

All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation,
the ability to interleave between internal banks in order
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access.

16Mx64 REGISTERED SYNCHRONOUS DRAM

FEATURES

Registered for enhanced performace of bus speeds

· 100, 125, 133MHz

Package:

· 219 Plastic Ball Grid Array (PBGA), 25 x 25mm

Single 3.3V ±0.3V power supply

Fully Synchronous; all signals registered on positive
edge of system clock cycle

Internal pipelined operation; column address can be
changed every clock cycle

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

8,192 refresh cycles

Commercial,

Industrial

and

Military

Temperature

Ranges

Organized as 16M x 64

· User confi gureable as 2 x 16M x 32

Weight: WEDPN16M64VR-XB2X - 2.5 grams
typical

BENEFITS

51%

SPACE

SAVINGS

17%

I/O

Reduction

Reduced part count

Reduced trace lengths for lower parasitic
capacitance

Glue-less connection to memory controller/PCI
Bridge

Suitable for hi-reliability applications

* This product is subject to change without notice.

WEDPN16M64VR-XB2X

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 0

FIGURE 1 PIN CONFIGURATION

NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.

NC = Not Connected Internally.

9 10

CAS#

Vss

CLK

LE#

DNU

DQMB0

WE#

RAS#

DQMB7

DQMB3

DQMB4

Vss

DQMB1

CLK

CKE

DQMB2

OE#

CLK

DQMB5

DQMB6

DNU

Top View

WEDPN16M64VR-XB2X

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 0

FUNCTIONAL DESCRIPTION

Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-12 select the row). The address bits (A0-8) registered
coincident with the READ or WRITE command are used to
select the starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register defi nition, command
descriptions and device operation.

INITIALIZATION

SDRAMs must be powered up and initialized in a predefi ned
manner. Operational procedures other than those specifi ed
may result in undefi ned operation. Once power is applied
to V

and V

CCQ

(simultaneously) and the clock is stable

(stable clock is defi ned as a signal cycling within timing
constraints specified for the clock pin), the SDRAM
requires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100µs period and continuing at
least through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.

Once the 100µs delay has been satisfi ed with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete,
the SDRAM is ready for Mode Register programming.
Because the Mode Register will power up in an unknown
state, it should be loaded prior to applying any operational
command.

REGISTER DEFINITION

MODE REGISTER

The Mode Register is used to defi ne the specifi c mode
of operation of the SDRAM. This defi nition includes the
selec-tion of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in

Figure 3. The Mode Register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.

Mode register bits M0-M2 specify the burst length, M3
specifi es the type of burst (sequential or interleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifi es the WRITE burst mode, and M10 and
M11 are reserved for future use. Address A12 (M12) is
undefi ned but should be driven LOW during loading of the
mode register.

The Mode Register must be loaded when all banks are
idle, and the controller must wait the specifi ed time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecifi ed operation.

BURST LENGTH

Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown
in Figure 3. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are available for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-8 when the burst length is set to two; by A2-8 when
the burst length is set to four; and by A3-8 when the burst
length is set to eight. The remaining (least signifi cant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached.

BURST TYPE

Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.

WEDPN16M64VR-XB2X

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 0

TABLE 1 BURST DEFINITION

FIGURE 1 MODE REGISTER DEFINITION

NOTES:

1. For full-page accesses: y = 512.

2. For a burst length of two, A1-8 select the block-of-two burst; A0 selects the starting

column within the block.

3. For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the starting

column within the block.

4. For a burst length of eight, A3-8 select the block-of-eight burst; A0-2 select the

starting column within the block.

5. For a full-page burst, the full row is selected and A0-8 select the starting column.

6. Whenever a boundary of the block is reached within a given sequence above, the

following access wraps within the block.

7. For a burst length of one, A0-8 select the unique column to be accessed, and Mode

Burst

Length

Starting Column

Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

Page

(y)

n = A0-9/8/7

(location 0-y)

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...

...Cn - 1,

Cn...

Not Supported

12 11 10 9 8 7 6 5 4 3 2 1 0

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Op Mode

Reserved*

Unused

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M12, M11, M10 = 0, 0

to ensure compatibility

with future devices.

WEDPN16M64VR-XB2X

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 0

CAS LATENCY

The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the fi rst piece of output data. The latency can be set to
two or three clocks.

If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n+m. The I/Os will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the
relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is programmed to two clocks, the I/Os will start driving
after T1 and the data will be valid by T2. Table 2 below
indicates the operating frequencies at which each CAS
latency setting can be used.

Reserved states should not be used as unknown operation
or incompatibility with future versions may result.

OPERATING MODE

The normal operating mode is selected by setting M7and
M8 to zero; the other combinations of values for M7 and
M8 are reserved for future use and/or test modes. The
programmed burst length applies to both READ and
WRITE bursts.

Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.

WRITE BURST MODE

When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses

TABLE 2 - CAS LATENCY

SPEED

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS LATENCY = 2

CAS LATENCY = 3

-133

100

133

-125

100

125

-100

100

FIGURE 4 CAS LATENCY

WEDPN16M64VR-XB2X

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 0

COMMANDS

The Truth Table provides a quick reference of available
commands. This is followed by a written description of each
command. Three additional Truth Tables appear following
the Operation section; these tables provide current state/
next state information.

INPUTS

OUTPUT

OE#

LE#

CLK

L or H

(1)

NOTES: 1. Output level before the indicated steady-state input conditions were

established.

REGISTER FUNCTION TABLE

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands
from being executed by the SDRAM, regardless of whether
the CLK signal is enabled. The SDRAM is effectively
deselected. Operations already in progress are not
affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform
a NOP to an SDRAM which is selected (CS is LOW). This
prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not
affected.

LOAD MODE REGISTER

The Mode Register is loaded via inputs A0-11. See Mode
Register heading in the Register Defi nition section. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.

TRUTH TABLE -- COMMANDS AND DQM OPERATION (NOTE 1)

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

DQM

ADDR

I/Os

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row) ( 3)

Bank/Row

READ (Select bank and column, and start READ burst) (4)

L/H

Bank/Col X

WRITE (Select bank and column, and start WRITE burst) (4)

L/H

Bank/Col Valid

BURST

TERMINATE

L H H L X X Active

PRECHARGE (Deactivate row in bank or banks) ( 5)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)

LOAD MODE REGISTER (2)

Op-Code

Write Enable/Output Enable (8)

Active

Write Inhibit/Output High-Z (8)

High-Z

NOTES:

1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-11 defi ne the op-code written to the Mode Register.

3. A0-12 provide row address, and BA0, BA1 determine which bank is made active.

4. A0-8 provide column address; A10 HIGH enables the auto precharge feature

(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks

precharged and BA0, BA1 are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is

LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care"

except for CKE.

8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs

(two-clock delay).

WEDPN16M64VR-XB2X

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 0

ACTIVE

The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and
the address provided on inputs A0-A12 selects the row.
This row remains active (or open) for accesses until
a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening
a different row in the same bank.

READ

The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-8
selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ
burst; if AUTO PRECHARGE is not selected, the row will
remain open for subsequent accesses. Read data appears
on the I/Os subject to the logic level on the DQM inputs
two clocks earlier. If a given DQM signal was registered
HIGH, the corresponding I/Os will be High-Z two clocks
later; if the DQM signal was registered LOW, the I/Os will
provide valid data.

WRITE

The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-8
selects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the I/Os
is written to the memory array subject to the DQM input
logic level appearing coincident with the data. If a given
DQM signal is registered LOW, the corresponding data
will be written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access

a specifi ed time (t

) after the PRECHARGE command is

issued. Input A10 determines whether one or all banks are
to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as "Don't Care." Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands being
issued to that bank.

AUTO PRECHARGE

AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, without requiring an explicit command. This is
accomplished by using A10 to enable AUTO PRECHARGE
in conjunction with a specifi c READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst, except in
the full-page burst mode, where AUTO PRECHARGE does
not apply. AUTO PRECHARGE is nonpersistent in that it
is either enabled or disabled for each individual READ or
WRITE command.

AUTO PRECHARGE ensures that the precharge is initiated
at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the
precharge time (t

) is completed. This is determined as

if an explicit PRECHARGE command was issued at the
earliest possible time.

BURST TERMINATE

The BURST TERMINATE command is used to truncate
either fi xed-length or full-page bursts. The most recently
registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the
SDRAM and is analagous to CAS-BEFORE-RAS (CBR)
REFRESH in conventional DRAMs. This command is
nonpersistent, so it must be issued each time a refresh
is required.

The addressing is generated by the internal refresh
controller. This makes the address bits "Don't Care" during
an AUTO REFRESH command. Each 256Mb SDRAM
requires 8,192 AUTO REFRESH cycles every refresh
period (tREF). Providing a distributed AUTO REFRESH
command will meet the refresh requirement and ensure

WEDPN16M64VR-XB2X

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 0

that each row is refreshed. Alternatively, 8,192 AUTO
REFRESH commands can be issued in a burst at the
minimum cycle rate (t

), once every refresh period

REF

SELF REFRESH*

The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). Once the SELF REFRESH
command is registered, all the inputs to the SDRAM
become "Don't Care," with the exception of CKE, which
must remain LOW.

Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own
AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to t

RAS

and

may remain in self refresh mode for an indefi nite period
beyond that.

The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock
is defi ned as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back
HIGH. Once CKE is HIGH, the SDRAM must have NOP
commands issued (a minimum of two clocks) for t

XSR

because time is required for the completion of any internal
refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.

* Self refresh available in commercial and industrial temperatures only.

WEDPN16M64VR-XB2X

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 0

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)

= +3.3V ±0.3V; -55°C

+125°C

Parameter/Condition

Symbol

Min

Max

Units

Supply Voltage

3.6

Input High Voltage: Logic 1; All inputs (21)

+ 0.3

Input Low Voltage: Logic 0; All inputs (21)

-0.3

0.8

Input Leakage Current: Any input 0V V

(All other pins not under test = 0V)

-5

µA

Output Leakage Current: I/Os are disabled; 0V V

OUT

-5

µA

Output High Voltage (I

OUT

= -4mA)

2.4

Output Low Voltage (I

OUT

= 4mA)

0.4

ABSOLUTE MAXIMUM RATINGS

Parameter

Unit

Voltage on V

, V

CCQ

Supply relative to V

-1 to 4.6

Voltage on NC or I/O pins relative to V

-1 to 4.6

Operating Temperature T

(Mil)

-55 to +125

°C

Operating Temperature T

(Ind)

-40 to +85

°C

Storage Temperature, Plastic

-55 to +125

°C

NOTE:

Stress greater than those listed under "Absolute Maximum Ratings" may cause
per ma nent damage to the device. This is a stress rating only and func tion al op er a tion
of the device at these or any other conditions greater than those in di cat ed in the
operational sections of this specifi cation is not implied. Exposure to ab so lute maximum
rating con di tions for extended periods may affect reliability.

CAPACITANCE (NOTE 2)

Parameter

Symbol

Max

Unit

Input Capacitance: CLK

14 pF

Addresses, BA0-1 Input Capacitance

Input Capacitance: All other input-only pins

8 pF

Input/Output Capacitance: I/Os

8 pF

REG

SPECIFICATIONS AND CONDITIONS (NOTES 1,6,11,13)

= +3.3V ±0.3V; -55°C

+125°C

Parameter/Condition

Symbol

Max

Units

Operating Current: Active Mode;
Burst = 2; Read or Write; t

= t

(min); CAS latency = 3 (3, 18, 19)

CC1

700

Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after t

RCD

met; No accesses in progress (3, 12, 19)

CC3

240

Operating Current: Burst Mode; Continuous burst;
Read or Write; All banks active; CAS latency = 3 (3, 18, 19)

CC4

750

Self Refresh Current: CKE 0.2V Commercial and Industrial temperatures only (27, 28)

CC7

BGA THERMAL RESISTANCE

Description

Symbol

Max

Unit

Notes

Junction to Ambient (No Airfl ow)

16.8

°C/W

Junction to Ball

12.2

°C/W

Junction to Case (Top)

6.5

°C/W

NOTE: Refer to PBGA Thermal Resistance Correlation Application note at
www.wedc.com in the application notes section for modeling conditions.

WEDPN16M64VR-XB2X

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 0

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS

(NOTES 5, 6, 8, 9, 11, 29)

Parameter

Symbol

-133

-125

-100

Unit

Min

Max

Min

Max

Min

Max

Access time from CLK (pos. edge)

CL = 3

5.4

5.8

CL = 2

Address hold time

0.8

1 1

Address setup time

1.5

CLK high-level width

2.5

CLK low-level width

2.5

Clock cycle time (22)

CL = 3

7.5

8 10

CL = 2

CKE hold time

CKH

0.8

1 1

CKE setup time

CKS

1.5

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

0.8

1 1

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

1.5

Data-in hold time

0.8

1 1

Data-in setup time

1.5

Data-out high-impedance time (10)

CL = 3 (10)

5.4

5.8 6

CL = 2 (10)

Data-out low-impedance time

Data-out hold time (load)

Data-out hold time (no load) (26)

OHN

1.8

ACTIVE to PRECHARGE command

RAS

120,000

120,000 50

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period (8,192 rows) Commercial, Industrial

REF

64 64

Refresh period (8,192 rows) Military

REF

AUTO REFRESH period

RFC

70 70

PRECHARGE command period

20 ns

ACTIVE bank A to ACTIVE bank B command

RRD

20 20

Transition time (7)

0.3

1.2

0.3 1.2

0.3

1.2

WRITE recovery time

(23)

1 CLK + 7ns

(24)

15 15

Exit SELF REFRESH to ACTIVE command

XSR

WEDPN16M64VR-XB2X

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

January 2005
Rev. 0

NOTES:

1. All voltages referenced to VSS.

2. This parameter is not tested but guaranteed by design. f = 1 MHz, T

= 25°C.

3. I

is dependent on output loading and cycle rates. Specifi ed values are obtained

with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifi cations are used only to indicate cycle time at which proper

operation over the full temperature range is ensured.

6. An initial pause of 100µs is required after power-up, followed by two AUTO

REFRESH commands, before proper device operation is ensured. (V

must be

powered up simultaneously.) The two AUTO REFRESH command wake-ups should
be repeated any time the t

REF

refresh requirement is exceeded.

7. AC characteristics assume t

= 1ns.

8. In addition to meeting the transition rate specifi cation, the clock and CKE must

transit between V

and V

(or between V

and V

) in a monotonic manner.

9. Outputs measured at 1.5V with equivalent load:

10. t

defi nes the time at which the output achieves the open circuit condition; it is not

a reference to V

or V

. The last valid data element will meet t

before going

High-Z.

11. AC timing and I

tests have V

= 0V and V

= 3V, with timing referenced to 1.5V

crossover point.

12. Other input signals are allowed to transition no more than once every two clocks

and are otherwise at valid V

or V

levels.

13. I

specifi cations are tested after the device is properly initialized.

14. Timing actually specifi ed by t

CKS

; clock(s) specifi ed as a reference only at minimum

cycle rate.

15. Timing actually specifi ed by t

plus t

; clock(s) specifi ed as a reference only at

minimum cycle rate.

16. Timing actually specifi ed by t

17. Required clocks are specifi ed by JEDEC functionality and are not dependent on any

timing parameter.

18. The I

current will decrease as the CAS latency is reduced. This is due to the fact

that the maximum cycle rate is slower as the CAS latency is reduced.

19. Address transitions average one transition every two clocks.

20. CLK must be toggled a minimum of two times during this period.

21. V

overshoot: V

(MAX) = V

+ 2V for a pulse width 3ns, and the pulse width

cannot be greater than one third of the cycle rate. V

undershoot: V

(MIN) = -2V for

a pulse width -3ns.

22. The clock frequency must remain constant (stable clock is defi ned as a signal

cycling within timing constraints specifi ed for the clock pin) during access or
precharge states (READ, WRITE, including t

, and PRECHARGE commands).

CKE may be used to reduce the data rate.

23. Auto precharge mode only. The precharge timing budget (t

) begins 7.5ns after the

fi rst clock delay, after the last WRITE is executed.

24. Precharge mode only.

25. JEDEC and PC100 specify three clocks.

26. Parameter guaranteed by design.

27. Self refresh available in commercial and industrial temperatures only.

28. OE# high.

29. All AC timings do not count extra clock cycle needed on control signals to be

registered.

AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11,29)

Parameter/Condition

Symbol

-133

-125

-100

Units

READ/WRITE command to READ/WRITE command (17)

CCD

CKE to clock disable or power-down entry mode (14)

CKED

CKE to clock enable or power-down exit setup mode (14)

PED

DQM to input data delay (17)

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay (17)

DWD

Data-in to ACTIVE command (15)

DAL

Data-in to PRECHARGE command (16)

DPL

Last data-in to burst STOP command (17)

BDL

Last data-in to new READ/WRITE command (17)

CDL

Last data-in to PRECHARGE command (16)

RDL

LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)

MRD

Data-out to high-impedance from PRECHARGE command (17)

CL = 3

ROH

CL = 2

ROH

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: WEDPN16M64VR-133B2M

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: WEDPN16M64VR-133B2M