1
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White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
GENERAL DESCRIPTION
The 32MByte (256Mb) SDRAM is a high-speed CMOS,
dynamic random-access ,memory using 4 chips containing
67,108,864 bits. Each chip is internally confi gured as a
quad-bank DRAM with a synchronous interface. Each of the
chip's 16,777,216-bit banks is organized as 4,096 rows by
256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0, BA1 select the bank; A0-11 select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-speed,
random-access operation.
The 256Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
4Mx64 Synchronous DRAM
21
21
Discrete Approach
S
A
V
I
N
G
S
Area
4 x 265mm
2
= 1061mm
2
441mm
2
58%
ACTUAL SIZE
22.3
11.9
54
TSOP
54
TSOP
54
TSOP
54
TSOP
WEDPN4M64V-XBX
FEATURES
High Frequency = 100, 125, 133MHz
Package:
219 Plastic Ball Grid Array (PBGA), 21 x 21mm
Single 3.3V 0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
Commercial,
Industrial
and
Military
Temperature
Ranges
Organized as 4M x 64
User Confi gurable as 2x4Mx32 or 4x4Mx16
Weight: WEDPN4M64V-XBX - 2 grams typical
BENEFITS
58%
SPACE
SAVINGS
Reduced part count
Reduced trace lengths for lower parasitic
capacitance
Laminate interposer for optimum TCE match
Suitable for hi-reliability applications
Upgradeable to 8M x 64 (contact factory for
availability)
*This product is subject to change without notice.
2
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White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FIGURE 1 PIN CONFIGURATION
NOTE: DNU = Do Not Use
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ
1
DQ
3
DQ
6
DQ
7
CAS
0
#
CS
0
#
V
SS
V
SS
V
SS
V
SS
DQ
56
DQ
57
DQ
60
DQ
62
Vss
V
SS
DQ
30
DQ
28
DQ
25
DQ
24
CLK
1
CKE
1
V
CC
V
CC
CS
2
#
CAS
2
#
DQ
39
DQ
38
DQ
35
DQ
33
V
CC
DQ
0
DQ
2
DQ
4
DQ
5
DQML0
WE
0
#
RAS
0
#
V
SS
V
SS
CKE
3
CLK
3
DQMH3
DQ
58
DQ
59
DQ
61
DQ
63
DQ
31
DQ
29
DQ
27
DQ
26
V
SS
DQMH1
V
CC
V
CC
V
CC
RAS
2
#
WE
2
#
DQML2
DQ
37
DQ
36
DQ
34
DQ
32
DQ
14
DQ
12
DQ
10
DQ
8
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
DQ
55
DQ
53
DQ
51
DQ
49
DQ
17
DQ
19
DQ
21
DQ
23
V
SS
V
SS
V
SS
Vss
V
SS
V
SS
V
SS
V
SS
DQ
40
DQ
42
DQ
44
DQ
46
DQ
15
DQ
13
DQ
11
DQ
9
DQMH0
CLK
0
CKE
0
V
CC
V
CC
CS
3
#
CAS
3
#
WE
3
#
DQ
54
DQ
52
DQ
50
DQ
48
DQ
16
DQ
18
DQ
20
DQ
22
DQML1
WE
1
#
CS
1
#
V
SS
V
SS
CKE
2
CLK
2
DQMH2
DQ
41
DQ
43
DQ
45
DQ
47
V
SS
V
SS
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
RAS
3
#
DQML3
V
CC
V
SS
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
RAS
1
#
CAS
1
#
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
CC
V
SS
V
SS
A
9
A
0
A
2
DNU
NC
V
CC
V
CC
V
CC
V
SS
V
SS
A
8
A
1
A
3
DNU
NC
V
SS
V
SS
V
SS
V
CC
V
CC
A
10
A
7
A
5
DNU
BA
0
V
CC
V
CC
V
CC
V
SS
V
SS
A
11
A
6
A
4
DNU
BA
1
V
SS
V
SS
V
SS
V
CC
V
CC
V
SS
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
CC
V
SS
V
SS
3
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WEDPN4M64V-XBX
January 2005
Rev. 8
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FIGURE 2 FUNCTIONAL BLOCK DIAGRAM
A0-11
BA0-1
RAS0#
WE0#
CAS0#
A0-11
BA0-1
CK0
CK
CAS#
DQ0
DQ15
CKE0
CKE
CS0#
CS#
DQML0
DQML
DQMH0
DQMH
DQ0
WE#
U0
RAS#
4M x 16
DQ15
RAS1#
WE1#
CAS1#
DQ0
DQ15
WE#
U1
RAS#
A0-11
BA0-1
CK1
CK
CAS#
DQ16
DQ31
CKE1
CKE
CS1#
CS#
DQML1
DQML
DQMH1
DQMH
4M x 16
RAS2#
WE2#
CAS2#
DQ0
DQ15
WE#
U2
RAS#
A0-11
BA0-1
CK2
CK
CAS#
DQ32
DQ47
CKE2
CKE
CS2#
CS#
DQML2
DQML
DQMH2
DQMH
4M x 16
RAS3#
WE3#
CAS3#
DQ0
DQ15
WE# RAS#
A
0-11
BA
0-1
CK3
CK
CAS#
DQ48
DQ63
CKE3
CKE
CS3#
CS#
DQML3
DQML
DQMH3
DQMH
U3
4M x 16
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high data
rate with automatic column-address generation, the ability to
interleave between internal banks in order to hide precharge
time and the capability to randomly change column addresses
on each clock cycle during a burst access.
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-11 select the row). The address bits (A0-7) registered
coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register defi nition, command
descriptions and device operation.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefi ned
manner. Operational procedures other than those specifi ed
may result in undefi ned operation. Once power is applied
to V
CC
and V
CCQ
(simultaneously) and the clock is stable
(stable clock is defi ned as a signal cycling within timing
constraints specifi ed for the clock pin), the SDRAM requires
a 100s delay prior to issuing any command other than a
COMMAND INHIBIT or a NOP. Starting at some point during
this 100s period and continuing at least through the end
of this period, COMMAND INHIBIT or NOP commands
should be applied.
Once the 100s delay has been satisfi ed with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete,
the SDRAM is ready for Mode Register programming. Because
the Mode Register will power up in an unknown state, it should
be loaded prior to applying any operational command.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to defi ne the specifi c mode
of operation of the SDRAM. This defi nition includes the
selec-tion of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in Figure
2. The Mode Register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifi es the type of burst (sequential or interleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifi es the WRITE burst mode, and M10 and
M11 are reserved for future use.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specifi ed time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecifi ed operation.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown
in Figure 2. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are available for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-7 when the
burst length is set to two; by A2-7 when the burst length is set
to four; and by A3-7 when the burst length is set to eight. The
remaining (least signifi cant) address bit(s) is (are) used to
select the starting location within the block. Full-page bursts
wrap within the page if the boundary is reached.
5
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WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
TABLE 1 BURST DEFINITION
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
A0
0
0-1
0-1
1
1-0
1-0
4
A1
A0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
n = A0-9/8/7
(location 0-y)
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
...Cn - 1,
Cn...
Not Supported
FIGURE 2 MODE REGISTER DEFINITION
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7 A6
A5 A4
A3
A8
A2
A1 A0
Mode Register (Mx)
Address Bus
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Op Mode
A10
A11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
NOTES:
1.
For full-page accesses: y = 256.
2.
For a burst length of two, A1-7 select the block-of-two burst; A0 selects the starting
column within the block.
3.
For a burst length of four, A2-7 select the block-of-four burst; A0-1 select the starting
column within the block.
4.
For a burst length of eight, A3-7 select the block-of-eight burst; A0-2 select the
starting column within the block.
5.
For a full-page burst, the full row is selected and A0-7 select the starting column.
6.
Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7.
For a burst length of one, A0-7 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
6
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White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FIGURE 3 CAS LATENCY
CK
I/O
T2
T1
T3
T0
COMMAND
NOP
READ
NOP
NOP
CK
I/O
T2
T1
T3
T0
CAS Latency = 2
LZ
D
OUT
t
OH
COMMAND
NOP
READ
t
AC
NOP
t
CAS Latency = 3
t
AC
T4
DON'T CARE
UNDEFINED
LZ
D
OUT
t
OH
t
OPERATING MODE
The normal operating mode is selected by setting M7and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
TABLE 2 CAS LATENCY
SPEED
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS LATENCY = 2
CAS LATENCY = 3
-100
75
100
-125
100
125
-133
100
133
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of each
command. Three additional Truth Tables appear following
the Operation section; these tables provide current state/
next state information.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
fi rst piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n+m. The I/Os will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the
relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency is
programmed to two clocks, the I/Os will start driving after
T1 and the data will be valid by T2. Table 2 below indicates
the operating frequencies at which each CAS latency setting
can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
7
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Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
TRUTH TABLE COMMANDS AND DQM OPERATION (NOTE 1)
Name (Function)
CS#
RAS#
CAS#
WE#
DQM
ADDR
I/Os
COMMAND
INHIBIT
(NOP)
H X X X X X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row) ( 3)
L
L
H
H
X
Bank/Row
X
READ (Select bank and column, and start READ burst) (4)
L
H
L
H
L/H
8
Bank/Col X
WRITE (Select bank and column, and start WRITE burst) (4)
L
H
L
L
L/H
8
Bank/Col Valid
BURST
TERMINATE
L H H L X X Active
PRECHARGE (Deactivate row in bank or banks) ( 5)
L
L
H
L
X
Code
X
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
L
L
L
H
X
X
X
LOAD MODE REGISTER (2)
L
L
L
L
X
Op-Code
X
Write Enable/Output Enable (8)
L
Active
Write Inhibit/Output High-Z (8)
H
High-Z
NOTES:
1.
CKE is HIGH for all commands shown except SELF REFRESH.
2.
A0-11 defi ne the op-code written to the Mode Register.
3.
A0-11 provide row address, and BA0, BA1 determine which bank is made active.
4.
A0-7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is
being read from or written to.
5.
A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care."
6.
This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7.
Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8.
Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock delay).
on inputs A0-11 selects the row. This row remains active
(or open) for accesses until a PRECHARGE command is
issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-7
selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ burst;
if AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses. Read data appears on
the I/Os subject to the logic level on the DQM inputs two
clocks earlier. If a given DQM signal was registered HIGH,
the corresponding I/Os will be High-Z two clocks later; if
the DQM signal was registered LOW, the I/Os will provide
valid data.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-7
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands
from being executed by the SDRAM, regardless of whether
the CK signal is enabled. The SDRAM is effectively
deselected. Operations already in progress are not
affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to an SDRAM which is selected (CS# is LOW).
This prevents unwanted commands from being registered
during idle or wait states. Operations already in progress
are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-11. See Mode
Register heading in the Register Defi nition section. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in
a particular bank for a subsequent access. The value on the
BA0, BA1 inputs selects the bank, and the address provided
8
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WEDPN4M64V-XBX
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selects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the I/Os is
written to the memory array subject to the DQM input logic
level appearing coincident with the data. If a given DQM
signal is registered LOW, the corresponding data will be
written to memory; if the DQM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE
will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specifi ed time (t
RP
) after the PRECHARGE command is
issued. Input A10 determines whether one or all banks are
to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as "Don't Care." Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished
by using A10 to enable AUTO PRECHARGE in conjunction
with a specifi c READ or WRITE command. A precharge of
the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of
the READ or WRITE burst, except in the full-page burst
mode, where AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled or
disabled for each individual READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is initiated
at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the
precharge time (t
RP
) is completed. This is determined as
if an explicit PRECHARGE command was issued at the
earliest possible time.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
either fi xed-length or full-page bursts. The most recently
registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
controller. This makes the address bits "Don't Care" during
an AUTO REFRESH command. The 64Mb SDRAM requires
4,096 AUTO REFRESH cycles every refresh period (t
REF
),
regardless of width option. Providing a distributed AUTO
REFRESH command will meet the refresh requirement
and ensure that each row is refreshed. Alternatively, 4,096
AUTO REFRESH commands can be issued in a burst at
the minimum cycle rate (t
RC
), once every refresh period
(t
REF
).
SELF REFRESH*
The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). Once the SELF REFRESH
command is registered, all the inputs to the SDRAM become
"Don't Care," with the exception of CKE, which must remain
LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to tRAS and may remain
in self refresh mode for an indefi nite period beyond that.
The procedure for exiting self refresh requires a sequence of
commands. First, CK must be stable (stable clock is defi ned
as a signal cycling within timing constraints specifi ed for
the clock pin) prior to CKE going back HIGH. Once CKE is
HIGH, the SDRAM must have NOP commands issued (a
minimum of two clocks) for t
XSR
, because time is required
for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.
* Self refresh available in commercial and industial temperatures only.
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
V
CC
= +3.3V 0.3V; -55C T
A
+125C
Parameter/Condition
Symbol
Min
Max
Units
Supply Voltage
V
CC
3
3.6
V
Input High Voltage: Logic 1; All inputs (21)
V
IH
2
V
CC
+ 0.3
V
Input Low Voltage: Logic 0; All inputs (21)
V
IL
-0.3
0.8
V
Input Leakage Current: Any input 0V VIN VCC (All other pins not under test = 0V)
I
I
-5
5
A
Input Leakage Address Current: Any input 0V VIN VCC (All other pins not under test = 0V)
I
I
-20
20
A
Output Leakage Current: I/Os are disabled; 0V VOUT VCC
I
OZ
-5
5
A
Output Levels:
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
V
OH
2.4
V
V
OL
0.4
V
ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
Voltage on VCC Supply relative to Vss
-1 to 4.6
V
Voltage on NC or I/O pins relative to Vss
-1 to 4.6
V
Operating Temperature TA (Mil)
-55 to +125
C
Operating Temperature TA (Ind)
-40 to +85
C
Storage Temperature, Plastic
-55 to +125
C
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions greater than those indicated in the operational sections
of this specifi cation is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE (NOTE 2)
Parameter
Symbol
Max
Unit
Inut Capacitance: CK
C
I1
5
pF
Addresses, BA0-1 Input Capacitance
C
A
17
pF
Input Capacitance: All other input-only pins
C
I2
7
pF
Input/Output Capacitance: I/Os
C
IO
8
pF
IDD SPECIFICATIONS AND CONDITIONS (NOTES 1,6,11,13)
V
CC
= +3.3V 0.3V; -55C T
A
125C
Parameter/Condition
Symbol
Max
Units
Operating Current: Active Mode;
Burst = 2; Read or Write; t
RC
= t
RC
(min); CAS latency = 3 (3, 18, 19)
I
CC1
460
mA
Standby Current: Active Mode; CKE = HIGH; CS = HIGH;
All banks active after t
RCD
met; No accesses in progress (3, 12, 19)
I
CC3
180
mA
Operating Current: Burst Mode; Continuous burst;
Read or Write; All banks active; CAS latency = 3 (3, 18, 19)
I
CC4
560
mA
Self Refresh Current: CKE - 0.2V Commercial and Industrial temperature only (27)
I
CC7
4
mA
BGA THERMAL RESISTANCE
Description
Symbol
Max
Units
Notes
Junction to Ambient
(No Airfl ow)
Theta JA
18.5
C/W
1
Junction to Ball
Theta JB
13.1
C/W
1
Junction to Case (Top)
Theta JC
9.1
C/W
1
NOTE 1: Refer to BGA Thermal Resistance Correlation application note at www.wedc.com
in the application notes section for modeling conditions.
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11)
Parameter
Symbol
-100
-125
-133
Unit
Min
Max
Min
Max
Min
Max
Access time from CK (pos. edge)
CL = 3
t
AC
7
6
5.5
ns
CL = 2
t
AC
7
6
6
ns
Address hold time
t
AH
1 1
0.8
ns
Address setup time
t
AS
2
2
1.5
ns
CK high-level width
t
CH
3
3
2.5
ns
CK low-level width
t
CL
3
3
2.5
ns
Clock cycle time (22)
CL = 3
t
CK
10 8
7.5
ns
CL = 2
t
CK
13
10
10
CKE hold time
t
CKH
1 1
0.8
ns
CKE setup time
t
CKS
2
2
1.5
ns
CS#, RAS#, CAS#, WE#, DQM hold time
t
CMH
1 1
0.8
ns
CS#, RAS#, CAS#, WE#, DQM setup time
t
CMS
2
2
1.5
ns
Data-in hold time
t
DH
1 1
0.8
ns
Data-in setup time
t
DS
2
2
1.5
ns
Data-out high-impedance time
CL = 3 (10)
t
HZ
7 6
5.5
ns
CL = 2 (10)
t
HZ
7 6
6
ns
Data-out low-impedance time
t
LZ
1 1
1
ns
Data-out hold time (load)
t
OH
3 3
3
ns
Data-out hold time (no load) (26)
t
OHN
1.8
1.8
1.8
ns
ACTIVE to PRECHARGE command
t
RAS
50
120,000 50
120,000
50
120,000
ns
ACTIVE to ACTIVE command period
t
RC
70
68
68
ns
ACTIVE to READ or WRITE delay
t
RCD
20
20
20
ns
Refresh period (4,096 rows) Commercial, Industrial
t
REF
64 64
64
ms
Refresh period (4,096 rows) Military
t
REF
16
16
16
ms
AUTO REFRESH period
t
RFC
70 70
70
ns
PRECHARGE command period
t
RP
20
20 20 ns
ACTIVE bank A to ACTIVE bank B command
t
RRD
20 20
20
ns
Transition time (7)
t
T
0.3
1.2
0.3
1.2
0.3
1.2
ns
WRITE recovery time
(23)
t
WR
1 CK + 7ns
1 CK + 7ns
1 CK + 7.5
--
(24)
15 15
15
ns
Exit SELF REFRESH to ACTIVE command
t
XSR
80 80
75
ns
11
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11)
Parameter/Condition
Symbol
-100
-125
-133
Units
READ/WRITE command to READ/WRITE command (17)
t
CCD
1
1
1
t
CK
CKE to clock disable or power-down entry mode (14)
t
CKED
1 1
1
t
CK
CKE to clock enable or power-down exit setup mode (14)
t
PED
1
1
1
t
CK
DQM to input data delay (17)
t
DQD
0 0
0
t
CK
DQM to data mask during WRITEs (17)
t
DQM
0 0
0
t
CK
DQM to data high-impedance during READs (17)
t
DQZ
2 2
2
t
CK
WRITE command to input data delay (17)
t
DWD
0 0
0
t
CK
Data-in to ACTIVE command (15)
t
DAL
4
5
5
t
CK
Data-in to PRECHARGE command (16)
t
DPL
2 2
2
t
CK
Last data-in to burst STOP command (17)
t
BDL
1
1
1
t
CK
Last data-in to new READ/WRITE command (17)
t
CDL
1 1
1
t
CK
Last data-in to PRECHARGE command (16)
t
RDL
2 2
2
t
CK
LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)
t
MRD
2
2
2
t
CK
Data-out to high-impedance from PRECHARGE command (17)
CL = 3
t
ROH
3
3
3
t
CK
CL = 2
t
ROH
2
--
--
t
CK
NOTES
1.
All voltages referenced to V
SS
.
2.
This parameter is not tested but garanteed by design. f = 1 MHz, T
A
= 25C.
3. I
DD
is dependent on output loading and cycle rates. Specifi ed values are obtained
with minimum cycle time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifi cations are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
6.
An initial pause of 100s is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (V
CC
must be
powered up simultaneously.) The two AUTO REFRESH command wake-ups should
be repeated any time the t
REF
refresh requirement is exceeded.
7.
AC characteristics assume t
T
= 1ns.
8.
In addition to meeting the transition rate specifi cation, the clock and CKE must transit
between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
9.
Outputs measured at 1.5V with equivalent load:
10. t
HZ
defi nes the time at which the output achieves the open circuit condition; it is not a
reference to V
OH
or V
OL
. The last valid data element will meet t
OH
before going High-
Z.
11. AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3V, with timing referenced to 1.5V
crossover point.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid V
IH
or V
IL
levels.
Q
1.5V
50
13. I
CC
specifi cations are tested after the device is properly initialized.
14. Timing actually specifi ed by t
CKS
; clock(s) specifi ed as a reference only at minimum
cycle rate.
15. Timing actually specifi ed by t
WR
plus t
RP
; clock(s) specifi ed as a reference only at
minimum cycle rate.
16. Timing actually specifi ed by t
WR
.
17. Required clocks are specifi ed by JEDEC functionality and are not dependent on any
timing parameter.
18. The
I
CC
current will decrease as the CAS latency is reduced. This is due to the fact
that the maximum cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every two clocks.
20. CK must be toggled a minimum of two times during this period.
21. V
IH
overshoot: V
IH
(MAX) = V
CC
+ 2V for a pulse width - 3ns, and the pulse width
cannot be greater than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for
a pulse width - 3ns.
22. The clock frequency must remain constant (stable clock is defi ned as a signal cycling
within timing constraints specifi ed for the clock pin) during access or precharge states
(READ, WRITE, including t
WR
, and PRECHARGE commands). CKE may be used to
reduce the data rate.
23. Auto precharge mode only. The precharge timing budget (t
RP
) begins 7.5ns/7ns after
the fi rst clock delay, after the last WRITE is executed.
24. Precharge
mode
only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.
12
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
PACKAGE 739: 219 PLASTIC BALL GRID ARRAY (PBGA)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
Bottom View
1 2
3
4 5
6 7
8
9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
219 x
0.762 (0.030) NOM
1.27 (0.050)
NOM
21.1 (0.831) SQ. MAX
19.05 (0.750) NOM
19.05 (0.750)
NOM
2.03 (0.080)
MAX
0.61
(0.024)
NOM
WED P N 4M 64 V - XXX B X
DEVICE GRADE:
M = Military
-55C to +125C
I = Industrial
-40C
to
+85C
C = Commercial 0C to +70C
PACKAGE:
B = 219 Plastic Ball Grid Array (PBGA), 21mm x 21mm
FREQUENCY (MHz)
100 = 100MHz
125 = 125MHz
133 = 133MHz
3.3V Power Supply
CONFIGURATION, 4M x 64
SDRAM
PLASTIC
WHITE ELECTRONIC DESIGNS CORP.
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