1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN4M72V-XB2X
January 2005
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
GENERAL DESCRIPTION
The 32MByte (256Mb) SDRAM is a high-speed CMOS,
dynamic random-access ,memory using 5 chips containing
67,108,864 bits. Each chip is internally confi gured as a
quad-bank DRAM with a synchronous interface. Each of
the chip's 16,777,216-bit banks is organized as 4,096 rows
by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Ac cess es begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
11 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
4Mx72 Synchronous DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
219 Plastic Ball Grid Array (PBGA), 21 x 21mm
Single 3.3V 0.3V power supply
Fully Synchronous; all signals registered on pos i tive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
Commercial,
Industrial
and
Military
Temperature
Rang es
Organized as 4M x 72
Weight: WEDPN4M72V-XB2X - 2 grams typical
BENEFITS
60%
SPACE
SAVINGS
Reduced part count
Reduced
I/O
count
19% I/O Reduction
Lower inductance and capacitance for low noise
performance
Suitable for hi-reliability applications
Upgradeable to 8M x 72 density with same foot print
WEDPN8M72V-XB2X
* This product is subject to change without notice..
21
21
Discrete Approach
S
A
V
I
N
G
S
Area
5 x 265mm
2
= 1328mm
2
441mm
2
67%
5 x 54 pins = 270 pins
219 Balls
19%
ACTUAL SIZE
22.3
11.9
11.9
I/O
Count
11.9
11.9
11.9
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
White Electronic Designs
WEDPN4M72V-XB2X
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN4M72V-XB2X
January 2005
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FIGURE 1 PIN CONFIGURATION
NOTE: DNU = Do Not Use, to be left unconnected for future upgrades.
* Pin D7 is DNU for 4M x 72, 8M x 72 product, Pin D7 is A12 for 16M x 72 and higher densities.
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ
1
DQ
3
DQ
6
DQ
7
CAS
0
#
CS
0
#
V
SS
V
SS
NC
NC
DQ
56
DQ
57
DQ
60
DQ
62
Vss
V
SS
DQ
30
DQ
28
DQ
25
DQ
24
CLK
1
CKE
1
V
CC
V
CC
CS
2
#
CAS
2
#
DQ
39
DQ
38
DQ
35
DQ
33
V
CC
DQ
0
DQ
2
DQ
4
DQ
5
DQML0
WE
0
#
RAS
0
#
V
SS
V
SS
CKE
3
CLK
3
DQMH3
DQ
58
DQ
59
DQ
61
DQ
63
DQ
31
DQ
29
DQ
27
DQ
26
NC
DQMH1
NC
V
CC
V
CC
RAS
2
#
WE
2
#
DQML2
DQ
37
DQ
36
DQ
34
DQ
32
DQ
14
DQ
12
DQ
10
DQ
8
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
DQ
55
DQ
53
DQ
51
DQ
49
DQ
17
DQ
19
DQ
21
DQ
23
V
SS
V
SS
V
SS
Vss
V
SS
V
SS
V
SS
V
SS
DQ
40
DQ
42
DQ
44
DQ
46
DQ
15
DQ
13
DQ
11
DQ
9
DQMH0
CLK
0
CKE
0
V
CC
V
CC
CS
3
#
CAS
3
#
WE
3#
DQ
54
DQ
52
DQ
50
DQ
48
DQ
16
DQ
18
DQ
20
DQ
22
DQML1
WE
1
#
CS
1
#
V
SS
V
SS
CKE
2
CLK
2
DQMH2
DQ
41
DQ
43
DQ
45
DQ
47
V
SS
V
SS
V
CC
V
CC
NC
NC
NC
V
SS
V
SS
NC
RAS
3
#
DQML3
NC
V
SS
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
NC
RAS
1
#
CAS
1
#
V
CC
V
CC
NC
NC
CS
4
#
NC
V
CC
V
SS
V
SS
A
9
A
0
A
2
DNU*
NC
DQMH4
DQ
73
DQ
75
DQ
77
DQ
79
A
8
A
1
A
3
DNU
NC
WE
4
#
DQ
70
DQ
68
DQ
66
DQ
64
A
10
A
7
A
5
DNU
BA
0
CLK
4
DQ
72
DQ
74
DQ
76
DQ
78
A
11
A
6
A
4
DNU
BA
1
CAS
4
#
DQ
71
DQ
69
DQ
67
DQ
65
V
SS
V
SS
V
CC
V
CC
NC
CKE
4
NC
V
SS
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
NC
RAS
4
#
DQML4
V
CC
V
SS
V
SS
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN4M72V-XB2X
January 2005
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FIGURE 2 FUNCTIONAL BLOCK DIAGRAM
A0-11
BA0-1
CK0
CKE0
CS0#
DQML0
DQMH0
RAS 1#
WE1#
CAS 1#
U1
CK
1
RAS 0#
WE0#
CAS 0#
U0
CKE
1
CS
1
#
DQML
1
DQMH
1
RAS 2#
WE2#
CAS 2#
U2
CK
2
CKE
2
CS
2
#
DQML
2
DQMH
2
RAS 3#
WE3#
CAS 3#
U3
CK
3
CKE
3
CS
3
#
DQML
3
DQMH
3
RAS 4#
WE4#
CAS 4#
U4
CK
4
CKE
4
CS
4
#
DQML
4
DQMH
4
DQ0
DQ15
DQ0
DQ15
A0-11
BA0-1
CK
CAS#
CKE
CS#
DQML
DQMH
WE# RAS#
DQ16
DQ31
DQ0
DQ15
A0-11
BA0-1
CK
CAS#
CKE
CS#
DQML
DQMH
WE# RAS#
DQ32
DQ47
DQ0
DQ15
A0-11
BA0-1
CK
CAS#
CKE
CS#
DQML
DQMH
WE# RAS#
DQ48
DQ63
DQ0
DQ15
A0-11
BA0-1
CK
CAS#
CKE
CS#
DQML
DQMH
WE# RAS#
DQ64
DQ79
DQ0
DQ15
A0-11
BA0-1
CK
CAS#
CKE
CS#
DQML
DQMH
WE# RAS#
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN4M72V-XB2X
January 2005
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
performed. After the AUTO REFRESH cycles are complete,
the SDRAM is ready for Mode Register programming.
Because the Mode Register will power up in an unknown
state, it should be loaded prior to applying any operational
command.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to defi ne the specifi c mode
of operation of the SDRAM. This defi nition includes the
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
Figure 2. The Mode Register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
Mode register bits M0-M2 specify the burst length, M3
specifi es the type of burst (sequential or interleaved),
M4-M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifi es the WRITE burst mode, and
M10 and M11 are reserved for future use.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specifi ed time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecifi ed operation.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown
in Figure 2. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are available for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown op er a tion
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
The 256Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is pro vid ed,
along with a power-saving, power-down mode.
All inputs and outputs are LV
TTL
compatible. SDRAMs offer
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation,
the ability to interleave between internal banks in order
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access.
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the AC TIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-11 select the row). The address bits (A0-7) registered
coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register defi nition, command
descriptions and device operation.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefi ned
manner. Operational procedures other than those specifi ed
may result in undefi ned operation. Once power is applied
to V
CC
and V
CCQ
(simultaneously) and the clock is stable
(stable clock is defi ned as a signal cycling within timing
constraints specified for the clock pin), the SDRAM
requires a 100s delay prior to issuing any command
other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100s period and continuing at
least through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.
Once the 100s delay has been satisfi ed with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPN4M72V-XB2X
January 2005
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
TABLE 1 BURST DEFINITION
FIGURE 3 MODE REGISTER DEFINITION
NOTES:
1. For full-page accesses: y = 256.
2. For a burst length of two, A1-7 select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-7 select the block-of-four burst; A0-1 select the starting
column within the block.
4. For a burst length of eight, A3-7 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-7 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-7 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A
9
A
7
A
6
A
5
A
4
A
3
A
8
A
2
A
1
A
0
Mode Register (Mx)
Address Bus
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Op Mode
A
10
A
11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential Type = In ter leaved
2
A0
0
0-1
0-1
1
1-0
1-0
4
A1
A0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
n = A
0
-9/8/7
(location 0-y)
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
...Cn - 1,
Cn...
Not Supported
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