White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

WEDPN4M72V-XBX

November 2003 Rev. 14

The 32MByte (256Mb) SDRAM is a high-speed CMOS, dy-
namic random-access ,memory using 5 chips containing
67,108,864 bits. Each chip is internally configured as a quad-
bank DRAM with a synchronous interface. Each of the chip's
16,777,216-bit banks is organized as 4,096 rows by 256
columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand, which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-11 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column lo-
cation for the burst access.

The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.

The 256Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is com-
patible with the 2

n rule of prefetch architectures, but it also

allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seam-
less, high-speed, random-access operation.

4Mx72 Synchronous DRAM

! High Frequency = 100, 125MHz
! Package:

· 219 Plastic Ball Grid Array (PBGA), 25 x 21mm

! Single 3.3V ±0.3V power supply
! Fully Synchronous; all signals registered on positive

edge of system clock cycle

! Internal pipelined operation; column address can be

changed every clock cycle

! Internal banks for hiding row access/precharge
! Programmable Burst length 1,2,4,8 or full page
! 4096 refresh cycles
! Commercial, Industrial and Military Temperature Ranges
! Organized as 4M x 72
! Weight: WEDPN4M72V-XBX - 2 grams typical

! 60% SPACE SAVINGS
! Reduced part count
! Reduced I/O count

· 19% I/O Reduction

! Lower inductance and capacitance for low noise

performance

! Suitable for hi-reliability applications
! Upgradeable to 8M x 72 density with same footprint

(contact factory for information)

FEATURES

BENEFITS

*This product is subject to change without notice.

GENERAL DESCRIPTION

Discrete Approach

Area

5 x 265mm

= 1328mm

525mm

60%

5 x 54 pins = 270 pins

219 Balls

19%

ACTUAL SIZE

22.3

11.9

I/O

Count

11.9

TSOP

White Electronic Designs

WEDPN4M72V-XBX

White Electronic Designs Corporation · Phoenix AZ · (602) 437-1520

WEDPN4M72V-XBX

. 1 P

ONFIGURATION

NOTE: DNU = Do Not Use, to be left unconnected for future upgrades.
* Pin D7 is DNU for 4M x 72, 8M x 72 product, Pin D7 is A12 for 16M x 72 and higher densities.

IEW

9 10

11 12 13 14

15 16

CAS

Vss

CLK

CKE

CAS

DQML0

RAS

CKE

CLK

DQMH3

DQMH1

RAS

DQML2

Vss

DQMH0

CLK

CKE

CAS

DQML1

CKE

CLK

DQMH2

RAS

DQML3

RAS

CAS

DNU*

DQMH4

DNU

CLK

DNU

CAS

CKE

RAS

DQML4

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WEDPN4M72V-XBX

. 2 FUNCTIONAL BLOCK DIAGRAM

0-11

0-1

CLK

CAS

CKE

DQML

DQMH

RAS

CAS

·
·
·
·
·

·
·
·
·
·
·

RAS

0-11

0-1

CLK

CAS

RAS

CAS

·
·
·
·
·

·
·
·
·
·
·

RAS

CKE

DQML

DQMH

RAS

CAS

·
·
·
·
·

·
·
·
·
·
·

RAS

0-11

0-1

CLK

CAS

CKE

DQML

DQMH

RAS

CAS

·
·
·
·
·

·
·
·
·
·
·

RAS

0-11

0-1

CLK

CAS

CKE

DQML

DQMH

RAS

CAS

·
·
·
·
·

·
·
·
·
·
·

RAS

0-11

0-1

CLK

CAS

CKE

DQML

DQMH

White Electronic Designs Corporation · Phoenix AZ · (602) 437-1520

WEDPN4M72V-XBX

Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0 and BA1 select the bank, A0-11 select the
row). The address bits (A0-7) registered coincident with
the READ or WRITE command are used to select the star t-
ing column location for the burst access.

Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information cover-
ing device initialization, register definition, command de-
scriptions and device operation.

SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those speci-
fied may result in undefined operation. Once power is ap-
plied to VDD and VDDQ (simultaneously) and the clock is
stable (stable clock is defined as a signal cycling within tim-
ing constraints specified for the clock pin), the SDRAM re-
quires a 100µs delay prior to issuing any command other
than a COMMAND INHIBIT or a NOP. Starting at some point
during this 100µs period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.

Once the 100µs delay has been satisfied with at least one
COMMAND INHIBIT or NOP command having been applied,
a PRECHARGE command should be applied. All banks must
be precharged, thereby placing the device in the all banks
idle state.

Once in the idle state, two AUTO REFRESH cycles must be

performed. After the AUTO REFRESH cycles are complete, the
SDRAM is ready for Mode Register programming. Because the
Mode Register will power up in an unknown state, it should
be loaded prior to applying any operational command.

The Mode Register is used to define the specific mode of
operation of the SDRAM. This definition includes the selec-
tion of a burst length, a burst type, a CAS latency, an oper-
ating mode and a write burst mode, as shown in Figure 3.
The Mode Register is programmed via the LOAD MODE REG-
ISTER command and will retain the stored information until
it is programmed again or the device loses power.

Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4-
M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the WRITE burst mode, and M10
and M11 are reserved for future use.

The Mode Register must be loaded when all banks are idle,
and the controller must wait the specified time before initi-
ating the subsequent operation. Violating either of these
requirements will result in unspecified operation.

Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in Fig-
ure 3. The burst length determines the maximum number of
column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4 or 8 locations are
available for both the sequential and the interleaved burst
types, and a full-page burst is available for the sequential type.
The full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown opera-
tion or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of col-
umns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-7 when the
burst length is set to two; by A2-7 when the burst length is
set to four; and by A3-7 when the burst length is set to
eight. The remaining (least significant) address bit(s) is (are)
used to select the starting location within the block. Full-
page bursts wrap within the page if the boundary is reached.

The 256Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.

All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, in-
cluding the ability to synchronously burst data at a high data
rate with automatic column-address generation, the ability
to interleave between internal banks in order to hide
precharge time and the capability to randomly change col-
umn addresses on each clock cycle during a burst access.

FUNCTIONAL DESCRIPTION

INITIALIZATION

BURST LENGTH

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WEDPN4M72V-XBX

ABLE

1 - B

URST

EFINITION

Burst

Starting Column

Order of Accesses Within a Burst

Length

Address

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

n = A0-9/8/7

Cn, Cn + 1, Cn + 2

Page

Cn + 3, Cn + 4...

Not Supported

(y)

(location 0-y)

...Cn - 1,

Cn...

Type = Sequential

Type = Interleaved

. 3 M

ODE

EGISTER

EFINITION

NOTES:
1. For full-page accesses: y = 256.
2. For a burst length of two, A1-7 select the block-of-two burst; A0 selects the
starting column within the block.
3. For a burst length of four, A2-7 select the block-of-four burst; A0-1 select the
starting column within the block.
4. For a burst length of eight, A3-7 select the block-of-eight burst; A0-2 select
the starting column within the block.
5. For a full-page burst, the full row is selected and A0-7 select the starting
column.
6. Whenever a boundary of the block is reached within a given sequence
above, the following access wraps within the block.
7. For a burst length of one, A0-7 select the unique column to be accessed, and
Mode Register bit M3 is ignored.

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Op Mode

Reserved* WB

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M11, M10 = 0, 0

to ensure compatibility

with future devices.

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WEDPN4M72V-XBX

The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.

If a READ command is registered at clock edge

n, and the

latency is

m clocks, the data will be available by clock edge

n+m. The I/Os will start driving as a result of the clock edge
one cycle earlier (

n + m - 1), and provided that the rel-

evant access times are met, the data will be valid by clock
edge

n + m. For example, assuming that the clock cycle

time is such that all relevant access times are met, if a READ
command is registered at T0 and the latency is programmed
to two clocks, the I/Os will start driving after T1 and the
data will be valid by T2. Table 2 below indicates the operat-
ing frequencies at which each CAS latency setting can be
used.

Reserved states should not be used as unknown opera-
tion or incompatibility with future versions may result.

ABLE

2 - C

ATENCY

. 4 C

ATENCY

ALLOWABLE OPERATING

FREQUENCY (MHZ)

CAS

SPEED

LATENCY = 2

LATENCY = 3

-100

100

-125

100

125

The normal operating mode is selected by setting M7and
M8 to zero; the other combinations of values for M7 and
M8 are reserved for future use and/or test modes. The pro-
grammed burst length applies to both READ and WRITE
bursts.

Test modes and reserved states should not be used be-
cause unknown operation or incompatibility with future
versions may result.

When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.

The Truth Table provides a quick reference of available com-
mands. This is followed by a written description of each
command. Three additional Truth Tables appear following
the Operation section; these tables provide current state/
next state information.

Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the burst
type and is selected via bit M3.

The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column ad-
dress, as shown in Table 1.

BURST TYPE

CAS LATENCY

OPERATING MODE

WRITE BURST MODE

COMMANDS

CLK

I/O

CAS Latency = 3

OUT

COMMAND

NOP

READ

NOP

DON'T CARE

UNDEFINED

CLK

I/O

CAS Latency = 2

OUT

COMMAND

NOP

READ

NOP

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WEDPN4M72V-XBX

RUTH

ABLE

- C

OMMANDS

DQM O

PERATION

OTE

NAME (FUNCTION)

RAS

CAS

DQM

ADDR

I/Os

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row) ( 3)

Bank/Row

READ (Select bank and column, and start READ burst) (4)

L/H

Bank/Col

WRITE (Select bank and column, and start WRITE burst) (4)

L/H

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or banks) ( 5)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)

LOAD MODE REGISTER (2)

Op-Code

Write Enable/Output Enable (8)

Active

Write Inhibit/Output High-Z (8)

High-Z

active (or open) for accesses until a PRECHARGE command
is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.

The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-7 se-
lects the star ting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed will
be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Read data appears on the I/Os sub-
ject to the logic level on the DQM inputs two clocks earlier.
If a given DQM signal was registered HIGH, the correspond-
ing I/Os will be High-Z two clocks later; if the DQM signal
was registered LOW, the I/Os will provide valid data.

The WRITE command is used to initiate a burst write access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-7 se-
lects the star ting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If

The COMMAND INHIBIT function prevents new commands
from being executed by the SDRAM, regardless of whether
the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.

The NO OPERATION (NOP) command is used to perform a
NOP to an SDRAM which is selected (CS is LOW). This pre-
vents unwanted commands from being registered during idle
or wait states. Operations already in progress are not affected.

The Mode Register is loaded via inputs A0-11. See Mode
Register heading in the Register Definition section. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until tMRD is met.

The ACTIVE command is used to open (or activate) a row
in a particular bank for a subsequent access. The value on
the BA0, BA1 inputs selects the bank, and the address pro-
vided on inputs A0-11 selects the row. This row remains

NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 define the op-code written to the Mode Register.
3. A0-11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care."
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock delay).

COMMAND INHIBIT

NO OPERATION (NOP)

LOAD MODE REGISTER

ACTIVE

READ

WRITE

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WEDPN4M72V-XBX

AUTO PRECHARGE is selected, the row being accessed will
be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the I/Os is
written to the memory array subject to the DQM input logic
level appearing coincident with the data. If a given DQM
signal is registered LOW, the corresponding data will be
written to memory; if the DQM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE
will not be executed to that byte/column location.

The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is is-
sued. Input A10 determines whether one or all banks are
to be precharged, and in the case where only one bank is
to be precharged, inputs BA0, BA1 select the bank. Other-
wise BA0, BA1 are treated as "Don't Care." Once a bank
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being is-
sued to that bank.

AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished
by using A10 to enable AUTO PRECHARGE in conjunction
with a specific READ or WRITE command. A precharge of
the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of
the READ or WRITE burst, except in the full-page burst
mode, where AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled or
disabled for each individual READ or WRITE command.

AUTO PRECHARGE ensures that the precharge is initiated at
the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge time
(tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time.

The BURST TERMINATE command is used to truncate either
fixed-length or full-page bursts. The most recently registered
READ or WRITE command prior to the BURST TERMINATE
command will be truncated.

AUTO REFRESH is used during normal operation of the SDRAM
and is analagous to CAS-BEFORE-RAS (CBR) REFRESH in con-
ventional DRAMs. This command is nonpersistent, so it must
be issued each time a refresh is required.

The addressing is generated by the internal refresh control-
ler. This makes the address bits "Don't Care" during an AUTO
REFRESH command. The 64Mb SDRAM requires 4,096 AUTO
REFRESH cycles every refresh period (tREF), regardless of
width option. Providing a distributed AUTO REFRESH com-
mand will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 4,096 AUTO REFRESH com-
mands can be issued in a burst at the minimum cycle rate
(tRC), once every refresh period (tREF).

The SELF REFRESH command can be used to retain data in
the SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the SDRAM retains data with-
out external clocking. The SELF REFRESH command is initi-
ated like an AUTO REFRESH command except CKE is dis-
abled (LOW). Once the SELF REFRESH command is regis-
tered, all the inputs to the SDRAM become "Don't Care,"
with the exception of CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to tRAS and may remain
in self refresh mode for an indefinite period beyond that.

The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock is
defined as a signal cycling within timing constraints speci-
fied for the clock pin) prior to CKE going back HIGH. Once
CKE is HIGH, the SDRAM must have NOP commands is-
sued (a minimum of two clocks) for tXSR, because time is
required for the completion of any inter nal refresh in
progress.

Upon exiting the self refresh mode, AUTO REFRESH com-
mands must be issued as both SELF REFRESH and AUTO
REFRESH utilize the row refresh counter.

*Self refresh available in commercial and industrial temperatures only.

PRECHARGE

AUTO PRECHARGE

BURST TERMINATE

AUTO REFRESH

SELF REFRESH*

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WEDPN4M72V-XBX

DC E

LECTRICAL

HARACTERISTICS

PERATING

ONDITIONS

OTES

1, 6)

(VCC = +3.3V ±0.3V; TA = -55°C

+125°C)

Parameter/Condition

Symbol

Units

Min

Max

Supply Voltage

3.6

Input High Voltage: Logic 1; All inputs (21)

+ 0.3

Input Low Voltage: Logic 0; All inputs (21)

-0.3

0.8

Input Leakage Current: Any input 0V - V

- V

(All other pins not under test = 0V)

-5

µA

Input Leakage Address Current: Any input 0V - V

- V

(All other pins not under test = 0V)

-25

µA

Output Leakage Current: I/Os are disabled; 0V - V

OUT

- V

-5

µA

Output Levels:

Output High Voltage (I

OUT

= -4mA)

2.4

Output Low Voltage (I

OUT

= 4mA)

0.4

BSOLUTE

AXIMUM

ATINGS

Parameter

Unit

Voltage on V

Supply relative to Vss

-1 to 4.6

Voltage on NC or I/O pins relative to Vss

-1 to 4.6

Operating Temperature T

(Mil)

-55 to +125

°C

Operating Temperature T

(Ind)

-40 to +85

°C

Storage Temperature, Plastic

-55 to +150

°C

NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.

APACITANCE

OTE

Parameter

Symbol

Max

Unit

Input Capacitance: CLK

7.0

Addresses, BA

0-1

Input Capacitance

Input Capacitance: All other input-only pins

7.0

Input/Output Capacitance: I/Os

10.0

IDD S

PECIFICATIONS

ONDITIONS

OTES

1,6,11,13)

(VCC = +3.3V ±0.3V; TA = -55°C

+125°C)

Parameter/Condition

Symbol

Max

Units

Operating Current: Active Mode;

CC1

575

Burst = 2; Read or Write; t

= t

(min); CAS latency = 3 (3, 18, 19)

Standby Current: Active Mode; CKE = HIGH; CS = HIGH;

CC3

225

All banks active after t

RCD

met; No accesses in progress (3, 12, 19)

Operating Current: Burst Mode; Continuous burst;

CC4

700

Read or Write; All banks active; CAS latency = 3 (3, 18, 19)

Self Refresh Current: CKE - 0.2V (27)

CC7

HERMAL

ESISTANCE

Parameter

Symbol

Max

Unit

Thermal Resistance: Die Junction to Ambient

15.8

°C/W

Thermal Resistance: Die Junction to Ball

10.8

°C/W

Thermal Resistance: Die Junction to Case

6.0

°C/W

Note: Refer to Application Note "PBGA Thermal Resistance Corrleation"
for further information regarding WEDC's thermal modeling.

1 0

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WEDPN4M72V-XBX

Parameter

Symbol

-100

-125

Unit

Min

Max

Min

Max

Access time from CLK (pos. edge)

CL = 3

CL = 2

Address hold time

Address setup time

CLK high-level width

CLK low-level width

Clock cycle time

(22)

CL = 3

CL = 2

CKE hold time

CKH

CKE setup time

CKS

CS, RAS, CAS, WE, DQM hold time

CMH

CS, RAS, CAS, WE, DQM setup time

CMS

Data-in hold time

Data-in setup time

Data-out high-impedance time

CL = 3 (10)

CL = 2 (10)

Data-out low-impedance time

Data-out hold time (load)

Data-out hold time (no load) (26)

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period (4,096 rows) Commercial, Industrial

REF

Refresh period (4,096 rows) Military

REF

AUTO REFRESH period

RFC

PRECHARGE command period

ACTIVE bank A to ACTIVE bank B command

RRD

Transition time (7)

0.3

1.2

0.3

1.2

WRITE recovery time

(23)

1 CLK + 7ns

(24)

Exit SELF REFRESH to ACTIVE command

XSR

LECTRICAL

HARACTERISTICS

ECOMMENDED

AC O

PERATING

HARACTERISTICS

OTES

5, 6, 8, 9, 11)

1 1

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WEDPN4M72V-XBX

AC F

UNCTIONAL

HARACTERISTICS

OTES

5,6,7,8,9,11)

Parameter/Condition

Symbol

-100

-125

Units

READ/WRITE command to READ/WRITE command (17)

CCD

CKE to clock disable or power-down entry mode (14)

CKED

CKE to clock enable or power-down exit setup mode (14)

PED

DQM to input data delay (17)

DQD

DQM to data mask during WRITEs (17)

DQM

DQM to data high-impedance during READs (17)

DQZ

WRITE command to input data delay (17)

DWD

Data-in to ACTIVE command (15)

DAL

Data-in to PRECHARGE command (16)

DPL

Last data-in to burst STOP command (17)

BDL

Last data-in to new READ/WRITE command (17)

CDL

Last data-in to PRECHARGE command (16)

RDL

LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)

MRD

Data-out to high-impedance from PRECHARGE command (17)

CL = 3

ROH

CL = 2

ROH

NOTES
1. All voltages referenced to VSS.
2. This parameter is not tested but garanteed by design. f = 1 MHz, TA = 25°C.
3. IDD is dependent on output loading and cycle rates. Specified values are
obtained with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range is ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (Vcc must be
powered up simultaneously.) The two AUTO REFRESH command wake-ups
should be repeated any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:

10. tHZ defines the time at which the output achieves the open circuit
condition; it is not a reference to VOH or VOL. The last valid data element will
meet tOH before going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced
to 1.5V crossover point.
12. Other input signals are allowed to transition no more than once every two
clocks and are otherwise at valid VIH or VIL levels.

13. ICC specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at
minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference
only at minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent
on any timing parameter.
18. The ICC current will decrease as the CAS latency is reduced. This is due to
the fact that the maximum cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width - 3ns, and the pulse
width cannot be greater than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width - 3ns.
22. The clock frequency must remain constant (stable clock is defined as a
signal cycling within timing constraints specified for the clock pin) during access
or precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
23. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/
7ns after the first clock delay, after the last WRITE is executed.
24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh avaiable in commercial and industrial temperatures only.

50pF

1 3

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WEDPN4M72V-XBX

Document Title

4M x 72 Synchronous DRAM

Revision History

Rev #

History

ReleaseDate

Status

Rev 1

Initial Release

August 1999

Advanced

Rev 2

Change mechanical outline dimensions (Pg. 1, 12)

September 1999

Advanced

1.1

21.00 (0.827) x 25.00(0.984) to
21.21 (0.835) x 25.25(0.994)

1.2

Ball diameter 0.75mm to 0.65mm

1.3

Package height from 3.04(0.120) to 2.27(0.090) Max

Rev 3

Change status from Advanced to Preliminary

September 1999

Preliminary

Rev 4

Changes (Pg. 1, 6, 9, 11)

November 1999

Preliminary

1.1

Remove reference to Figure 4 in CAS Latency
Description

1.2

Change all references of V

and V

DDQ

to V

1.3

Add Input Leakage Current Min 25uA, and 25uA to DC
Electrical Characteristics Table

1.4

Change all references of I

to I

1.5

Add CKE < 0.2V for Self Refresh Current

1.6

Remove statement V

and V

SSQ

must be at same

potential under Note 6 for AC Functional Characteristics

Rev 5

Change ball diameter from 0.65mm to 0.835mm on Mechanical

January 2000

Preliminary

Outline (Pg. 1, 12)

Rev 6

Remove Commercial Temperature Only note from 125MHz

February 2000

Preliminary

Speed grade (Pg. 1, 12)

Rev 7

Add Weight = 2grams Typical to Features (Pg. 1)

April 2000

Preliminary

Rev 8

Changes (Pg.1, 8, 9)

June 2000

Preliminary

1.1

Remove Commercial Temp Only Note on Pg. 1

1.2

Add note *Self Refresh available in commercial and
Industrial temperature only

1.3

Add Thermal Resistance Table: Theta JB = 3.7

C/W

Rev 8

1.4

Change maximum Self Refresh Current from 5mA
To 4mA.

1 4

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WEDPN4M72V-XBX

Rev 9

Change status from Preliminary to Final (Pg. 1)

April 2001

Final

Rev 10

Changes (Pg. 1, 9)

April 2002

Final

1.1

Delete Power Dissipation of 5W from Absolute
Maximum Ratings Table

1.2

Correct Thermal Resistance 3.7

C/W to 6.7

C/W

Rev 11

Changes (Pg. 1, 10)

August 2002

Final

1.1

Change tAC for CL3 to 7ns @ 100MHz

1.2

Change tAC for CL2 to 7ns @ 100MHz, 6ns @ 125MHz

1.3

Add tCK for CL3; 10ns @ 100MHz, 8ns @ 125MHz

1.4

Change tCK for CL2; 13ns @ 100MHz, 10ns @ 125MHz

1.5

Change tHZ for CL3; to 7ns @ 100MHz

1.6

Change tHZ for CL2; to 6ns @ 125MHz

1.7

Change tREF for Military Temperature to 16ms @ 125MHz

Rev 12

Changes (Pg 1, 2, 14)

October 2002

Final

1.1

Add Note on future upgrades to pinout

Rev 13

Changes (Pg 1, 9)

January 2003

Final

1.1

Add Thermal Resistance Table

1.2

Change I

CC7

from 4

A to 5

May 2003

Rev 14

Changes (Pg. 1, 12, 14)

November 2003

Final

1.1

Change mechanical drawing to new style

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