White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

WEDPN8M64V-XBX

November 2003 Rev. 13

GENERAL DESCRIPTION

The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-
namic random-access memory using 4 chips containing
134,217,728 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip's 33,554,432-bit banks is organized as 4,096 rows
by 512 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA

, BA

select the bank; A

0-11

select the

row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.

The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page,
with a burst terminate option. An AUTO PRECHARGE func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence.

The 512Mb SDRAM uses an internal pipelined architec-
ture to achieve high-speed operation. This architecture is
compatible with the 2

n rule of prefetch architectures, but

it also allows the column address to be changed on ev-
ery clock cycle to achieve a high-speed, fully random ac-
cess. Precharging one bank while accessing one of the
other three banks will hide the precharge cycles and pro-
vide seamless, high-speed, random-access operation.

8Mx64 Synchronous DRAM

FEATURES

High Frequency = 100, 125, 133**MHz
Package:

· 219 Plastic Ball Grid Array (PBGA), 25 x 25mm

Single 3.3V ±0.3V power supply

Unbuffered
Fully synchronous; all signals registered on positive

edge of system clock cycle

Internal pipelined operation; column address can be

changed every clock cycle

Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page

4,096 refresh cycles
Commercial, Industrial and Military Temperature Ranges
Organized as 8M x 64

· User Configurable as 2 x 8M x 32 or 4 x 8M x 16

Weight: WEDPN8M64V-XBX - 2.5 grams typical

BENEFITS

41% SPACE SAVINGS

Reduced part count
Low Profile: 2.20 mm (0.087) Max
Reduced trace lengths for lower parasitic capacitance

Laminate interposer for optimum TCE match
Suitable for hi-reliability applications
Upgradeable to 16M x 64 density (WEDPN16M64V-XBX)

This product is subject to change without notice.

** 133MHz available at commercial (0

C to + 70

C) temperature only.

Discrete Approach

S
A
V

Area

4 x 265mm

= 1061mm

625mm

41%

ACTUAL SIZE

22.3

11.9

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WEDPN8M64V-XBX

. 1 P

ONFIGURATION

NOTE:

DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.

IEW

9 10

11 12 13 14 15 16

CAS

Vss

CLK

CKE

CAS

DQML0

RAS

CKE

CLK

DQMH3

Vss

DQMH1

Vcc

RAS

DQML2

Vss

DQMH0

CLK

CKE

CAS

DQML1

CKE

CLK

DQMH2

Vss

RAS

DQML3

Vcc

Vss

RAS

CAS

Vcc

Vss

DNU

Vcc

Vss

DNU

Vss

Vcc

DNU

Vcc

Vss

DNU

Vss

Vcc

Vss

Vcc

Vss

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WEDPN8M64V-XBX

. 2 F

UNCTIONAL

LOCK

IAGRAM

0-11

0-1

CLK

CAS

CKE

DQML

DQMH

RAS

CAS

·
·
·
·
·

·
·
·
·
·
·

RAS

0-11

0-1

CLK

CAS

RAS

CAS

·
·
·
·
·

·
·
·
·
·
·

RAS

CKE

DQML

DQMH

RAS

CAS

·
·
·
·
·

·
·
·
·
·
·

RAS

0-11

0-1

CLK

CAS

CKE

DQML

DQMH

RAS

CAS

·
·
·
·
·

·
·
·
·
·
·

RAS

0-11

0-1

CLK

CAS

CKE

DQML

DQMH

8M x 16

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WEDPN8M64V-XBX

FUNCTIONAL DESCRIPTION

Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an AC-
TIVE command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA

and BA

select the bank, A

0-11

select

the row). The address bits (A

0-8

) registered coincident

with the READ or WRITE command are used to select the
star ting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information cov-
ering device initialization, register definition, command
descriptions and device operation.

INITIALIZATION

SDRAMs must be powered up and initialized in a pre-
defined manner. Operational procedures other than those
specified may result in undefined operation. Once power
is applied to VDD and VDDQ (simultaneously) and the clock
is stable (stable clock is defined as a signal cycling within
timing constraints specified for the clock pin), the SDRAM
requires a 100µs delay prior to issuing any command other
than a COMMAND INHIBIT or a NOP. Starting at some point
during this 100µs period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.

Once the 100µs delay has been satisfied with at least one
COMMAND INHIBIT or NOP command having been applied,
a PRECHARGE command should be applied. All banks must
be precharged, thereby placing the device in the all banks
idle state.

Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete,

the SDRAM is ready for Mode Register programming. Because
the Mode Register will power up in an unknown state, it should
be loaded prior to applying any operational command.

REGISTER DEFINITION

MODE REGISTER

The Mode Register is used to define the specific mode of
operation of the SDRAM. This definition includes the selec-
tion of a burst length, a burst type, a CAS latency, an op-
erating mode and a write burst mode, as shown in Figure
3. The Mode Register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.

Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4-
M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the WRITE burst mode, and M10
and M11 are reserved for future use.

The Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time be-
fore initiating the subsequent operation. Violating either
of these requirements will result in unspecified operation.

BURST LENGTH

Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
Figure 3. The burst length determines the maximum num-
ber of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 1, 2, 4 or 8
locations are available for both the sequential and the in-
terleaved burst types, and a full-page burst is available for
the sequential type. The full-page burst is used in con-
junction with the BURST TERMINATE command to generate
arbitrary burst lengths.

Reserved states should not be used, as unknown opera-
tion or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A

1-8

when the burst length is set to two; by A

2-8

when

the burst length is set to four; and by A

3-8

when the burst

length is set to eight. The remaining (least significant) ad-

The 512Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.

All inputs and outputs are LVTTL compatible. SDRAMs of-
fer substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation, the
ability to interleave between internal banks in order to hide
precharge time and the capability to randomly change col-
umn addresses on each clock cycle during a burst access.

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WEDPN8M64V-XBX

Burst

Star

Star ting Column

ting Column

Order of Accesses W

Order of Accesses Within a Burst

ithin a Burst

Length

Address

A 0

0-1

1-0

A 1

A 0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A 2

A 1

A 0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

n = A0-9/8/7

Cn, Cn + 1, Cn + 2

Page

Cn + 3, Cn + 4...

Not Suppor ted

(y)

(location 0-y)

...Cn - 1,

Cn...

NOTES:

NOTES:
1. For full-page accesses: y = 512.
2. For a burst length of two, A

1-8

select the block-of-two burst; A0 selects

the starting column within the block.

3. For a burst length of four, A

2-8

select the block-of-four burst; A0-1 select

the starting column within the block.

4. For a burst length of eight, A

3-8

select the block-of-eight burst; A

0-2

select the starting column within the block.

5. For a full-page burst, the full row is selected and A

0-8

select the starting

column.

6. Whenever a boundary of the block is reached within a given sequence

above, the following access wraps within the block.

7. For a burst length of one, A

0-8

select the unique column to be accessed,

and Mode Register bit M3 is ignored.

ABLE

1 - B

URST

EFINITION

T
T

T
Type = Sequential T

ype = Sequential T

ype = Sequential Type = Interleaved

ype = Interleaved

. 3 M

ODE

EGISTER

EFINITION

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Op Mode

Reserved* WB

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M11, M10 = 0, 0

to ensure compatibility

with future devices.

dress bit(s) is (are) used to select the star ting location
within the block. Full-page bursts wrap within the page if
the boundary is reached.

BURST TYPE

Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by
the burst length, the burst type and the star ting column
address, as shown in Table 1.

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WEDPN8M64V-XBX

ALL

ALLOW

OWABLE OPER

ABLE OPER

ABLE OPERA

ATING

TING

FREQUENC

FREQUENCY (MHz)

Y (MHz)

C A

A S

SPEED

L
L
L
L
L A

ATENC

TENC

TENCY = 2

Y = 2

L
L
L
L
L A

ATENC

TENC

TENCY = 3

Y = 3

-100

100

-125

100

125

-133

100

133

CAS LATENCY

The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two
or three clocks.

If a READ command is registered at clock edge

n, and the

latency is

m clocks, the data will be available by clock

edge

n+m. The I/Os will start driving as a result of the

clock edge one cycle earlier (

n + m - 1), and provided

that the relevant access times are met, the data will be
valid by clock edge

n + m. For example, assuming that

the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the I/Os will start
driving after T1 and the data will be valid by T2. Table 2
below indicates the operating frequencies at which each
CAS latency setting can be used.

Reserved states should not be used as unknown opera-
tion or incompatibility with future versions may result.

OPERATING MODE

The normal operating mode is selected by setting M7and
M8 to zero; the other combinations of values for M7 and M8

. 4 C

ATENCY

CLK

I/O

CAS Latency = 3

OUT

COMMAND

NOP

READ

NOP

DON'T CARE

UNDEFINED

CLK

I/O

CAS Latency = 2

OUT

COMMAND

NOP

READ

NOP

are reserved for future use and/or test modes. The pro-
grammed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used be-
cause unknown operation or incompatibility with future
versions may result.

WRITE BURST MODE

When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.

ABLE

2 - CAS LATENCY

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WEDPN8M64V-XBX

RUTH

ABLE

- C

OMMANDS

AND

DQM O

PERATION

OTE

NAME (FUNCTION)

R
R

R
RA

A S

C A

A S

DQM

ADDR

I/Os

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row) ( 3)

Bank/Row

READ (Select bank and column, and start READ burst) (4)

L/H

Bank/Col

WRITE (Select bank and column, and start WRITE burst) (4)

L/H

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or banks) ( 5)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)

LOAD MODE REGISTER (2)

Op-Code

Write Enable/Output Enable (8)

Active

Write Inhibit/Output High-Z (8)

High-Z

NOTES

NOTES:::::

1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A

0-11

define the op-code written to the Mode Register.

3. A

0-11

provide row address, and BA

, BA

determine which bank is made active.

4. A

0-8

provide column address; A

HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature;

, BA

determine which bank is being read from or written to.

5. A10 LOW: BA

, BA

determine the bank being precharged. A

HIGH: All banks precharged and BA

, BA

are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock delay).

ACTIVE

The ACTIVE command is used to open (or activate) a row
in a par ticular bank for a subsequent access. The value on
the BA

, BA

inputs selects the bank, and the address pro-

vided on inputs A

0-11

selects the row. This row remains

active (or open) for accesses until a PRECHARGE command
is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access
to an active row. The value on the BA

, BA

inputs selects

the bank, and the address provided on inputs A

0-8

se-

lects the starting column location. The value on input A

determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Read data appears on the I/Os sub-
ject to the logic level on the DQM inputs two clocks ear-
lier. If a given DQM signal was registered HIGH, the corre-
sponding I/Os will be High-Z two clocks later; if the DQM
signal was registered LOW, the I/Os will provide valid data.

COMMANDS

The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command. Three additional Truth Tables appear fol-
lowing the Operation section; these tables provide cur-
rent state/next state information.

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands
from being executed by the SDRAM, regardless of whether
the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a
NOP to an SDRAM which is selected (CS is LOW). This pre-
vents unwanted commands from being registered during idle
or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The Mode Register is loaded via inputs A

0-11

. See Mode

Register heading in the Register Definition section. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until t

MRD

is met.

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WEDPN8M64V-XBX

BURST TERMINATE

The BURST TERMINATE command is used to truncate either
fixed-length or full-page bursts. The most recently regis-
tered READ or WRITE command prior to the BURST TERMI-
NATE command will be truncated.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the
SDRAM and is analagous to CAS-BEFORE-RAS (CBR) REFRESH
in conventional DRAMs. This command is nonpersistent,
so it must be issued each time a refresh is required.

The addressing is generated by the internal refresh con-
troller. This makes the address bits "Don't Care" during an
AUTO REFRESH command. Each 128Mb SDRAM requires
4,096 AUTO REFRESH cycles every refresh period (t

REF

Providing a distributed AUTO REFRESH command will meet
the refresh requirement and ensure that each row is re-
freshed. Alternatively, 4,096 AUTO REFRESH commands can
be issued in a burst at the minimum cycle rate (t

), once

every refresh period (t

REF

SELF REFRESH*

The SELF REFRESH command can be used to retain data in
the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data without external clocking. The SELF REFRESH command
is initiated like an AUTO REFRESH command except CKE is
disabled (LOW). Once the SELF REFRESH command is reg-
istered, all the inputs to the SDRAM become "Don't Care,"
with the exception of CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to tRAS and may remain
in self refresh mode for an indefinite period beyond that.

The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock is
defined as a signal cycling within timing constraints speci-
fied for the clock pin) prior to CKE going back HIGH. Once
CKE is HIGH, the SDRAM must have NOP commands issued
(a minimum of two clocks) for t

XSR

, because time is re-

quired for the completion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH com-
mands must be issued as both SELF REFRESH and AUTO
REFRESH utilize the row refresh counter.

WRITE

The WRITE command is used to initiate a burst write access
to an active row. The value on the BA

, BA

inputs selects

the bank, and the address provided on inputs A

0-8

selects

the star ting column location. The value on input A

deter-

mines whether or not AUTO PRECHARGE is used. If AUTO
PRECHARGE is selected, the row being accessed will be
precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the I/Os is
written to the memory array subject to the DQM input logic
level appearing coincident with the data. If a given DQM
signal is registered LOW, the corresponding data will be
written to memory; if the DQM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE
will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (t

) after the PRECHARGE command is is-

sued. Input A

determines whether one or all banks are

to be precharged, and in the case where only one bank is
to be precharged, inputs BA

, BA

select the bank. Other-

wise BA

, BA

are treated as "Don't Care." Once a bank

has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.

AUTO PRECHARGE

AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished
by using A

to enable AUTO PRECHARGE in conjunction

with a specific READ or WRITE command. A precharge of
the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of
the READ or WRITE burst, except in the full-page burst
mode, where AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled or
disabled for each individual READ or WRITE command.

AUTO PRECHARGE ensures that the precharge is initiated at
the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge time
(t

) is completed. This is determined as if an explicit

PRECHARGE command was issued at the earliest possible time.

*Self Refresh available in commercial and industrial
temperatures only.

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WEDPN8M64V-XBX

P
P

P
Parameter/Condition

arameter/Condition

Symbol

Units

Min

Max

Supply Voltage

3.6

Input High Voltage: Logic 1; All inputs (21)

+ 0.3

Input Low Voltage: Logic 0; All inputs (21)

-0.3

0.8

Input Leakage Current: Any input 0V

-5

µA

(All other pins not under test = 0V)

Input Leakage Address Current (All other pins not under test = 0V)

-20

µA

Output Leakage Current: I/Os are disabled; 0V

OUT

-5

µA

Output Levels:

Output High Voltage (I

OUT

= -4mA)

2.4

Output Low Voltage (I

OUT

= 4mA)

0.4

DC E

LECTRICAL

HARACTERISTICS

AND

PERATING

ONDITIONS

OTES

1, 6)

= +3.3V ±0.3V; T

= -55°C

+125°C)

BSOLUTE

AXIMUM

ATINGS

P
P

P
Parameter

arameter

Unit

Voltage on V

, V

DDQ

Supply relative to Vss

-1 to 4.6

Voltage on NC or I/O pins relative to Vss

-1 to 4.6

Operating Temperature T

(Mil)

-55 to +125

°C

Operating Temperature T

(Ind)

-40 to +85

°C

Storage Temperature, Plastic

-55 to +150

°C

NOTE:

NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.

APACITANCE

OTE

Parameter

Symbol

Max

Unit

Input Capacitance: CLK

Addresses, BA

0-1

Input Capacitance

Input Capacitance: All other input-only pins

Input/Output Capacitance: I/Os

PECIFICATIONS

AND

ONDITIONS

OTES

1, 6, 11, 13)

= +3.3V ±0.3V; T

= -55°C

+125°C)

P
P

P
Parameter/Condition

arameter/Condition

Symbol

Max

Units

Operating Current: Active Mode;

CC1

650

Burst = 2; Read or Write; t

= t

(min); CAS latency = 3 (3, 18, 19)

Standby Current: Active Mode; CKE = HIGH; CS = HIGH;

CC3

200

All banks active after t

RCD

met; No accesses in progress (3, 12, 19)

Operating Current: Burst Mode; Continuous burst;

CC4

650

Read or Write; All banks active; CAS latency = 3 (3, 18, 19)

Self Refresh Current: CKE

0.2V (27)

CC7

BGA T

HERMAL

ESISTANCE

Description

Symbol

Symbol Max

Max

Units

Notes

Junction to Ambient

Theta JA 14.8

C/W

(No Airflow)

Junction to Ball

Theta JB 10.0

C/W

Junction to Case (Top) Theta JC

4.8

C/W

NOTE 1: Refer to BGA Thermal Resistance Correlation
application note at www.whiteedc.com in the application
notes section for modeling conditions.

1 0

White Electronic Designs Corporation · Phoenix AZ · (602) 437-1520

WEDPN8M64V-XBX

P
P

P
Parameter

arameter

Symbol

-100

-125

-133

Unit

Min

Max

Min

Max

Min

Max

Access time from CLK (pos. edge)

CL = 3

5.5

CL = 2

5.5

Address hold time

0.8

Address setup time

1.5

CLK high-level width

2.5

CLK low-level width

2.5

Clock cycle time (22)

CL = 3

7.5

CL = 2

CKE hold time

CKH

0.8

CKE setup time

CKS

1.5

CS, RAS, CAS, WE, DQM hold time

CMH

0.8

CS, RAS, CAS, WE, DQM setup time

CMS

1.5

Data-in hold time

0.8

Data-in setup time

1.5

Data-out high-impedance time

CL = 3 (10)

5.5

CL = 2 (10)

5.5

Data-out low-impedance time

Data-out hold time (load)

Data-out hold time (no load) (26)

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period (4,096 rows) Commercial, Industrial

REF

Refresh period (4,096 rows) Military

REF

AUTO REFRESH period

RFC

PRECHARGE command period

ACTIVE bank A to ACTIVE bank B command

RRD

Transition time (7)

0.3

1.2

0.3

1.2

0.3

1.2

WRITE recovery time

(23)

1 CLK + 7ns

1 CLK + 7.5ns

(24)

Exit SELF REFRESH to ACTIVE command

XSR

LECTRICAL

HARACTERISTICS

AND

ECOMMENDED

AC O

PERATING

HARACTERISTICS

OTES

5, 6, 8, 9, 11)

1 1

White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

WEDPN8M64V-XBX

AC F

UNCTIONAL

HARACTERISTICS

OTES

5,6,7,8,9,11)

P
P

P
Parameter/Condition

arameter/Condition

Symbol

-100

-125

-133

Units

READ/WRITE command to READ/WRITE command (17)

CCD

CKE to clock disable or power-down entry mode (14)

CKED

CKE to clock enable or power-down exit setup mode (14)

PED

DQM to input data delay (17)

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay (17)

DWD

Data-in to ACTIVE command (15)

DAL

Data-in to PRECHARGE command (16)

DPL

Last data-in to burst STOP command (17)

BDL

Last data-in to new READ/WRITE command (17)

CDL

Last data-in to PRECHARGE command (16)

RDL

LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)

MRD

Data-out to high-impedance from PRECHARGE command (17)

CL = 3

ROH

CL = 2

ROH

NOTES:

NOTES:
1. All voltages referenced to V

2. This parameter is not tested but guaranteed by design. f = 1 MHz, T

25°C.

3. I

is dependent on output loading and cycle rates. Specified values

are obtained with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which

proper operation over the full temperature range is ensured.

6. An initial pause of 100ms is required after power-up, followed by two

AUTO REFRESH commands, before proper device operation is ensured.
(V

must be powered up simultaneously.) The two AUTO REFRESH

command wake-ups should be repeated any time the t

REF

refresh

requirement is exceeded.

7. AC characteristics assume t

= 1ns.

8. In addition to meeting the transition rate specification, the clock and CKE

must transit between V

and V

(or between V

and V

) in a

monotonic manner.

9. Outputs measured at 1.5V with equivalent load:

10. t

defines the time at which the output achieves the open circuit

condition; it is not a reference to V

or V

. The last valid data

element will meet t

before going High-Z.

11. AC timing and I

tests have V

= 0V and V

= 3V, with timing

referenced to 1.5V crossover point.

50pF

12. Other input signals are allowed to transition no more than once every

two clocks and are otherwise at valid V

or V

levels.

13. I

specifications are tested after the device is properly initialized.

14. Timing actually specified by t

CKS

; clock(s) specified as a reference only

at minimum cycle rate.

15. Timing actually specified by t

plus t

; clock(s) specified as a

reference only at minimum cycle rate.

16. Timing actually specified by t

17. Required clocks are specified by JEDEC functionality and are not

dependent on any timing parameter.

18. The I

current will decrease as the CAS latency is reduced. This is due

to the fact that the maximum cycle rate is slower as the CAS latency is
reduced.

19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. V

overshoot: V

(MAX) = V

+ 2V for a pulse width

3ns, and the

pulse width cannot be greater than one third of the cycle rate. V

undershoot: V

(MIN) = -2V for a pulse width

3ns.

22. The clock frequency must remain constant (stable clock is defined as a

signal cycling within timing constraints specified for the clock pin) during
access or precharge states (READ, WRITE, including t

, and

PRECHARGE commands). CKE may be used to reduce the data rate.

23. Auto precharge mode only. The precharge timing budget (t

) begins

7.5ns/7ns after the first clock delay, after the last WRITE is executed.

24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.

1 2

White Electronic Designs Corporation · Phoenix AZ · (602) 437-1520

WEDPN8M64V-XBX

DEVICE GR

DEVICE GRADE:

ADE:

M = Military

-55°C to +125°C

I = Industrial

-40°C to +85°C

C = Commercial

0°C to +70°C

P
P

P
PA

ACK

CKA

AGE:

GE:

B = 219 Plastic Ball Grid Array (PBGA)

FREQUENC

FREQUENCY (MHz)

Y (MHz)

100 = 100MHz

125 = 125MHz

133 = 133MHz*

3.3V P

3.3V Power Supply

ower Supply

CONFIGUR

CONFIGURA

ATION, 8M x 64

TION, 8M x 64

SDR

SDRAM

PL A

A STIC

STIC

WHITE ELECTRONIC DESIGNS CORP

WHITE ELECTRONIC DESIGNS CORP.....

*133MHz available in commercial temperature only.

WED

P
P

P
P N

8M 64

8M 64 V -

V -

V - XXX

XXX

XXX B

ACKAGE

740: 219 P

LASTIC

ALL

RID

RRAY

(PBGA)

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

RDERING

NFORMATION

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

R
P

K
J

F
E

C
B

219 x

0.762 (0.030) NOM

1.27 (0.050)
NOM

25.1 (0.988) SQ. MAX

2.03 (0.080)

MAX

0.61 (0.024) NOM

19.05 (0.750) NOM

19.05 (0.750)

NOM

OTTOM

IEW

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