1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPS512K32V-XBX
White Electronic Designs
512Kx32 SRAM 3.3V MULTI-CHIP PACKAGE
n Low Power CMOS
n TTL Compatible Inputs and Outputs
n Fully Static Operation:
No clock or refresh required.
n Three State Output.
Note: This data sheet describes a product that is subject to change without notice.
FEATURES
n Access Times of 12, 15, 17, 20ns
n Packaging
143 PBGA , 16mm x 18mm, 288mm
2
n Organized as 512Kx32; User Configurable as 1Mx16 or
2Mx8
n Commercial, Industrial and Military Temperature Ranges
n Low Voltage Operation:
3.3V 10% Power Supply
P
IN
C
ONFIGURATION
F
OR
WEDPS512K32V-XBX
February 2003 Rev. 4
P
IN
D
ESCRIPTION
I/O
0-31
Data Inputs/Outputs
A
0-18
Address Inputs
WE
1-4
Write Enables
CS
1-4
Chip Selects
OE
Output Enable
V
CC
Power Supply
GND
Ground
NC
Not Connected
B
LOCK
D
IAGRAM
512K x 8
8
I/O
0-7
WE
CS
1
1
512K x 8
8
I/O
8-15
WE
CS
2
2
512K x 8
8
I/O
16-23
WE
CS
3
3
512K x 8
8
I/O
24-31
WE
CS
4
4
A
0
-
18
OE
T
OP
V
IEW
1
2
3
4
5
6
7
8
9
10
11
12
A
-
A 2
A 1
A 0
GND
GND
V
C C
V
C C
A18
A17
A16
GND
B
CS2
A 3
A 4
D 1 4
D 1 5
N C
CS4
D 2 4
D 2 5
O E
A15
N C
C
D 9
D 8
N C
D 1 2
D 1 3
GND
V
C C
D 2 6
D 2 7
WE4
D 3 1
D 3 0
D
D 1 0
D 1 1
GND
GND
GND
GND
V
C C
V
C C
V
C C
V
C C
D 2 8
D 2 9
E
WE2
GND
GND
GND
GND
GND
V
C C
V
C C
V
C C
V
C C
V
C C
N C
F
GND
GND
GND
GND
GND
GND
V
C C
V
C C
V
C C
V
C C
V
C C
V
C C
G
V
C C
V
C C
V
C C
V
C C
V
C C
V
C C
GND
GND
GND
GND
GND
GND
H
CS1
V
C C
V
C C
V
C C
V
C C
V
C C
GND
GND
GND
GND
GND
N C
J
D 1
D 0
V
C C
V
C C
V
C C
V
C C
GND
GND
GND
GND
D 2 3
D 2 2
K
D 2
D 3
N C
D 7
D 5
V
C C
GND
D 1 7
D 1 6
CS3
D 2 0
D 2 1
L
WE1
A 6
A 5
D 6
D 4
N C
WE3
D 1 9
D 1 8
A14
A13
N C
M
GND
A 7
A 8
A 9
V
C C
V
C C
GND
GND
A10
A11
A12
V
C C
2
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPS512K32V-XBX
White Electronic Designs
C
APACITANCE
(T
A
= +25C)
Parameter
Symbol
Conditions
Max Unit
OE capacitance
C
OE
V
IN
= 0 V, f = 1.0 MHz
30
pF
WE
1-4
capacitance
C
WE
V
IN
= 0 V, f = 1.0 MHz
10
pF
CS
1-4
capacitance
C
CS
V
IN
= 0 V, f = 1.0 MHz
10
pF
Data I/O capacitance
C
I/O
V
I/O
= 0 V, f = 1.0 MHz
10
pF
Address input capacitance
C
AD
V
IN
= 0 V, f = 1.0 MHz
30
pF
This parameter is guaranteed by design but not tested.
T
RUTH
T
ABLE
A
BSOLUTE
M
AXIMUM
R
ATINGS
Parameter
Symbol
Min
Max
Unit
Operating Temperature
T
A
-55
+125
C
Storage Temperature
T
STG
-65
+150
C
Signal Voltage Relative to GND
V
G
-0.5
4.6
V
Junction Temperature
T
J
150
C
Supply Voltage
V
CC
-0.5
4.6
V
CS
OE
WE
Mode
Data I/O
Power
H
X
X
Standby
High Z
Standby
L
L
H
Read
Data Out
Active
L
X
L
Write
Data In
Active
L
H
H
Out Disable
High Z
Active
R
ECOMMENDED
O
PERATING
C
ONDITIONS
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
3.0
3.6
V
Input High Voltage
V
IH
2.2
V
CC
+ 0.3
V
Input Low Voltage
V
IL
-0.3
+0.8
V
DC C
HARACTERISTICS
(V
CC
= 3.3V 0.3V, T
A
= -55C to +125C)
Parameter
Sym
Conditions
Units
Min
Max
Input Leakage Current
I
LI
V
IN
= GND to V
CC
10
A
Output Leakage Current
I
LO
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
10
A
Operating Supply Current (x 32 Mode)
I
CC
x 32
CS = V
IL
, OE = V
IH
, f = 5MHz, V
CC
= 3.6V
400
mA
Standby Current
I
SB
CS = V
IH
, OE = V
IH
, f = 5MHz, V
CC
= 3.6V
120
mA
Output Low Voltage
V
OL
I
OL
= 4.0mA
0.4
V
Output High Voltage
V
OH
I
OH
= -4.0mA
2.4
V
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V.
NOTE: Contact factory for low power option.
BGA T
HERMAL
R
ESISTANCE
Description
Symbol
Max
Unit
Notes
Junction to Ambient (No Airflow)
Theta JA
16.9
C/W
1
Junction to Ball
Theta JB
11.3
C/W
1
Junction to Case (Top)
Theta JC
9.8
C/W
1
NOTE:
Refer to Application Note "PBGA Thermal Resistance Correlation" at
www.whiteedc.com in the application notes section for modeling conditions.
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPS512K32V-XBX
White Electronic Designs
AC T
EST
C
IRCUIT
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75
W.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
AC T
EST
C
ONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 2.5
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
AC C
HARACTERISTICS
(V
CC
= 3.3V, T
A
= -55C to +125C)
Parameter
Symbol -12
-15 -17 -20 Units
Read Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
1 2
1 5
1 7
2 0
ns
Address Access Time
t
A A
1 2
1 5
1 7
2 0
ns
Output Hold from Address Change
t
OH
0
0
0
0
ns
Chip Select Access Time
t
A C S
1 2
1 5
1 7
2 0
ns
Output Enable to Output Valid
t
OE
7
8
8
1 0
ns
Chip Select to Output in Low Z
t
C L Z
1
1
1
1
1
ns
Output Enable to Output in Low Z
t
OLZ
1
0
0
0
0
ns
Chip Disable to Output in High Z
t
CHZ
1
7
8
8
1 0
ns
Output Disable to Output in High Z
t
OHZ
1
7
8
8
1 0
ns
1. This parameter is guaranteed by design but not tested.
AC C
HARACTERISTICS
(V
CC
= 3.3V, T
A
= -55C to +125C)
Parameter
Symbol -12
-15 -17 -20 Units
Write Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
1 2
1 5
1 7
2 0
ns
Chip Select to End of Write
t
CW
1 0
1 2
1 2
1 4
ns
Address Valid to End of Write
t
A W
1 0
1 2
1 2
1 4
ns
Data Valid to End of Write
t
DW
8
9
9
1 0
ns
Write Pulse Width
t
WP
1 0
1 2
1 4
1 4
ns
Address Setup Time
t
AS
0
0
0
0
ns
Address Hold Time
t
AH
0
0
0
0
ns
Output Active from End of Write
t
OW
1
2
2
3
3
ns
Write Enable to Output in High Z
t
WHZ
1
7
8
8
9
ns
Data Hold Time
t
DH
0
0
0
0
ns
1. This parameter is guaranteed by design but not tested.
Current Source
Current Source
I
OL
I
OH
C
eff
= 50 pf
D.U.T.
V
Z
1.5V
(Bipolar Supply)
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPS512K32V-XBX
White Electronic Designs
WS32K32-XHX
T
IMING
W
AVEFORM
- R
EAD
C
YCLE
W
RITE
C
YCLE
- CS C
ONTROLLED
W
RITE
C
YCLE
- WE C
ONTROLLED
ADDRESS
DATA I/O
PREVIOUS DATA VALID
DATA VALID
READ CYCLE 1 (CS = OE = V
IL
, WE = V
IH
)
t
OH
t
AA
t
RC
ADDRESS
t
RC
CS
OE
DATA I/O
t
AA
t
ACS
t
CHZ
t
CLZ
t
OE
t
OLZ
t
OHZ
HIGH IMPEDANCE
DATA VALID
READ CYCLE 2 (WE = V
IH
)
ADDRESS
t
WC
t
AW
t
AS
t
AH
t
CW
t
WP
t
DW
t
DH
CS
WE
DATA I/O
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
ADDRESS
t
WC
t
AW
t
CW
t
AH
t
AS
t
WP
t
WHZ
t
DW
t
OW
t
DH
DATA VALID
CS
DATA I/O
WE
WRITE CYCLE 1, WE CONTROLLED
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPS512K32V-XBX
White Electronic Designs
P
ACKAGE
756: 143 B
ALL
G
RID
A
RRAY
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
0.61 (0.024)
BSC
1.27
(0.050)
BSC
A
B
C
D
E
F
G
H
J
K
L
M
13.97 (0.550)
BSC
16.25 (0.640)
MAX
18.25 (0.719)
MAX
13.97 (0.550)
BSC
2.21 (0.087)
MAX
BOTTOM VIEW
12 11 10 9 8 7 6 5 4 3 2 1
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPS512K32V-XBX
White Electronic Designs
O
RDERING
I
NFORMATION
WHITE ELECTRONIC DESIGNS CORP.
PLASTIC
SRAM
ORGANIZATION, 512Kx32
User configurable as 1Mx16 or 2Mx8
Low Voltage Supply 3.3V
10%
ACCESS TIME (ns)
PACKAGE TYPE:
B = 143 PBGA, 16mm x 18mm, 288mm
2
DEVICE GRADE:
M = M
ILITARY
S
CREENED
-55C
TO
+125C
I = I
NDUSTRIAL
-40C
TO
85C
C = C
OMMERCIAL
0C
TO
+70C
WED P S 512K 32 V - XX X X
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPS512K32V-XBX
White Electronic Designs
Document Title
512K x 32 SRAM PBGA Multi-Chip Package
Revision History
Rev #
History
Release Date
Status
Rev 0
Initial Release
March 2002
Advanced
Rev 1
Changes (Pg. 1)
March 2002
Advanced
1.1 Switch Rows and Columns header position
Rev 2
Changes (Pg. 1)
May 2002
Advanced
1.1 Switch Rows and Columns header position
(Pg. 1)
Rev 3
Changes (Pg. 1, 5)
May 2002
Advanced
1.1 Remove excess white space from package drawing for
to create a consistent accurate style.
Rev 4
Changes (Pg. 1, 2, 7)
January 2003
Final
1.1 Add Thermal Resistance Table
Change product status to Final
PDF 
ZIP