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White Electronic Designs

WEDPZ512K72S-XBX

Fast clock speed: 150, 133, and 100MHz

Fast access times: 3.8ns, 4.2ns, and 5.0ns

Fast OE access times: 3.8ns, 4.2ns, and 5.0ns

High performance 3-1-1-1 access rate

2.5V ± 5% power supply

Common data inputs and data outputs

Byte write enable and global write control

Six chip enables for depth expansion and address

pipeline

Internally self-timed write cycle

Burst control pin (interleaved or linear burst sequence)

Automatic power-down for portable applications

Commercial, industrial and military temperature ranges

Packaging:

152 PBGA package 17 x 23mm

512K x 72 Synchronous Pipeline Burst ZBL SRAM

May 2003 Rev. 5

UNCTIONAL

LOCK

IAGRAM

*PRELIMINARY

FEATURES

DESCRIPTION

BENEFITS

30% space savings compared to equivalent TQFP

solution

Reduced part count

24% I/O reduction

Laminate interposer for optimum TCE match

Low Profile

Reduce layer count for board routing

Suitable for hi-reliability applications

User configurable as 1M x 36 or 2M x 18

Upgradable to 1M x 72 (contact factory for availability)

The WEDC SyncBurst - SRAM employs high-speed, low-

power CMOS design that is fabricated using an advanced

CMOS process. WEDCs 32Mb SyncBurst SRAMs integrate

two 512K x 36 SSRAMs into a single BGA package to pro-

vide 512K x 72 configuration. All synchronous inputs pass

through registers controlled by a positive-edge-triggered

single-clock input (CLK). The ZBL or Zero Bus Latency

Memory utilizes all the bandwidth in any combination of

operating cycles. Address, data inputs, and all control sig-

nals except output enable and linear burst order are syn-

chronized to input clock. Burst order control must be tied

High or Low. Asynchronous inputs include the sleep

mode enable (ZZ). Output Enable controls the outputs at

any given time. Write cycles are internally self-timed and

initiated by the rising edge of the clock input. This feature

eliminates complex off-chip write pulse generation and pro-

vides increased timing flexibility for incoming signals.

*Preliminary product that is not fully characterized, non-qualified and is subject

to change without notice.

0-18

BWa

BWb

BWc

BWd

CLK

CKE

CS1

CS2

ADV

LBO

BWa

BWb

BWc

BWd

CLK

CKE

CS1

CS2

ADV

LBO

DQPA

DQA

0-7

DQPB

DQB

0-7

DQPC

DQC

0-7

DQPD

DQD

0-7

DQPA

DQA

0-7

DQPB

DQB

0-7

DQPC

DQC

0-7

DQPD

DQD

0-7

512K x 36 SSRAM

BWe

BWf

BWg

BWh

WE1

OE1

CLK1

CKE1

CS1

CS2

ADV1

BWa

BWb

BWc

BWd

WEO

OEO

CLK

CKE

CS1

CS2

ADV

LBO

512K x 36 SSRAM

DQPA

DQA

0-7

DQPB

DQB

0-7

DQPC

DQC

0-7

DQPH

DQD

0-7

DQPE

DQE

0-7

DQPF

DQF

0-7

DQPG

DQG

0-7

DQPH

DQH

0-7

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WEDPZ512K72S-XBX

White Electronic Designs

ONFIGURATION

(TOP VIEW)

NOTE: DNU means Do Not Use and are reserved for future use.

* Pin F

reserved for A

upgrade to 1M x 72.

ADV

DQB

DNU

DQA

CKE

DQB

DQA

CLK

CS2

DQC

DQPC

DQPB

DQB

DQD

DQA

BWa

BWb

DQC

DQD

DQA

DQPA

BWc

BWd

DQC

DDQ

DQD

DQPD

CS1

CS2

DQC

DDQ

DQD

DNU*

DQC

DQD

DQC

DQD

DQF

DQD

DQF

FQF

DQD

DQF

DQE

ADV

DQF

DDQ

DQE

CKE

DQPF

DDQ

DQE

LBO

CLK

CS2

DQF

DQE

BWe

BWfDQF

DQG

DQH

DQE

DQPE

BWg

BWh

DQG

DQH

DQPH

CS1

CS2

DQG

DQPG

DQG

DQH

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White Electronic Designs

WEDPZ512K72S-XBX

BURST SEQUENCE TABLE

NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed.

Write operation occurs when WE is driven low at the

rising edge of the clock. BW[h:a] can be used for byte

write operation. The pipe-lined ZBL SSRAM uses a

late-late write cycle to utilize 100% of the bandwidth. At

the first rising edge of the clock, WE and address are

registered, and the data associated with that address

is required two cycles later.
Subsequent addresses are generated by ADV High for

the burst access as shown below. The starting point of

the burst seguence is provided by the external address.

The burst address counter wraps around to its initial

state upon completion. The burst sequence is deter-

mined by the state of the LBO pin. When this pin is low,

linear burst sequence is selected. And when this pin is

high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When

ZZ is driven high, the SRAM will enter a Power Sleep

Mode after two cycles. At this time, internal state of the

SRAM is preserved. When ZZ returns to low, the SRAM

operates after two cycles of wake up time.

(Interleaved Burst, LBO = High)

Case 1 Case 2 Case 3 Case 4

LBO Pin High A1 A0 A1 A0 A1 A0 A1 A0

First Address

Fourth Address 1

(Linear Burst, LBO = Low)

Case 1 Case 2 Case 3 Case 4

LBO Pin High A1 A0 A1 A0 A1 A0 A1 A0

First Address

Fourth Address 1

The WEDPZ512K72S-XBX is an ZBL SSRAM designed

to sustain 100% bus bandwidth by eliminating turn-

around cycle when there is transition from Read to

Write, or vice versa. All inputs (with the exception of OE,

LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the

ADV input. Subsequent burst addresses can be inter-

nally generated by the burst advance pin (ADV). ADV

should be driven to Low once the device has been

deselected in order to load a new address for next

operation.
Clock Enable (CKE) pin allows the operation of the

chip to be suspended as long as necessary. When

CKE is high, all synchronous inputs are ignored and

the internal device registers will hold their previous

values. NBL SSRAM latches external address and ini-

tiates a cycle when CKE and ADV are driven low at the

rising edge of the clock.
Output Enable (OE) can be used to disable the output at

any given time. Read operation is initiated when at the

rising edge of the clock, the address presented to the

address inputs are latched in the address register, CKE

is driven low, the write enable input signals WE are

driven high, and ADV driven low. The internal array is

read between the first rising edge and the second ris-

ing edge of the clock and the data is latched in the out-

put register. At the second clock edge the data is driven

out of the SRAM. During read operation OE must be

driven low for the device to drive out the requested data.

FUNCTION DESCRIPTION

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WEDPZ512K72S-XBX

White Electronic Designs

TRUTH TABLES

YNCHRONOUS

RUTH

ABLE

RITE

RUTH

ABLE

BWa

BWb

BWc

BWd

Operation

Read

Write Byte a

Write Byte b

Write Byte c

Write Byte d

Write All Bytes

Write Abort/NOP

CEx ADVWE BWx OE

CKE CLK Address Accessed

Operation

N/A

Deselect

N/A

Continue Deselect

External Address

Begin Burst Read Cycle

Next Address

Continue Burst Read Cycle

External Address

NOP/Dummy Read

Next Address

Dummy Read

External Address

Begin Burst Write Cycle

Next Address

Continue Burst Write Cycle

N/A

NOP/Write Abort

Next Address

Write Abort

Current Address

Ignore Clock

NOTES:

1. X means Dont Care.

2. The rising edge of clock is symbolized by ( ).

3. A continue deselect cycle can only be entered if a deselect cycle is executed first.

4. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

5. Operation finally depends on status of asynchronous input pins (ZZ and OE).

6. CEx refers to the combination of CS

, CS

and CS

NOTES:

1. X means Dont Care.

2. All inputs in this table must meet setup and hold time around the rising edge of CLK ( ).

3. Replace BW

with BW

, BW

, with BW

, BW

with BW

and BW

with BW

for operation of IC

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White Electronic Designs

WEDPZ512K72S-XBX

150

133

100

Description

Symbol Conditions

MHz

MHz Units Notes

(Max) (Max) (Max)

Power Supply

Device Selected; All Inputs £ V

or ³ V

; Cycle

700

650

600

Current: Operating

Time ³ T

CYC

MIN; V

= MAX; Output Open

Power Supply

SB2

Device Deselected; V

= MAX; All Inputs £ V

IL or

³ V

Current: Standby

All Inputs Static; CLK Frequency = MAX

120

Output Open, ZZ ³ V

DD -

0.2V

Clock Running

Device Deselected; V

= MAX; All Inputs

180

160

Standby Current

£ V

+ 0.2 or V

- 0.2; f = max ; ZZ £ V

BSOLUTE

AXIMUM

ATINGS

Voltage or any other pin relative to V

-0.3V to +3.6V

Voltage on V

supply relative to V

-0.3V to +3.6V

Storage temperature (BGA)

-55°C to +150°C

LECTRICAL

HARACTERISTICS

(-55°C TA +125°C)

*Stress greater than those listed under Absolute Maximum Ratings: may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions greater than those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum

rating condtions for extended periods may affect reliability.

Description

Symbol

Conditions

Min

Max

Units

Notes

Input High (Logic 1) Voltage

1.7

+0.3

Input Low (Logic 0) Voltage

-0.3

0.7

Input Leakage Current

DD =

ax,

0V V

-4

µA

Output Leakage Current

Output(s) Disabled, V

OUT

= V

to V

DDQ

-2

µA

Output High Voltage

= -1.0mA

2.0

---

Output Low Voltage

= 1.0mA

---

0.4

Supply Voltage

2.375

2.625

I/O Power Suply

DDQ

2.375

2.625

NOTES:

1. All voltages referenced to V

(GND)

2. ZZ pin has an internal pull-up, and input leakage = ± 20 µA.

DC C

HARACTERISTICS

(-55°C TA + 125°C)

BGA C

APACITANCE

= + 25°C, f = 1MH

)

NOTES: 1. This parameter is not tested but guaranteed by design.

Description

Symbol Max Units Notes

Control Input Capacitance (LBO, zz)

Control Input Capacitance

Input/Output Capacitance (DQ)

Address Capacitance

Clock Capacitance

NOTES: 1. I

is specified with no output current and increases with faster cycle times.

increases with faster cycle times and greater output loading.

HERMAL

ESISTANCE

Parameter

Symbol Max Unit

Thermal Resistance: Die Junction to Ambient

qJA

28.7 °C/W

Thermal Resistance: Die Junction to Ball

qJB

16.0 °C/W

Thermal Resistance: Die Junction to Case

qJC

7.1 °C/W

Note: Refer to Application Note PBGA Thermal Resistance Corrleation

for further information regarding WEDCs thermal modeling.

White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com

WEDPZ512K72S-XBX

White Electronic Designs

AC C

HARACTERISTICS

(-55°C T

+125°C)

NOTES:

1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low

and CSx is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this

device is chip selected.

2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.

3. A write cycle is defined by WE low having been registered into the device at ADV Low. A Read cycle is defined by WE

High with ADV Low. Both cases must meet setup and hold times.

UTPUT

OAD

(A)

UTPUT

OAD

(B)

(FOR T

LZC

, T

LZOE

, T

HZOE

AND

HZC

)

Dout

Zo=50

RL=50

VL=1.25V

50pF*

Dout

1538

5pF*

+2.5V

1667

*Including Scope and Jig Capacitance

AC T

EST

ONDITIONS

Parameter

Value

Input Pulse Level

0 to 2.5V

Input Rise and Fall Time

1.0V/ns

Input and Output Timing Reference Levels

1.25V

Output Load

See Output Load (A & B)

Symbol

150MHz

133MHz

100MHz

Parameter

Min

Max

Min

Max

Min

Max

Units

Clock Time

C Y C

6.7

7.5

10.0

n s

Clock Access Time

3.8

4.2

5.0

n s

Output enable to Data Valid

3.8

4.2

5.0

n s

Clock High to Output Low-Z

L Z C

1.5

n s

Output Hold from Clock High

1.5

n s

Output Enable Low to output Low-Z

LZOE

0.0

n s

Output Enable High to Output High-Z

HZOE

3.0

3.5

n s

Clock High to Output High-Z

HZC

3.0

3.5

n s

Clock High Pulse Width

2.5

3.0

n s

Clock Low Pulse Width

2.5

3.0

n s

Address Setup to Clock High

A S

1.5

n s

CKE Setup to Clock High

C E S

1.5

n s

Data Setup to Clock High

D S

1.5

n s

Write Setup to Clock High

1.5

n s

Address Advance to Clock High

A D V S

1.5

n s

Chip Select Setup to Clock High

C S S

1.5

n s

Address Hold to Clock high

A H

0.5

n s

CKE Hold to Clock High

C E H

0.5

n s

Data Hold to Clock High

0.5

n s

Write Hold to Clock High

0.5

n s

Address Advance to Clock High

ADVH

0.5

n s

Chip Select Hold to Clock High

C S H

0.5

---

0.5

n s

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White Electronic Designs

WEDPZ512K72S-XBX

SNOOZE MODE is a low-current, power-down mode

in which the device is deselected and current is re-

duced to ISB

. The duration of SNOOZE MODE is

dictated by the length of time Z is in a HIGH state. After

the device enters SNOOZE MODE, all inputs except ZZ

become gated inputs and are ignored. ZZ is an asyn-

chronous, active HIGH input that causes the device to

enter SNOOZE MODE.

When ZZ becomes a logic HIGH, ISB

is guaranteed

after the setup time t

is met. Any READ or WRITE

operation pending when the device enters SNOOZE

MODE is not guaranteed to complete successfully.

Therefore, SNOOZE MODE must not be initiated until

valid pending operations are completed.

NOOZE

ODE

Description

Conditions

Symbol

Min

Max

Units

Current during SNOOZE MODE

ZZ ³ V

SB2Z

ZZ active to input ignored

tzz

cycle

ZZ inactive to input sampled

trzz

cycle

ZZ active to snooze current

ZZI

cycle

ZZ inactive to exit snooze current

RZZI

FIG. 2

SNOOZE MODE

NOOZE

ODE

IMING

IAGRAM

SUPPLY

CLOCK

ALL INPUTS

(except ZZ)

Output (Q)

ZZI

RZZ

RZZI

HIGH-Z

DESELECT or READ Only

ISB2Z

DON'T CARE

Deselect or Read Only

Normal

Operation Cycle

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White Electronic Designs

WEDPZ512K72S-XBX

0.61 (0.024) ± 0.08 (0.003)

BSC

1.27

(0.050)

BSC

20.32 (0.800)

BSC

9 8 7 6 5 4 3 2 1

23.20 (0.913)

MAX

17.2 (0.677)

MAX

10.16 (0.400)

BSC

2.20 (0.087)

MAX

BOTTOM VIEW

0.76 (0.030) ± 0.08 (0.003)

DEVICE GRADE:

M = Military

-55°C to +125°C

I = Industrial

-40°C to +85°C

C = Commercial

0°C to +70°C

PACKAGE:

B = 152 Plastic Ball Grid Array (PBGA)

FREQUENCY (MHz)

100 = 100MHz
133 = 133MHz
150 = 150MHz

2.5 V Voltage

CONFIGURATION, 512K x 72

SSRAM ZBL

PLASTIC

WHITE ELECTRONIC DESIGNS CORP.

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

WED P Z 512K 72 S - XXX B X

ORDERING INFORMATION

PACKAGE DIMENSION:

152 BUMP PBGA

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WEDPZ512K72S-XBX

White Electronic Designs

Document Title

512K x 72 Synchronous SRAM NBL

Revision History

Rev #

History

Release Date

Status

Rev 0

Initial Release

February 2001

Advanced

Rev 1

Changes (Pg. 1, 5, 6, 13)

April 2001

Advanced

1.1 Block Diagram: Change DQD to DQPD, Font Consistency
1.2 Electrical Characteristics Note 2: Change reference to mA instead of MA.
1.3 DC Characteristics: Adjust location of Units & Notes for ISB2.
1.4 AC Characteristics: Change temperature range to (-55°C £ T

£ +125°C)

1.5 Package Dimension: Adjust length line to end of package
1.6 Block Diagram: Adjust look for consistency
1.7 DC Characteristics: ISB2 condition should read All Inputs £ V

or ³ V

instead of > V

1.8 Figure 2: Inputs transition should not be shown fully connected.
1.9 Figure 6: Unknown text deleted from timing diagram
1.10 Package Dimension: Ball diameter arrow corrected to point to ball.

Rev 2

Change (1)

November 2001

Preliminary

1.1 Change status from Advanced to Preliminary

Rev 3

Changes (1, 2)

November 2001

Preliminary

1.1 Block Diagram: Address lines should be A0-18
1.2 Pin Configuration: Add Note *Pin F8 reserved for A19 upgrade to 1Mx72.

Rev 4

Changes (1, 5)

November 2002

Preliminary

1.1 BGA Capacitance: Remove references to temperature in individual conditions
1.2 Change C

from 10pF to 8pF

1.3 Change C

from 20pF to 16pF

1.4 Change C

from 7pF to 6pF

1.5 Add Control Input Capacitance (C

) 16pF

Rev 5

Changes (5)

May 2003

Preliminary

Add Thermal Resistance table

Update current values

Update package mechanical drawing

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