White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

WEDPZ512K72V-XBX

FEATURES

Fast clock speed: 150, 133, and 100MHz

Fast access times: 3.8ns, 4.2ns, and 5.0ns

Fast OE access times: 3.8ns, 4.2ns, and 5.0ns

High performance 3-1-1-1 access rate

3.3V ± 5% power supply

I/O supply voltage 3.3V or 2.5V

Common data inputs and data outputs

Byte write enable and global write control

Six chip enables for depth expansion and

address pipeline

Internally self-timed write cycle

Burst control pin (interleaved or linear burst
sequence)

Automatic power-down for portable applications

Commercial, industrial and military temperature
ranges

Packaging:

· 152 PBGA package 17 x 23mm

BENEFITS

30% space savings compared to equivalent
TQFP solution

Reduced part count

24% I/O reduction

Laminate interposer for optimum TCE match

Low Profile

Reduce layer count for board routing

Suitable for hi-reliability applications

User configurable as 1M x 36 or 2M x 18

Upgradable to 1M x 72 (contact factory for availability)

512K x 72 Synchronous Pipeline Burst ZBL SRAM

November 2003 Rev. 6

UNCTIONAL

LOCK

IAGRAM

DESCRIPTION

The WEDC SyncBurst - SRAM employs high-speed,
low-power CMOS design that is fabricated using an
advanced CMOS process. WEDC's 32Mb SyncBurst
SRAMs integrate two 512K x 36 SSRAMs into a single
BGA package to provide 512K x 72 configuration. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK).
The ZBL or Zero Bus Latency Memory utilizes all the
bandwidth in any combination of operating cycles. Ad-
dress, data inputs, and all control signals except out-
put enable and linear burst order are synchronized to
input clock. Burst order control must be tied "High or
Low." Asynchronous inputs include the sleep mode
enable (ZZ). Output Enable controls the outputs at any
given time. Write cycles are internally self-timed and
initiated by the rising edge of the clock input. This fea-
ture eliminates complex off-chip write pulse genera-
tion and provides increased timing flexibility for incom-
ing signals.

*Product is not qualified and is subject to change without notice.

0-18

BWa

BWb

BWc

BWd

CLK

CKE

CS1

CS2

ADV

LBO

BWa

BWb

BWc

BWd

CLK

CKE

CS1

CS2

ADV

LBO

DQPA

DQA

0-7

DQPB

DQB

0-7

DQPC

DQC

0-7

DQPD

DQD

0-7

DQPA

DQA

0-7

DQPB

DQB

0-7

DQPC

DQC

0-7

DQPD

DQD

0-7

512K x 36 SSRAM

BWe

BWf

BWg

BWh

WE1

OE1

CLK1

CKE1

CS1

CS2

ADV1

BWa

BWb

BWc

BWd

WEO

OEO

CLK

CKE

CS1

CS2

ADV

LBO

512K x 36 SSRAM

DQPA

DQA

0-7

DQPB

DQB

0-7

DQPC

DQC

0-7

DQPH

DQD

0-7

DQPE

DQE

0-7

DQPF

DQF

0-7

DQPG

DQG

0-7

DQPH

DQH

0-7

White Electronic Designs Corporation · Phoenix AZ · (602) 437-1520

WEDPZ512K72V-XBX

ONFIGURATION

(TOP VIEW)

NOTE: DNU means Do Not Use and are reserved for future use.
* Pin F

reserved for A

upgrade to 1M x 72

ADV

DQB

DNU

DQA

CKE

DQB

DQA

CLK

CS2

DQC

DQPC

DQPB

DQB

DQD

DQA

BWa

BWb

DQC

DQD

DQA

DQPA

BWc

BWd

DQC

DDQ

DQD

DQPD

CS1

CS2

DQC

DDQ

DQD

DNU*

DQC

DQD

DQC

DQD

DQF

DQD

DQF

FQF

DQD

DQF

DQE

ADV

DQF

DDQ

DQE

CKE

DQPF

DDQ

DQE

LBO

CLK

CS2

DQF

DQE

BWe

BWf

DQF

DQG

DQH

DQE

DQPE

BWg

BWh

DQG

DQH

DQPH

CS1

CS2

DQG

DQPG

DQG

DQH

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WEDPZ512K72V-XBX

BURST SEQUENCE TABLE

NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed.

Write operation occurs when WE is driven low at the
rising edge of the clock. BW[h:a] can be used for byte
write operation. The pipe-lined ZBL SSRAM uses a
late-late write cycle to utilize 100% of the bandwidth. At
the first rising edge of the clock, WE and address are
registered, and the data associated with that address
is required two cycles later.

Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of
the burst seguence is provided by the external address.
The burst address counter wraps around to its initial
state upon completion. The burst sequence is deter-
mined by the state of the LBO pin. When this pin is low,
linear burst sequence is selected. And when this pin is
high, Interleaved burst sequence is selected.

During normal operation, ZZ must be driven low. When
ZZ is driven high, the SRAM will enter a Power Sleep
Mode after two cycles. At this time, internal state of the
SRAM is preserved. When ZZ returns to low, the SRAM
operates after two cycles of wake up time.

(Interleaved Burst, LBO = High)

Case 1

Case 2

Case 3

Case 4

LBO Pin High

First Address

Fourth Address

(Linear Burst, LBO = Low)

Case 1

Case 2

Case 3

Case 4

LBO Pin High

First Address

Fourth Address

The WEDPZ512K72V-XBX is an ZBL SSRAM designed
to sustain 100% bus bandwidth by eliminating turn-
around cycle when there is transition from Read to
Write, or vice versa. All inputs (with the exception of OE,
LBO and ZZ) are synchronized to rising clock edges.

All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be inter-
nally generated by the burst advance pin (ADV). ADV
should be driven to Low once the device has been
deselected in order to load a new address for next
operation.

Clock Enable (CKE) pin allows the operation of the
chip to be suspended as long as necessary. When
CKE is high, all synchronous inputs are ignored and
the internal device registers will hold their previous
values. NBL SSRAM latches external address and ini-
tiates a cycle when CKE and ADV are driven low at the
rising edge of the clock.

Output Enable (OE) can be used to disable the output at
any given time. Read operation is initiated when at the
rising edge of the clock, the address presented to the
address inputs are latched in the address register, CKE
is driven low, the write enable input signals WE are
driven high, and ADV driven low. The internal array is
read between the first rising edge and the second ris-
ing edge of the clock and the data is latched in the out-
put register. At the second clock edge the data is driven
out of the SRAM. During read operation OE must be
driven low for the device to drive out the requested data.

FUNCTION DESCRIPTION

White Electronic Designs Corporation · Phoenix AZ · (602) 437-1520

WEDPZ512K72V-XBX

TRUTH TABLES

YNCHRONOUS

RUTH

ABLE

RITE

RUTH

ABLE

BWa

BWb

BWc

BWd

Operation

Read

Write Byte a

Write Byte b

Write Byte c

Write Byte d

Write All Bytes

Write Abort/NOP

CEx

ADV

BWx

CKE

CLK

Address Accessed

Operation

N/A

Deselect

N/A

Continue Deselect

External Address

Begin Burst Read Cycle

Next Address

Continue Burst Read Cycle

External Address

NOP/Dummy Read

Next Address

Dummy Read

External Address

Begin Burst Write Cycle

Next Address

Continue Burst Write Cycle

N/A

NOP/Write Abort

Next Address

Write Abort

Current Address

Ignore Clock

NOTES:
1. X means "Don't Care."
2. The rising edge of clock is symbolized by ( - ).
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins (ZZ and OE).
6. CEx refers to the combination of CS

, CS

and CS

NOTES:
1. X means "Don't Care."
2. All inputs in this table must meet setup and hold time around the rising edge of CLK (- ).
3. Replace BWa with BWe, BWb, with BWf, BWc with BWg and BWd with BWh for operation of IC2.

White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

WEDPZ512K72V-XBX

150

133

100

Description

Symbol

Conditions

MHz

Units

Notes

(Max)

Power Supply

Device Selected; All Inputs

; Cycle

700

650

600

Current: Operating

Time

TCYC MIN; V

= MAX; Output Open

Power Supply

Device Deselected; V

= MAX; All Inputs

VIL or

VIH

Current: Standby

All Inputs Static; CLK Frequency = MAX

120

Output Open, ZZ

- 0.2V

Clock Running

S B

Device Deselected; V

= MAX; All Inputs

200

180

160

Standby Current

+ 0.2 or

- 0.2; f = max ; ZZ

VIL

BSOLUTE

AXIMUM

ATINGS

VIN Voltage or any other pin relative hovss

-0.3V to +4.6V

Voltage on VDD Supply Relative to VSS

-0.3V to +4.6V

Storage Temperature (BGA)

-55°C to +150°C

Maximum Operating Junction Temperature

125°C

LECTRICAL

HARACTERISTICS

(-55°C

+125°C)

*Stress greater than those listed under "Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability.

Description

Symbol

Conditions

Min

Max

Units

Notes

Input High (Logic 1) Voltage

3.3V I/O

2.0

VDD +0.5

2.5V I/O

1.7

VDD +0.5

Input Low (Logic 0) Voltage

3.3V I/O

-0.3

0.8

2.5 I/O

-0.3

0.7

Input Leakage Current

= Max, 0V

VIN

VDD

-4

µA

Output Leakage Current

Output(s) Disabled, V

OUT

= V

to V

DDQ

-2

µA

Output High Voltage

= -4.0mA

2.4

---

= -1mA (2.5v I/O)

2.0

---

Output Low Voltage

= 8.0mA (3.3V I/O)

---

0.4

= 1.0 mA (2.5v I/O)

---

0.4

Supply Voltage

3.135

3.465

I/O Power Suply (3.3V)

DDQ

3.135

3.465

I/O Power Suply (2.5V)

DDQ

2.375

2.9

NOTES:
1. All voltages referenced to V

(GND)

2. ZZ pin has an internal pull-up, and input leakage = ± 20 µA.

DC C

HARACTERISTICS

(-55°C

+ 125°C)

NOTES:
1. I

is specified with no output current and increases with faster cycle times.

increases with faster cycle times and greater output loading.

BGA C

APACITANCE

= + 25°C, f = 1MHz)

NOTES: 1. This parameter is not tested but guaranteed by design.

Description

Symbol

Max

Units

Notes

Control Input Capacitance (LBO, zz)

Control Input Capacitance

Input/Output Capacitance (DQ)

Address Capacitance

Clock Capacitance

CCK

HERMAL

ESISTANCE

Parameter

Symbol

Max

Unit

Thermal Resistance: Die Junction to Ambient

28.1 °C/W

Thermal Resistance: Die Junction to Ball

16.0 °C/W

Thermal Resistance: Die Junction to Case

7.1

°C/W

Note: Refer to Application Note "PBGA Thermal Resistance Corrleation"
for further information regarding WEDC's thermal modeling.

White Electronic Designs Corporation · Phoenix AZ · (602) 437-1520

WEDPZ512K72V-XBX

AC C

HARACTERISTICS

(-55°C - TA - +125°C)

NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low
and CSx is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is
chip selected.
2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low. A Read cycle is defined by WE
High with ADV Low. Both cases must meet setup and hold times.

UTPUT

OAD

(A)

UTPUT

OAD

(B)

(FOR t

LZC

, t

LZOE

, t

HZOE

AND

HZC

)

Dout

Zo=50

RL=50

VL=1.5V

50pF*

Dout

353

1538

5pF*

+3.3V for 3.3V I/O, +2.5V for 2.5V I/O

319

/1667

*Including Scope and Jig
Capacitance

AC T

EST

ONDITIONS

Parameter

Value

Input Pulse Level

0 to 3.6V

Input Rise and Fall Time

1.0V/ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Output Load (A & B)

Symbol

150MHz

133MHz

100MHz

Parameter

Min

Max

Min

Max

Min

Max

Units

Clock Time

C Y C

6.7

7.5

10.0

Clock Access Time

3.8

4.2

5.0

Output enable to Data Valid

3.8

4.2

5.0

Clock High to Output Low-Z

LZC

1.5

Output Hold from Clock High

1.5

Output Enable Low to output Low-Z

LZOE

0.0

Output Enable High to Output High-Z

HZOE

3.0

3.5

Clock High to Output High-Z

HZC

3.0

3.5

Clock High Pulse Width

2.5

3.0

Clock Low Pulse Width

2.5

3.0

Address Setup to Clock High

A S

1.5

CKE Setup to Clock High

C E S

1.5

Data Setup to Clock High

1.5

Write Setup to Clock High

W S

1.5

Address Advance to Clock High

A D V S

1.5

Chip Select Setup to Clock High

C S S

1.5

Address Hold to Clock high

0.5

CKE Hold to Clock High

C E H

0.5

Data Hold to Clock High

0.5

Write Hold to Clock High

W H

0.5

Address Advance to Clock High

A D V H

0.5

Chip Select Hold to Clock High

C S H

0.5

---

0.5

= 1.5V for 3.3V I/O

DDQ

/ 2

for 2.5V I/O

White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

WEDPZ512K72V-XBX

SNOOZE MODE is a low-current, "power-down" mode
in which the device is deselected and current is re-
duced to ISB2Z. The duration of SNOOZE MODE is
dictated by the length of time Z is in a HIGH state. After
the device enters SNOOZE MODE, all inputs except ZZ
become gated inputs and are ignored. ZZ is an asyn-
chronous, active HIGH input that causes the device to
enter SNOOZE MODE.

When ZZ becomes a logic HIGH, ISB2Z is guaranteed
after the setup time t

is met. Any READ or WRITE

operation pending when the device enters SNOOZE
MODE is not guaranteed to complete successfully.
Therefore, SNOOZE MODE must not be initiated until
valid pending operations are completed.

NOOZE

ODE

Description

Conditions

Symbol

Min

Max

Units

Current during SNOOZE MODE

S B 2 Z

ZZ active to input ignored

cycle

ZZ inactive to input sampled

R Z Z

cycle

ZZ active to snooze current

ZZI

cycle

ZZ inactive to exit snooze current

RZZI

FIG. 2

SNOOZE MODE

NOOZE

ODE

IMING

IAGRAM

SUPPLY

CLOCK

ALL INPUTS

(except ZZ)

Output (Q)

ZZI

RZZ

RZZI

HIGH-Z

DESELECT or READ Only

ISB2Z

DON'T CARE

Deselect or Read Only

Normal

Operation Cycle

White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

WEDPZ512K72V-XBX

0.61 (0.024) NOM

1.27

(0.050)

NOM

20.32 (0.800)

NOM

9 8 7 6 5 4 3 2 1

23.1 (0.909)

MAX

17.1 (0.673)

MAX

10.16 (0.400)

NOM

2.03 (0.080)

MAX

BOTTOM VIEW

0.762 (0.030) NOM

1.27 (0.050) NOM

DEVICE GRADE:

M = Military

-55°C to +125°C

I = Industrial

-40°C to +85°C

C = Commercial

0°C to +70°C

PACKAGE:

B = 152 Plastic Ball Grid Array (PBGA)

FREQUENCY (MHz)

100 = 100MHz

133 = 133MHz

150 = 150MHz

3.3 V Voltage

CONFIGURATION, 512K x 72

SSRAM ZBL

PLASTIC

WHITE ELECTRONIC DESIGNS CORP.

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

WED P Z 512K 72 V - XXX B X

ORDERING INFORMATION

PACKAGE DIMENSION:

152 BUMP PBGA

White Electronic Designs Corporation · Phoenix AZ · (602) 437-1520

WEDPZ512K72V-XBX

Document Title

512K x 72 Synchronous SRAM NBL

Revision History

Rev #

History

Release Date

Status

Rev 0

Initial Release

May 2001

Advanced

Rev 1

Changes (Pg. 1)

March 2001

Preliminary

1.1 Change status from Advanced to Preliminary

Rev 2

Changes (Pg. 1, 2)

March 2002

Preliminary

1.1 Block Diagram: Address lines should be A0-18
1.2 Pin Configuration: Add Note *Pin F8 reserved for A19 upgrade to 1Mx72.

Rev 3

Changes (Pg. 1, 5)

November 2002

Preliminary

1.1 BGA Capacitance: Remove references to temperature in individual conditions
1.2 Change C

from 10pF to 8pF

1.3 Change C

from 20pF to 16pF

1.4 Change C

from 7pF to 6pF

1.5 Add Control Input Capacitance (C

) 16pF

Rev 4

Changes (Pg. 5)

May 2003

Preliminary

1.1 Add Thermal Resistance table
1.2 Update current values
1.3 Update package mechanical drawing

Rev 5

Changes (Pg. 1, 5, 14)

June 2003

Preliminary

1.1 Remove reference to Preliminary status
1.2 Add Maximum Operating Junction Temperature of 125°C

Rev 6

Changes (Pg. 1, 13, 14)

November 2003

Preliminary

1.1 Change mechanical drawing to new style

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