White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WEDPZ512K72V-XBX

February 2006
Rev. 7

FEATURES

Fast clock speed: 150, 133, and 100MHz

Fast access times: 3.8ns, 4.2ns, and 5.0ns

Fast OE# access times: 3.8ns, 4.2ns, and 5.0ns

High performance 3-1-1-1 access rate

3.3V ± 5% power supply

I/O supply voltage 3.3V or 2.5V

Common data inputs and data outputs

Byte write enable and global write control

Six chip enables for depth expansion and
address pipeline

Internally self-timed write cycle

Burst control pin (interleaved or linear burst
sequence)

Automatic power-down for portable applications

Commercial, industrial and military temperature
ranges

Packaging:

· 152 PBGA package 17 x 23mm

BENEFITS

30% space savings compared to equivalent
TQFP solution

Reduced part count

24% I/O reduction

Laminate interposer for optimum TCE match

Low Profi le

Reduce layer count for board routing

Suitable for hi-reliability applications

User confi gurable as 1M x 36 or 2M x 18

Upgradable to 1M x 72 (contact factory for availability)

512K x 72 Synchronous Pipeline Burst ZBL SRAM

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The WEDC SyncBurst - SRAM employs high-speed,
low-power CMOS design that is fabricated using an
advanced CMOS process. WEDC's 32Mb SyncBurst
SRAMs integrate two 512K x 36 SSRAMs into a single
BGA package to provide 512K x 72 confi guration. All
synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The ZBL
or Zero Bus Latency Memory utilizes all the bandwidth
in any combination of operating cycles. Address, data
inputs, and all control signals except output enable and
linear burst order are synchronized to input clock. Burst
order control must be tied "High or Low." Asynchronous
inputs include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are
internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip write
pulse generation and provides increased timing fl exibility
for incoming signals.

* Product is subject to change without notice.

0-18

BWa#

BWb#

BWc#

BWd#

CLK

CKE

CS1

CS2

ADV

LBO#

BWa#

BWb#

BWc#

BWd#

CLK

CKE#

CS1#

CS2#

CS2

ADV

LBO#

DQPA

DQA

0-7

DQPB

DQB

0-7

DQPC

DQC

0-7

DQPD

DQD

0-7

DQPA

DQA

0-7

DQPB

DQB

0-7

DQPC

DQC

0-7

DQPD

DQD

0-7

512K x 36 SSRAM

BWe#

BWf#

BWg#

BWh#

WE1#

OE1#

CLK1#

CKE1#

CS1

CS2

ADV1

BWa#

BWb#

BWc#

BWd#

WEO#

OEO#

CLK

CKE

CS1#

CS2#

CS2

ADV

LBO#

512K x 36 SSRAM

DQPA

DQA

0-7

DQPB

DQB

0-7

DQPC

DQC

0-7

DQPH

DQD

0-7

DQPE

DQE

0-7

DQPF

DQF

0-7

DQPG

DQG

0-7

DQPH

DQH

0-7

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WEDPZ512K72V-XBX

February 2006
Rev. 7

PIN CONFIGURATION

(TOP VIEW)

NOTE: DNU means Do Not Use and are reserved for future use.
* Pin F

reserved for A

upgrade to 1M x 72

ADV

DQb

dnu

DQa

CKE

DQb

DQa

CLK

CS2

DQc

DQpc

DQpb

DQb

DQd

DQa

BWa#

BWb#

DQC

DQD

DQA

DQPA

BWc#

BWd#

DQC

CCQ

DQD

DQPD

CS1

CS2

DQC

CCQ

DQD

DNU*

DQC

DQD

DQC

DQD

DQF

DQD

DQF

FQF

DQD

DQF

DQE

ADV

DQF

CCQ

DQE

CKE

DQPF

CCQ

DQE

LBO#

CLK

CS2

DQF

DQE

BWe#

BWf#

DQF

DQG

DQH

DQE

DQPE

BWg#

BWh#

DQG

DQH

DQPH

CS1

CS2

DQG

DQPG

DQG

DQH

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WEDPZ512K72V-XBX

February 2006
Rev. 7

BURST SEQUENCE TABLE

Write operation occurs when WE# is driven low at the
rising edge of the clock. BW#[h:a] can be used for byte
write operation. The pipe-lined ZBL SSRAM uses a late-
late write cycle to utilize 100% of the bandwidth. At the fi rst
rising edge of the clock, WE# and address are registered,
and the data associated with that address is required two
cycles later.

Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of the
burst sequence is provided by the external address. The
burst address counter wraps around to its initial state upon
completion. The burst sequence is determined by the state
of the LBO# pin. When this pin is low, linear burst sequence
is selected. And when this pin is high, Interleaved burst
sequence is selected.

During normal operation, ZZ must be driven low. When ZZ
is driven high, the SRAM will enter a Power Sleep Mode
after two cycles. At this time, internal state of the SRAM
is preserved. When ZZ returns to low, the SRAM operates
after two cycles of wake up time.

(Interleaved Burst, LBO# = High)

LBO# Pin

High

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed.

(Linear Burst, LBO# = Low)

LBO# Pin

High

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

FUNCTION DESCRIPTION

The WEDPZ512K72V-XBX is an ZBL SSRAM designed
to sustain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or vice
versa. All inputs (with the exception of OE#, LBO# and ZZ)
are synchronized to rising clock edges.

All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be internally
generated by the burst advance pin (ADV). ADV should
be driven to Low once the device has been deselected in
order to load a new address for next operation.

Clock Enable (CKE#) pin allows the operation of the chip to
be suspended as long as necessary. When CKE# is high,
all synchronous inputs are ignored and the internal device
registers will hold their previous values. NBL SSRAM
latches external address and initiates a cycle when CKE
and ADV are driven low at the rising edge of the clock.

Output Enable (OE#) can be used to disable the output at
any given time. Read operation is initiated when at the rising
edge of the clock, the address presented to the address
inputs are latched in the address register, CKE# is driven
low, the write enable input signals WE# are driven high,
and ADV driven low. The internal array is read between
the fi rst rising edge and the second rising edge of the clock
and the data is latched in the output register. At the second
clock edge the data is driven out of the SRAM. During read
operation OE# must be driven low for the device to drive
out the requested data.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WEDPZ512K72V-XBX

February 2006
Rev. 7

TRUTH TABLES

WRITE TRUTH TABLE

WE#

BWa#

BWb#

BWc#

BWd#

Operation

Read

Write Byte a

Write Byte b

Write Byte c

Write Byte d

Write All Bytes

Write Abort/NOP

NOTES:
1. X

means

"Don't

Care."

All inputs in this table must meet setup and hold time around the rising edge of CLK ().

Replace BWa# with BWe#, BWb#, with BWf#, BWc# with BWg# and BWd# with BWh# for operation of IC2.

SYNCHRONOUS TRUTH TABLE

CEx#

ADV

WE#

BWx#

OE#

CKE#

CLK

Address Accessed

Operation

N/A

Deselect

N/A

Continue Deselect

External Address

Begin Burst Read Cycle

Next Address

Continue Burst Read Cycle

External Address

NOP/Dummy Read

Next Address

Dummy Read

External Address

Begin Burst Write Cycle

Next Address

Continue Burst Write Cycle

N/A

NOP/Write Abort

Next Address

Write Abort

Current Address

Ignore Clock

NOTES:
1. X

means

"Don't

Care."

The rising edge of clock is symbolized by ().

A continue deselect cycle can only be entered if a deselect cycle is executed fi rst.

WRITE# = L means Write operation in WRITE TRUTH TABLE.

WRITE# = H means Read operation in WRITE TRUTH TABLE.

Operation fi nally depends on status of asynchronous input pins (ZZ and OE).

CEx# refers to the combination of CS1#, CS2 and CS2#.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WEDPZ512K72V-XBX

February 2006
Rev. 7

DC CHARACTERISTICS

-55°C T

+ 125°C

Description

Symbol

Conditions

150

MHz

(Max)

133

MHz

(Max)

100

MHz

(Max)

Units

Notes

Power Supply Current:
Operating

Device Selected; All Inputs V

or V

; Cycle Time TCYC MIN;

= MAX; Output Open

700

650

600 mA

Power Supply Current:
Standby

Device Deselected; V

= MAX; All Inputs V

or V

All Inputs Static; CLK Frequency = MAX
Output Open, ZZ V

- 0.2V

120

Clock Running Standby
Current

Device Deselected; V

= MAX; All Inputs

+ 0.2 or V

- 0.2; f = max ; ZZ V

200

180

160

NOTES:
1. I

is specifi ed with no output current and increases with faster cycle times.

increases with faster cycle times and greater output loading.

ABSOLUTE MAXIMUM RATINGS*

Electrical Characteristics

-55°C T

+ 125°C

Description

Symbol

Conditions

Min

Max

Units

Notes

Input High (Logic 1) Voltage

3.3V I/O

2.0

+0.5

2.5V I/O

1.7

+0.5

Input Low (Logic 0) Voltage

3.3V I/O

-0.3

0.7

2.5 I/O

-0.3

0.7

Input Leakage Current

= Max, 0V V

-4

µA

Output Leakage Current

Output(s) Disabled, V

OUT

= V

to V

CCQ

-2

µA

Output High Voltage

= -4.0mA

2.4

= -1mA (2.5v I/O)

2.0

Output Low Voltage

= 8.0mA (3.3V I/O)

0.4

= 1.0 mA (2.5v I/O)

0.4

Supply Voltage

3.135

3.465

I/O Power Supply (3.3V)

CCQ

3.135

3.465

I/O Power Supply (2.5V)

CCQ

2.375

2.9

NOTES:
1.

All voltages referenced to V

(GND)

ZZ pin has an internal pull-up, and input leakage = ± 20 µA.

BGA CAPACITANCE

= + 25°C, f = 1MHz

Description

Symbol

Max

Units

Notes

Control Input Capacitance (LBO#, zz)

Control Input Capacitance

Input/Output Capacitance (DQ)

Address Capacitance

Clock Capacitance

CCK

NOTES: 1. This parameter is not tested but guaranteed by design.

THERMAL RESISTANCE

Parameter

Symbol

Max

Unit

Thermal Resistance: Die Junction to Ambient

28.1

°C/W

Thermal Resistance: Die Junction to Ball

16.0

°C/W

Thermal Resistance: Die Junction to Case

7.1

°C/W

Note: Refer to Application Note "PBGA Thermal Resistance Corrleation" for further

information regarding WEDC's thermal modeling.

Voltage or any other pin relative hovss

-0.3V to +4.6V

Voltage on V

Supply Relative to V

-0.3V to +4.6V

Storage Temperature (BGA)

-55°C to +150°C

Maximum Operating Junction Temperature

125°C

* Stress greater than those listed under "Absolute Maximum Ratings: may cause

permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specifi cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WEDPZ512K72V-XBX

February 2006
Rev. 7

OUTPUT LOAD (A)

OUTPUT LOAD (B)

FOR tlzc, tlzoe, thzoe, and thzc

Dout

Zo=50

RL=50

VL=1.5V

50pF*

Dout

353/1538

5pF*

+3.3V for 3.3V I/O, +2.5V for 2.5V I/O

319/1667

*Including Scope and Jig Capacitance

AC TEST CONDITIONS

Parameter

Value

Input Pulse Level

0 to 3.6V

Input Rise and Fall Time

1.0V/ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Output Load (A & B)

AC CHARACTERISTICS

-55°C T

+ 125°C

Parameter

Symbol

150MHz

133MHz

100MHz

Units

Min

Max

Min

Max

Min

Max

Clock Time

CYC

6.7

7.5

10.0

Clock Access Time

3.8

4.2

5.0

Output enable to Data Valid

3.8

4.2

5.0 ns

Clock High to Output Low-Z

LZC

1.5

Output Hold from Clock High

1.5

Output Enable Low to output Low-Z

LZOE

0.0

Output Enable High to Output High-Z

HZOE

3.0

3.5

3.5 ns

Clock High to Output High-Z

HZC

3.0

3.5

3.5 ns

Clock High Pulse Width

2.5

3.0

Clock Low Pulse Width

2.5

3.0

-- ns

Address Setup to Clock High

1.5

-- ns

CKE Setup to Clock High

CES

1.5

Data Setup to Clock High

1.5

Write Setup to Clock High

1.5

Address Advance to Clock High

ADVS

1.5 1.5 1.5 ns

Chip Select Setup to Clock High

CSS

1.5 1.5 1.5

Address Hold to Clock high

0.5

CKE Hold to Clock High

CEH

0.5

Data Hold to Clock High

0.5

Write Hold to Clock High

0.5

Address Advance to Clock High

ADVH

0.5

Chip Select Hold to Clock High

CSH

0.5

NOTES:
1.

All Address inputs must meet the specifi ed setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CSx# is
sampled valid. All other synchronous inputs must meet the specifi ed setup and hold times whenever this device is chip selected.

Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.

A write cycle is defi ned by WE# low having been registered into the device at ADV Low. A Read cycle is defi ned by WE# High with ADV Low.
Both cases must meet setup and hold times.

= 1.5V for 3.3V I/O

CCQ

/ 2

for 2.5V I/O

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WEDPZ512K72V-XBX

February 2006
Rev. 7

SNOOZE MODE is a low-current, "power-down" mode in
which the device is deselected and current is reduced to
ISB2Z. The duration of SNOOZE MODE is dictated by the
length of time Z is in a HIGH state. After the device enters
SNOOZE MODE, all inputs except ZZ become gated inputs
and are ignored. ZZ is an asynchronous, active HIGH input
that causes the device to enter SNOOZE MODE.

When ZZ becomes a logic HIGH, ISB2Z is guaranteed after
the setup time t

is met. Any READ or WRITE operation

pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore, SNOOZE
MODE must not be initiated until valid pending operations
are completed.

Snooze Mode

Description

Conditions

Symbol

Min

Max

Units

Current during SNOOZE MODE

ZZ V

SB2Z

ZZ active to input ignored

cycle

ZZ inactive to input sampled

RZZ

cycle

ZZ active to snooze current

ZZI

cycle

ZZ inactive to exit snooze current

RZZI

FIGURE 2 SNOOZE MODE TIMING DIAGRAM

SNOOZE MODE

SUPPLY

CLOCK

ALL INPUTS

(except ZZ)

Output (Q)

ZZI

RZZ

RZZI

HIGH-Z

DESELECT or READ Only

ISB2Z

DON'T CARE

Deselect or Read Only

Normal

Operation Cycle

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WEDPZ512K72V-XBX

February 2006
Rev. 7

0.61 (0.024) NOM

1.27

(0.050)

NOM

20.32 (0.800)

NOM

23.1 (0.909)

MAX

17.1 (0.673)

MAX

10.16 (0.400)

NOM

2.03 (0.080)

MAX

0.762 (0.030) NOM

1.27 (0.050) NOM

9 8 7 6 5 4 3 2 1

DEVICE

GRADE:

M = Military

-55°C to +125°C

Industrial

-40°C

+85°C

Commercial

0°C

+70°C

PACKAGE:

B = 152 Plastic Ball Grid Array (PBGA)

FREQUENCY

(MHz)

100

100MHz

133

133MHz

150

150MHz

3.3 V Voltage

CONFIGURATION, 512K x 72

SSRAM

ZBL

PLASTIC

WHITE ELECTRONIC DESIGNS CORP.

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

WED P Z 512K 72 V - XXX B X

ORDERING INFORMATION

PACKAGE DIMENSION:  152 BUMP PBGA

Bottom View

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WEDPZ512K72V-XBX

February 2006
Rev. 7

Document Title

512K x 72 Synchronous Pipeline Burst ZBL SRAM

Revision History

Rev #

History

Release Date

Status

Rev 0

Initial Release

May 2001

Advanced

Rev 1

Changes (Pg. 1)
1.1 Change status from Advanced to Preliminary

March 2001

Preliminary

Rev 2

Changes (Pg. 1, 2)
1.1 Block Diagram: Address lines should be A0-18
1.2

Pin Confi guration: Add Note *Pin F8 reserved for A19
upgrade to 1Mx72.

March 2002

Preliminary

Rev 3

Changes (Pg. 1, 5)
1.1

BGA Capacitance: Remove references to temperature in
individual conditions

1.2 Change C

from 10pF to 8pF

1.3 Change C

from 20pF to 16pF

1.4 Change C

from 7pF to 6pF

1.5 Add Control Input Capacitance (C

) 16pF

November 2002

Preliminary

Rev 4

Changes (Pg. 5)
1.1 Add Thermal Resistance table
1.2 Update current values
1.3 Update package mechanical drawing

May 2003

Preliminary

Rev 5

Changes (Pg. 1, 5, 14)
1.1 Remove reference to Preliminary status
1.2 Add Maximum Operating Junction Temperature of 125°C

June 2003

Preliminary

Rev 6

Changes (Pg. 1, 13, 14)
1.1 Change mechanical drawing to new style

November 2003

Preliminary

Rev 7

Changes (Pg. 1, 5, 14)
1.1 Change VIL 3.3V ti 0.7V maximum
1.2 Change status to Final

February 2006

Final

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