WMS256K16-XXX
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2004
Rev. 6
256Kx16 MONOLITHIC SRAM, SMD 5962-96902
FEATURES
Access Times 17, 20, 25, 35ns
MIL-STD-883 Compliant Devices Available
Packaging
44 pin Ceramic SOJ (Package 102)
44 lead Ceramic Flatpack (Package 225)
44 lead Formed Ceramic Flatpack
Organized as 256Kx16
Data
Byte
Control:
Lower Byte (LB#) = I/O
1-8
Upper Byte (UB#) = I/O
9-16
2V Minimum Data Retention for battery back up
operation (WMS256K16L-XXX Low Power Version
Only)
Commercial,
Industrial
and
Military
Temperature
Range
5V
Power
Supply
Low
Power
CMOS
TTL Compatible Inputs and Outputs
PIN CONFIGURATION FOR WMS256K16-XXX
A
0-17
Address Inputs
LB#
Lower-Byte Control (I/O
1-8
)
UB#
Upper-Byte Control (I/O
9-16
)
I/O
1-16
Data Input/Output
CS#
Chip Select
OE#
Output Enable
WE#
Write Enable
V
CC
+5.0V Power
GND
Ground
NC
No Connection
PIN DESCRIPTION
44 CSOJ
44 FlatpacK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
A1
A2
A3
A4
CS#
I/O1
I/O2
I/O3
I/O4
V
CC
GND
I/O5
I/O6
I/O7
I/O8
WE#
A5
A6
A7
A8
A9
A17
A16
A15
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
TOP VIEW
WMS256K16-XXX
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2004
Rev. 6
TRUTH TABLE
CS#
WE#
OE#
LB#
UB#
Mode
Data I/O
Power
I/O
1-8
I/O
9-16
H
X
X
X
X
Not Select
High Z
High Z
Standby
L
H
H
X
X
Output Disable
High Z
High Z
Active
L
X
X
H
H
L
H
L
L
H
Read
Data Out
High Z
Active
H
L
High Z
Data Out
L
L
Data Out
Data Out
L
L
X
L
H
Write
Data In
High Z
Active
H
L
High Z
Data In
L
L
Data In
Data In
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Max
Unit
Operating Temperature
T
A
-55
+125
C
Storage Temperature
T
STG
-65
+150
C
Signal Voltage Relative to GND
VG
-0.5
V
CC
+0.5
V
Junction Temperature
TJ
150
C
Supply Voltage
V
CC
-0.5
7.0
V
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
4.5
5.5
V
Input High Voltage
V
IH
2.2
V
CC
+ 0.3
V
Input Low Voltage
V
IL
-0.3
+0.8
V
Operating Temp. (Mil.)
T
A
-55
+125
C
CAPACITANCE
T
A
= +25C
Parameter
Symbol
Condition
Max
Unit
Input capacitance
C
IN
V
IN
= 0V, f = 1.0MHz
20
pF
Output capacitance
C
OUT
V
OUT
= 0V, f = 1.0MHz
20
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55C T
A
+125C
Parameter
Symbol
Conditions
Min
Max
Units
Input Leakage Current
I
LI
V
CC
= 5.5, V
IN
= GND to V
CC
10
A
Output Leakage Current
I
LO
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
10
A
Operating Supply Current
I
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
275
mA
Standby Current
I
SB
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
17
mA
Output Low Voltage
V
OL
I
OL
= 6mA, V
CC
= 4.5
0.4
V
Output High Voltage
V
OH
I
OH
= -4.0mA, V
CC
= 4.5
2.4
V
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
LOW POWER DATA RETENTION CHARACTERISTICS (WMS256K16L-XXX ONLY)
-55C T
A
+125C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Data Retention Supply Voltage
VDR
CS# V
CC
-0.2V
2.0
5.5
V
Data Retention Current
I
CCDR
1
V
CC
= 3V
1.0
8.0
mA
WMS256K16-XXX
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2004
Rev. 6
I
Current Source
D.U.T.
C = 50 pf
eff
I
OL
V
1.5V
(Bipolar Supply)
Z
Current Source
OH
Notes:
Vz is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75 .
Vz is typically the midpoint of V
OH
and V
OL
.
I
OL
& IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55C T
A
+125C
Parameter
Write Cycle
Symbol
-17
-20
-25
-35
Units
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
17
20
25
35
ns
Chip Select to End of Write
t
CW
14
17
20
25
ns
Address Valid to End of Write
t
AW
14
17
20
25
ns
Data Valid to End of Write
t
DW
10
12
15
20
ns
Write Pulse Width
t
WP
14
17
20
25
ns
Address Setup Time
t
AS
0
0
0
0
ns
Address Hold Time
t
AH
2
2
2
2
ns
Output Active from End of Write
t
OW
1
0
0
0
0
ns
Write Enable to Output in High Z
t
WHZ
1
9
10
10
15
ns
Data Hold Time
t
DH
0
0
0
0
ns
LB#, UB# Valid to End of Write
t
BW
14
17
20
25
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55C T
A
+125C
Parameter
Read Cycle
Symbol
-17
-20
-25
-35
Units
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
17
20
25
35
ns
Address Access Time
t
AA
17
20
25
35
ns
Output Hold from Address Change
t
OH
0
0
0
0
ns
Chip Select Access Time
t
ACS
17
20
25
35
ns
Output Enable to Output Valid
t
OE
10
12
15
20
ns
Chip Select to Output in Low Z
t
CLZ
1
2
5
5
5
ns
Output Enable to Output in Low Z
t
OLZ
1
0
0
0
0
ns
Chip Disable to Output in High Z
t
CHZ
1
9
10
12
15
ns
Output Disable to Output in High Z
t
OHZ
1
9
10
12
15
ns
LB#, UB# Access Time
t
BA
10
12
14
17
ns
LB#, UB# Enable to Low Z Output
t
BLZ
1
0
0
0
0
ns
LB#, UB# Disable to High Z Output
t
BHZ
1
9
10
12
15
ns
1. This parameter is guaranteed by design but not tested.
WMS256K16-XXX
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2004
Rev. 6
TIMING WAVEFORM - READ CYCLE
WRITE CYCLE - CS# CONTROLLED
WRITE CYCLE - WE# CONTROLLED
ADDRESS
DATA I/O
READ CYCLE 1 (CS# = OE# = V
IL
, UB# or LB# = V
IL
, WE# = V
IH
)
t
AA
t
OH
t
RC
DATA VALID
PREVIOUS DATA VALID
ADDRESS
DATA I/O
READ CYCLE 2 (WE# = V
IH
)
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
OHZ
t
RC
DATA VALID
HIGH IMPEDANCE
CS#
OE#
t
CHZ
LB#, UB#
t
BHZ
t
BA
t
BLZ
ADDRESS
DATA I/O
WRITE CYCLE 1, WE# CONTROLLED
t
AW
t
CW
t
AH
t
WP
t
DW
t
WHZ
t
AS
t
OW
t
DH
t
WC
DATA VALID
CS#
WE#
t
BW
LB#, UB#
ADDRESS
DATA I/O
WRITE CYCLE 2, CS# CONTROLLED
t
AW
t
AS
t
CW
t
AH
t
WP
t
DH
t
DW
t
WC
CS#
WE#
DATA VALID
t
BW
LB#, UB#
WRITE CYCLE - LB#, UB# CONTROLLED
ADDRESS
DATA I/O
WRITE CYCLE 3, LB#, UB# CONTROLLED
t
AW
t
AS
t
CW
t
AH
t
WP
t
DH
t
DW
t
WC
CS#
WE#
DATA VALID
t
BW
LB#, UB#
WMS256K16-XXX
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2004
Rev. 6
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 102: 44 LEAD, CERAMIC SOJ
1.27 (0.050) TYP
28.70 (1.13) 0.25 (0.010)
26.7 (1.050) TYP
11.3 (0.446)
0.2 (0.009)
3.96 (0.156) MAX
0.2 (0.008)
0.05 (0.002)
9.55 (0.376) 0.25 (0.010)
1.27 (0.050) 0.25 (0.010)
0.89 (0.035)
Radius TYP
PACKAGE 225: 44 LEAD, CERAMIC FLAT PACK
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
28.45 (1.120)
0.26 (0.010)
12.95 (0.510)
0.13 (0.005)
2.60 (0.102)
MAX
0.14 (0.006)
0.05 (0.002)
1.27 (0.050) TYP
26.67 (1.050) TYP
10.16 (0.400)
0.51 (0.020)
0.43 (0.017)
0.05 (0.002)
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