1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WMS512K8-XXX
October 2004
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
512Kx8 MONOLITHIC SRAM, SMD 5962-95613
32 pin, Rectangular Ceramic Leadless Chip
Carrier (Package 601)
Commercial, Industrial and Military
Temperature Range
5V Power Supply
Low Power CMOS
Low Power Data Retention for Battery Back-up
Operation
TTL Compatible Inputs and Outputs
*This product is subject to change without notice.
FEATURES
Access Times 15, 17, 20, 25, 35, 45, 55ns
MIL-STD-883 Compliant Devices Available
Revolutionary, Center Power/Ground Pinout JEDEC
Approved
36 lead Ceramic SOJ (Package 100)
36 lead Ceramic Flat Pack (Package 226)
Evolutionary, Corner Power/Ground Pinout JEDEC
Approved
32 pin Ceramic DIP (Package 300)
32 lead Ceramic SOJ (Package 101)
32 lead Ceramic ThinpackTM Flat Pack
(Package 321)
TOP VIEW
PIN DESCRIPTION
EVOLUTIONARY PINOUT
REVOLUTIONARY PINOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A0
A1
A2
A3
A4
CS#
I/O0
I/O1
V
CC
V
SS
I/O2
I/O3
WE#
A5
A6
A7
A8
A9
NC
A18
A17
A16
A15
OE#
I/O7
I/O6
V
SS
V
CC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
4 3 2 1 32 31 30
14 15 16 17 18 19 20
A7
A6
A5
A4
A3
A2
A1
A0
I/O
0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
A12
A14
A16
A18
V
CC
A15
A17
36 FLAT PACK
36 CSOJ
TOP VIEW
TOP VIEW
32 DIP
32 CSOJ (DE)
32 FLAT PACK (FF)
32 CLCC
A0-18 Address
Inputs
I/O 0-7
Data Input/Output
CS# Chip
Select
OE# Output
Enable
WE# Write
Enable
V
CC
+5.0V
Power
GND Ground
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WMS512K8-XXX
October 2004
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
Parameter
Symbol
Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
CC
= 5.5, V
IN
= GND to V
CC
10
A
Output Leakage Current
I
LO
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND TO V
CC
10 A
Operating Supply Current*
I
CC
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5,
160
mA
Standby Current
I
SS
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
0.45
mA
Output Low Voltage
V
OL
I
OL
= 6mA for 17 - 35ns,
I
OL
= 2.1mA for 45 - 55ns, V
CC
= 4.5
0.4
V
Output High Voltage
V
OH
I
OH
= -4.0mA for 17 - 35ns,
I
OH
= 1.0mA for 45 - 55ns, V
CC
= 4.5
2.4
V
DC Characteristics - CMOS Compatible
(V
CC
= 5.0V, GND
= 0V, -55C
T
A
125C)
Recommended Operating Conditions
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
4.5
5.5
V
Input High Voltage
V
IH
2.2
V
CC
+ 0.3
V
Input Low Voltage
V
IL
-0.3
+0.8
V
Operating Temp. (Mil)
T
A
-55
+125
C
Capacitance
(T
A
= +25C)
Parameter
Symbol
Conditions Package
Speed
(ns)
Max
Unit
Input capacitance
C
IN
V
IN
= 0 V, f = 1.0 MHz
32 pin CSOJ, DIP, Flat Pack Evolutionary
15 to 55
20
pF
32 pin CLCC
15 to 55
15
pF
36 pin CSOJ & Flat Pack Revolutionary
15 to 35
12
pF
45 to 55
20
pF
Output
capacitance
C
OUT
V
OUT
= 0 V, f = 1.0 MHz
32 pin CSOJ, DIP, Flat Pack Revolutionary
15 to 55
20
pF
36 pin CSOJ & Flat Pack Revolutionary
15 to 35
12
pF
45 to 55
20
pF
This parameter is guaranteed by design but not tested.
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Operating Temperature
T
A
-55
+125
C
Storage Temperature Range
T
STG
-65
+150
C
Signal Voltage Range to GND
V
G
-0.5
V
CC
-0.5
V
Junction Temperature
T
J
150
C
Supply Voltage Range (V
CC
)
V
CC
-0.5
7.0
V
Truth Table
CS#
OE#
WE#
MODE
DATA I/O
POWER
H
X
X
Standby
High Z
Standby
L
L
H
Read
Data Out
Active
L
X
L
Write
Data In
Active
L
H
H
Out Disable
High Z
Acvive
Parameter
Symbol
Conditions
Min
Max
Unit
Data Retention Supply Voltage
V
DR
CS#
3
V
CC
-0.2V
2.0
5.5
V
Low Power Data Retention
I
CCDR1
V
CC
= 3V
7
mA
Low Power Data Retention
I
CCDR2
V
CC
= 2V
2
mA
Data retention characteristics for low power "l" version
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WMS512K8-XXX
October 2004
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
AC Characteristics
(V
CC
= 5.0V, GND = 0V, -55C
T
A
< 125C)
Parameter
Symbol
-15
-17
-20
-25
-35
-45
-55
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
15
17
20
25
35
45
55
ns
Address Access Time
tAA
15
17
20
25
35
45
55
ns
Output Hold from Address Change
tOH
0
0
0
0
0
0
0
ns
Chip Select Access Time
tACS
15
17
20
25
35
45
55
ns
Output Enable to Output Valid
tOE
8
9
10
12
25
25
25
ns
Chip Select to Output in Low Z
tCLZ1
2
2
2
2
4
4
4
ns
Output Enable to Output in Low Z
tOLZ1
0
0
0
0
0
0
0
ns
Chip Disable to Output in High Z
tCHZ1
8
9
10
12
15
20
20
ns
Output Disable to Output in High Z
tOHZ1
8
9
10
12
15
20
20
ns
AC Characteristics
(V
CC
= 5.0V, GND = 0V, -55C
T
A
125C)
Parameter
Symbol
-15
-17
-20
-25
-35
-45
-55
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
15
17
20
25
35
45
55
ns
Chip Select to End of Write
tCW
13
14
14
15
25
35
50
ns
Address Valid to End of Write
tAW
13
14
14
15
25
35
50
ns
Data Valid to End of Write
tDW
8
9
10
10
20
25
25
ns
Write Pulse Width
tWP
13
14
14
15
25
35
40
ns
Address Setup Time
tAS
2
2
2
2
2
2
2
ns
Address Hold Time
tAH
0
0
0
0
0
5
5
ns
Output Active from End of Write
tOW1
2
2
3
4
4
5
5
ns
Write Enable to Output in High Z
tWHZ1
8
9
9
10
15
20
25
ns
Data Hold Time
tDH
0
0
0
0
0
0
0
ns
1. This parameter is guaranteed by design but not tested.
AC TEST CIRCUIT
AC TEST CONDITIONS
Current Source
Current Source
I
OL
I
OH
C
eff
= 50 pF
D.U.T.
V
Z
1.5V
(Bipolar Supply)
Parameter
Typ
Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75
.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WMS512K8-XXX
October 2004
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
TIMING WAVEFORM - READ CYCLE
WRITE CYCLE - WE# CONTROLLED
WRITE CYCLE - CS# CONTROLLED
ADDRESS
DATA I/O
READ CYCLE 1 (CS# = OE# = V
IL
, WE# = V
IH
)
t
AA
t
OH
t
RC
DATA VALID
PREVIOUS DATA VALID
ADDRESS
DATA I/O
CS#
OE#
t
RC
t
AA
t
ACS
t
CLZ
t
CHZ
t
OE
t
OLZ
t
OHZ
HIGH IMPEDANCE
DATA VALID
READ CYCLE 2 (WE# = V
IH
)
ADDRESS
DATA I/O
WRITE CYCLE 1, WE# CONTROLLED
t
AW
t
CW
t
AH
t
WP
t
DW
t
WHZ
t
AS
t
OW
t
DH
t
WC
DATA VALID
CS#
WE#
ADDRESS
DATA I/O
WRITE CYCLE 2, CS# CONTROLLED
t
AW
t
AS
t
CW
t
AH
t
WP
t
DH
t
DW
t
WC
CS#
WE#
DATA VALID
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WMS512K8-XXX
October 2004
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
PACKAGE 100: 36 LEAD, CERAMIC SOJ
PACKAGE 101: 32 LEAD, CERAMIC SOJ
23.37 (0.920)
0.25 (0.010)
11.23 (0.442)
0.30 (0.012)
0.2 (0.008)
0.05 (0.002)
1.27 (0.050) TYP
21.6 (0.850) TYP
9.55 (0.376)
0.25 (0.010)
1.27 (0.050)
0.25 (0.010)
4.7 (0.184) MAX
0.89 (0.035)
Radius TYP
21.1 (0.830)
0.25 (0.010)
1.27 (0.050) TYP
19.1 (0.750) TYP
0.2 (0.008)
0.05 (0.002)
9.55 (0.376)
0.25 (0.010)
1.27 (0.050)
0.25 (0.010)
3.96 (0.156) MAX
0.89 (0.035)
Radius TYP
11.23 (0.442)
0.30 (0.012)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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