WS512K32-XXX
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2005
Rev. 4
512Kx32 SRAM MODULE, SMD 5962-94611
FEATURES
Access Times of 70, 85, 100, 120ns
Packaging
68 lead, Hermetic CQFP (G2T)
1
, 22.4mm (0.880
inch) square. 4.57mm (0.180 inch) high (Package
509)
Organized as 512Kx32, User Confi gurable as
1Mx16 or 2Mx8
Commercial, Industrial and Military Temperature
Ranges
TTL Compatible Inputs and Outputs
5V
Power
Supply
Low
Power
CMOS
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight
WS512K32-XG2TX
1
- 8 grams typical
Note 1: Package Not Recommended for New Designs.
This product is subject to change without notice.
FIGURE 1 PIN CONFIGURATION FOR WS512K32-XG2TX
1
TOP VIEW
PIN DESCRIPTION
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS#
1
OE#
CS#
2
A
17
WE#
2
WE#
3
WE#
4
A
18
NC
NC
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS#
3
GND
CS#
4
WE#
1
A
6
A
7
A
8
A
9
A
10
V
CC
BLOCK DIAGRAM
512K x 8
8
I / O
0 - 7
W E #
1
CS#
1
512K x 8
8
I / O
8 - 1 5
W E #
2
CS#
2
512K x 8
8
I / O
1 6 - 2 3
W E #
3
CS#
3
512K x 8
8
I / O
2 4 - 3 1
W E #
4
CS#
4
A
0 - 1 8
O E #
I/O0-31
Data Inputs/Outputs
A0-18
Address Inputs
WE#1-4 Write Enables
CS#1-4
Chip Selects
OE#
Output Enable
V
CC
Power Supply
GND Ground
NC
Not Connected
Note 1: Package Not Recommended for New Designs.
WS512K32-XXX
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2005
Rev. 4
Parameter
Symbol
Min
Max
Unit
Operating Temperature
T
A
-55 +125
C
Storage Temperature
T
STG
-65
+150
C
Signal Voltage Relative to GND
V
G
-0.5
V
CC
+0.5
V
Junction Temperature
T
J
150
C
Supply Voltage
V
CC
-0.5
7.0
V
TRUTH TABLE
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
4.5
5.5
V
Input High Voltage
V
IH
2.2
V
CC
+ 0.3
V
Input Low Voltage
V
IL
-0.5
+0.8
V
Operating Temp (Mil)
T
A
-55
+125
C
CAPACITANCE
T
A
= +25C
Parameter
Symbol Conditions Max Unit
OE# capacitance
C
OE
V
IN
= 0 V, f = 1.0 MHz
50
pF
WE#
1-4
capacitance
C
WE
V
IN
= 0 V, f = 1.0 MHz
15
pF
CQFP G2T
CS#
1-4
capacitance
C
CS
V
IN
= 0 V, f = 1.0 MHz
20
pF
Data I/O capacitance
C
I/O
V
I/O
= 0 V, f = 1.0 MHz
20
pF
Address input capacitance
C
AD
V
IN
= 0 V, f = 1.0 MHz
50
pF
This parameter is guaranteed by design but not tested.
Parameter
Symbol
Conditions
Min
Max
Units
Input Leakage Current
I
LI
V
CC
= 5.5, V
IN
= GND to V
CC
10
A
Output Leakage Current
I
LO
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
10
A
Operating Supply Current x 32 Mode
I
CC
x 32
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
200
mA
Standby Current
I
SB
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
4.0
mA
Output Low Voltage
V
OL
I
OL
= 2.1mA, V
CC
= 4.5
0.4
V
Output High Voltage
V
OH
I
OH
= -1.0mA, V
CC
= 4.5
2.4
V
DC CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55C to +125C)
DATA RETENTION CHARACTERISTICS
(T
A
= -55C to +125C)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Data Retention Supply Voltage
V
DR
CS#
V
CC
-0.2V
2.0
5.5
V
Data Retention Current
I
CCDR1
V
CC
= 3V
0.4
1.6
mA
CS#
OE#
WE#
Mode
Data I/O
Power
H
X
X
Standby
High Z
Standby
L
L
H
Read
Data Out
Active
L
H
H
Out Disable
High Z
Active
L
X
L
Write
Data In
Active
LOW CAPACITANCE CQFP
T
A
= +25C
Parameter
Symbol
Conditions Max Unit
OE# capacitance
C
OE
V
IN
= 0 V, f = 1.0 MHz
32
pF
CQFP G4 capacitance
C
WE
V
IN
= 0 V, f = 1.0 MHz
32
pF
CS#1-4 capacitance
C
CS
V
IN
= 0 V, f = 1.0 MHz
15
pF
Data I/O capacitance
C
I/O
V
I/O
= 0 V, f = 1.0 MHz
15
pF
Address input capacitance
C
AD
V
IN
= 0 V, f = 1.0 MHz 32
pF
This parameter is guaranteed by design but not tested.
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
WS512K32-XXX
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2005
Rev. 4
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75
.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Current Source
V
Z
1.5V
(Bipolar Supply)
D.U.T.
C
eff
+50pf
I
OL
I
OH
Current Source
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
AC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, T
A
= -55C to +125C
Parameter
Symbol
-15*
-17
-20
-25
Units
Write Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
70
85
100
120
ns
Chip Select to End of Write
t
CW
60
75
80
100
ns
Address Valid to End of Write
t
AW
60
75
80
100
ns
Data Valid to End of Write
t
DW
30
30
40
40
ns
Write Pulse Width
t
WP
50
50
60
60
ns
Address Setup Time
t
AS
0
0
0
0
ns
Address Hold Time
t
AH
5
5
5
5
ns
Output Active from End of Write
t
OW
1
5
5
5
5
ns
Write Enable to Output in High Z
t
WHZ
1
25
25
35
35
ns
Data Hold from Write Time
t
DH
0
0
0
0
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, T
A
= -55C to +125C
Parameter
Symbol
-70
-85
-100
-120
Units
Read Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
70
85
100
120
ns
Address Access Time
t
AA
70
85
100
120
ns
Output Hold from Address Change
t
OH
5
5
5
5
ns
Chip Select Access Time
t
ACS
70
85
100
120
ns
Output Enable to Output Valid
t
OE
35
40
50
60
ns
Chip Select to Output in Low Z
t
CLZ
1
10
10
10
10
ns
Output Enable to Output in Low Z
t
OLZ
1
5
5
5
5
ns
Chip Disable to Output in High Z
t
CHZ
1
25
25
35
35
ns
Output Disable to Output in High Z
t
OHZ
1
25
25
35
35
ns
1. This parameter is guaranteed by design but not tested.
FIGURE 2 AC TEST CIRCUIT
WS512K32-XXX
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2005
Rev. 4
FIGURE 5 WRITE CYCLE - CS# CONTROLLED
ADDRESS
DATA I/O
WRITE CYCLE 2, CS# CONTROLLED
t
AW
t
AS
t
CW
t
AH
t
WP
t
DH
t
DW
t
WC
CS#
WE#
DATA VALID
FIGURE 3 TIMING WAVEFORM - READ CYCLE
ADDRESS
DATA I/O
READ CYCLE 2 (WE# = V
IH
)
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
OHZ
t
RC
DATA VALID
HIGH IMPEDANCE
CS#
OE#
t
CHZ
ADDRESS
DATA I/O
READ CYCLE 1 (CS# = OE# = V
IL
, WE# = V
IH
)
t
AA
t
OH
t
RC
DATA VALID
PREVIOUS DATA VALID
FIGURE 4 WRITE CYCLE - WE# CONTROLLED
ADDRESS
DATA I/O
WRITE CYCLE 1, WE# CONTROLLED
t
AW
t
CW
t
AH
t
WP
t
DW
t
WHZ
t
AS
t
OW
t
DH
t
WC
DATA VALID
CS#
WE#
WS512K32-XXX
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2005
Rev. 4
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
1
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
25.15 (0.990) 0.26 (0.010) SQ
22.36 (0.880) 0.26 (0.010) SQ
0.38 (0.015) 0.05 (0.002)
24.03 (0.946)
0.26 (0.010)
0.27 (0.011) 0.04 (0.002)
4.57 (0.180) MAX
23.87
(0.940) REF
0.25 (0.010) REF
1.0 (0.040)
0.127 (0.005)
0.19 (0.007)
0.06 (0.002)
R 0.25
(0.010)
1 / 7
SEE DETAIL "A"
DETAIL A
1.27 (0.050) TYP
20.3 (0.80) REF
Note 1: Package Not Recommended for New Designs.
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