WSE128K16-XXX

White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

128K

16 SRAM/EEPROM MODULE

PRELIMINARY*

FEATURES

s Access Times of 35ns (SRAM) and 150ns (EEPROM)
s Access Times of 45ns (SRAM) and 120ns (EEPROM)
s Access Times of 70ns (SRAM) and 300ns (EEPROM)
s Packaging

· 66 pin, PGA Type, 1.075" square HIP, Hermetic Ceramic

HIP (H1) (Package 400)

· 68 lead, Hermetic CQFP (G2T), 22mm (0.880") square

(Package 509). Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (Fig. 2)

s 128Kx16 SRAM
s 128Kx16 EEPROM
s Organized as 128Kx16 of SRAM and 128Kx16 of EEPROM

Memory with separate Data Buses

s Both blocks of memory are User Configurable as 256Kx8
s Low Power CMOS
s Commercial, Industrial and Military Temperature Ranges

s TTL Compatible Inputs and Outputs
s Built-in Decoupling Caps and Multiple Ground Pins for

Low Noise Operation

s Weight - 13 grams typical

EEPROM MEMORY FEATURES

s Write Endurance 10,000 Cycles
s Data Retention at 25

C, 10 Years

s Low Power CMOS Operation
s Automatic Page Write Operation
s Page Write Cycle Time 10ms Max.
s Data Polling for End of Write Detection
s Hardware and Software Data Protection
s TTL Compatible Inputs and Outputs

* This data sheet describes a product under development, not fully

characterized, and is subject to change without notice.

E W E E CS

S W E S CS

128K x 8

SRAM

S D

0 - 7

128K x 8

SRAM

S D

8 - 1 5

128K x 8

EEPROM

E D

0 - 7

128K x 8

EEPROM

E D

8 - 1 5

1 6

O E

S W E S CS

BLOCK DIAGRAM

PIN DESCRIPTION

0-15

EEPROM Data Inputs/Outputs

0-15

SRAM Data Inputs/Outputs

0-16

Address Inputs

SWE

1-2

SRAM Write Enable

SCS

1-2

SRAM Chip Selects

Output Enable

Power Supply

GND

Ground

Not Connected

EWE

1-2

EEPROM Write Enable

ECS

1-2

EEPROM Chip Select

SWE

SCS

GND

SCS

SWE

ECS

EWE

ECS

GND

11 22 33 44 55 66

1 12 23 34 45 56

TOP VIEW

FIG.1

PIN CONFIGURATION FOR WSE128K16-XH1X

May 2001, Rev. 4

White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520

WSE128K16-XXX

TOP VIEW

FIG. 2

PIN CONFIGURATION FOR WSE128K16-XG2TX

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

GND

SCS

SWE

EWE

GND

ECS

GND

ECS

SWE

BLOCK DIAGRAM

PIN DESCRIPTION

0-15

EEPROM Data Inputs/Outputs

0-15

SRAM Data Inputs/Outputs

0-16

Address Inputs

SWE

1-2

SRAM Write Enable

SCS

1-2

SRAM Chip Selects

Output Enable

Power Supply

GND

Ground

Not Connected

EWE

1-2

EEPROM Write Enable

ECS

1-2

EEPROM Chip Select

The WEDC 68 lead G2T CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2T has the TCE
and lead inspection advantage
of the CQFP form.

0.940"

E W E E CS

S W E S CS

128K x 8

SRAM

S D

0 - 7

128K x 8

SRAM

S D

8 - 1 5

128K x 8

EEPROM

E D

0 - 7

128K x 8

EEPROM

E D

8 - 1 5

1 6

O E

S W E S CS

WSE128K16-XXX

White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

EEPROM TRUTH TABLE

RECOMMENDED OPERATING CONDITIONS

Mode

Data I/O

Standby

High Z

Read

Data Out

Write

Data In

Out Disable

High Z/Data Out

Write

Inhibit

Parameter

Symbol

Min

Max

Unit

Supply Voltage

4.5

5.5

Input High Voltage

2.0

+ 0.3

Input Low Voltage

-0.3

+0.8

Operating Temp. (Mil.)

-55

+125

DC CHARACTERISTICS

= 5.0V, V

= 0V, T

= -55

C to +125

Parameter

Symbol

Conditions

Min

Max

Unit

Input Leakage Current

= 5.5, V

= GND to V

Output Leakage Current

SCS = V

, OE = V

IH,

OUT

= GND to V

SRAM Operating Supply Current x 16 Mode

CCx16

SCS = V

, OE = ECS = V

IH,

f = 5MHz, V

= 5.5

360

Standby Current

ECS = SCS = V

, OE = V

IH,

f = 5MHz, V

= 5.5

31.2

SRAM Output Low Voltage

(35 to 45ns)

= 8.0mA, V

= 4.5

0.4

(70ns)

= 2.1mA, V

= 4.5

0.4

SRAM Output High Voltage

(35 to 45ns)

= -4.0mA, V

= 4.5

2.4

(70ns)

= -1mA, V

= 4.5

2.4

EEPROM Operating Supply Current x 16 Mode

CC1

ECS = V

, OE = SCS = V

155

EEPROM Output Low Voltage

= 2.1 mA, V

= 4.5V

0.45

EEPROM Output High Voltage

OH1

= 400

A, V

= 4.5V

2.4

NOTES:
1. The I

current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).

The frequency component typically is less than 2 mA/MHz, with OE at V

2. DC test conditions: V

= 0.3V, V

= V

- 0.3V

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Min

Max

Unit

Operating Temperature

-55

+125

Storage Temperature

STG

-65

+150

Signal Voltage Relative to GND

-0.5

Vcc+0.5

Junction Temperature

150

Supply Voltage

-0.5

7.0

CAPACITANCE

= +25

Parameter

Symbol

Conditions

Max

Unit

OE capacitance

= 0 V, f = 1.0 MHz

1-4

capacitance

= 0 V, f = 1.0 MHz

HIP (PGA)

CQFP G2T

1-4

capacitance

= 0 V, f = 1.0 MHz

Data I/O capacitance

I/O

= 0 V, f = 1.0 MHz

Address input capacitance

= 0 V, f = 1.0 MHz

This parameter is guaranteed by design but not tested.

SRAM TRUTH TABLE

SCS

SWE

Mode

Data I/O

Power

Standby

High Z

Standby

Read

Data Out

Active

Read

High Z

Active

Write

Data In

Active

White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520

WSE128K16-XXX

FIG. 3

AC TEST CIRCUIT

AC TEST CONDITIONS

Current Source

D.U.T.

C = 50 pf

eff

1.5V

(Bipolar Supply)

Current Source

NOTES:
V

is programmable from -2V to +7V.

& I

programmable from 0 to 16mA.

Tester Impedance Z

= 75

is typically the midpoint of V

and V

& I

are adjusted to simulate a typical resistive load circuit.

ATE tester includes jig capacitance.

Parameter

Typ

Unit

Input Pulse Levels

= 0, V

= 3.0

Input Rise and Fall

Input and Output Reference Level

1.5

Output Timing Reference Level

1.5

SRAM AC CHARACTERISTICS

= 5.0V, GND = 0V, T

= -55

C to +125

Parameter

Symbol

-35

-45

-70

Units

Read Cycle

Min

Max

Min

Max

Min

Max

Read Cycle Time

Address Access Time

Output Hold from Address Change

Chip Select Access Time

ACS

Output Enable to Output Valid

Chip Select to Output in Low Z

CLZ

Output Enable to Output in Low Z

OLZ

Chip Disable to Output in High Z

CHZ

Output Disable to Output in High Z

OHZ

1. This parameter is guaranteed by design but not tested.

SRAM AC CHARACTERISTICS

= 5.0V, GND = 0V, T

= -55

C to +125

Parameter

Symbol

-35

-45

-70

Units

Write Cycle

Min

Max

Min

Max

Min

Max

Write Cycle Time

Chip Select to End of Write

Address Valid to End of Write

Data Valid to End of Write

Write Pulse Width

Address Setup Time

Address Hold Time

Output Active from End of Write

Write Enable to Output in High Z

WHZ

Data Hold Time

1. This parameter is guaranteed by design but not tested.

WSE128K16-XXX

White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

WS32K32-XHX

FIG. 4

SRAM READ CYCLE

FIG. 6

SRAM WRITE CYCLE

SCS CONTROLLED

FIG. 5

SRAM WRITE CYCLE

SWE CONTROLLED

ADDRESS

DATA I/O

WRITE CYCLE 1, SWE CONTROLLED

WHZ

DATA VALID

SCS

SWE

ADDRESS

DATA I/O

WRITE CYCLE 2, SCS CONTROLLED

SCS

SWE

DATA VALID

ADDRESS

DATA I/O

READ CYCLE 2, (SWE = V

)

ACS

CLZ

OLZ

OHZ

DATA VALID

HIGH IMPEDANCE

SCS

SOE

CHZ

ADDRESS

DATA I/O

READ CYCLE 1, (SCS = OE = V

, SWE = V

)

DATA VALID

PREVIOUS DATA VALID

SRAM

White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520

WSE128K16-XXX

EEPROM WRITE

A write cycle is initiated when OE is high and a low pulse is on
EWE or ECS with ECS or EWE low. The address is latched on the
falling edge of ECS or EWE whichever occurs last. The data is
latched by the rising edge of ECS or EWE, whichever occurs first.
A byte write operation will automatically continue to completion.

WRITE CYCLE TIMING

Figures 7 and 8 show the write cycle timing relationships. A
write cycle begins with address application, write enable and
chip select. Chip select is accomplished by placing the ECS
line low. Write enable consists of setting the EWE line low.
The write cycle begins when the last of either ECS or EWE goes
low.

The EWE line transition from high to low also initiates an
internal 150

sec delay timer to permit page mode operation.

Each subsequent EWE transition from high to low that occurs
before the completion of the 150

sec time out will restart the

timer from zero. The operation of the timer is the same as a
retriggerable one-shot.

EEPROM AC WRITE CHARACTERISTICS

= 5.0V, V

= 0V, T

= -55

C to +125

Write Cycle Parameter

Symbol

Min

Max

Unit

Write Cycle Time, TYP = 6ms

Address Set-up Time

Write Pulse Width (EWE or ECS)

150

Chip Select Set-up Time

Address Hold Time

100

Data Hold Time

Chip Select Hold Time

CSH

Data Set-up Time

100

Output Enable Set-up Time

OES

Output Enable Hold Time

OEH

Write Pulse Width High

WPH

White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520

WSE128K16-XXX

EEPROM AC READ CHARACTERISTICS

= 5.0V, V

= 0V, T

= -55

C to +125

FIG. 9

EEPROM READ WAVEFORMS

ADDRESS

ECS

1-2

EEPROM

DATA

OUTPUT

ACC

ACS

OUTPUT

VALID

ADDRESS VALID

HIGH Z

EEPROM READ

The WSE128K16-XXX EEPROM stores data at the memory
location determined by the address pins. When ECS and OE
are low and EWE is high, this data is present on the outputs.
When ECS and OE are high, the outputs are in a high imped-
ance state. This two line control prevents bus contention.

NOTES:
OE may be delayed up to t

ACS

- t

after the

falling edge of ECS without impact on t

or by

ACC

- t

after an address change without

impact on t

ACC

Read Cycle Parameter

Symbol

-120

-150

-300

Unit

Min

Max

Min

Max

Min

Max

Read Cycle Time

120

150

300

Address Access Time

ACC

120

150

300

Chip Select Access Time

ACS

120

150

300

Output Hold from Add. Change, OE or ECS

Output Enable to Output Valid

Chip Select or OE to High Z Output

WSE128K16-XXX

White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

EEPROM DATA POLLING

The WSE128K16-XXX offers a data polling feature for the
EEPROM which allows a faster method of writing to the device.
Figure 11 shows the timing diagram for this function. During a
byte or page write cycle, an attempted read of the last byte
written will result in the complement of the written data on D

(for each chip.) Once the write cycle has been completed, true
data is valid on all outputs and the next cycle may begin. Data
polling may begin at any time during the write cycle.

EEPROM DATA POLLING CHARACTERISTICS

= 5.0V, V

= 0V, T

= -55

C to +125

FIG. 10

EEPROM DATA POLLING WAVEFORMS

Parameter

Symbol

Min

Max

Unit

Data Hold Time

OE Hold Time

OEH

OE To Output Valid

Write Recovery Time

EWE

1-2

OEH

HIGH Z

ECS

1-2

ADDRESS

White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520

WSE128K16-XXX

EEPROM PAGE WRITE OPERATION

The WSE128K16-XXX has a page write operation that allows one
to 128 bytes of data to be written into the device and consecutively
loads during the internal programming period. Successive bytes
may be loaded in the same manner after the first data byte has
been loaded. An internal timer begins a time out operation at each
write cycle. If another write cycle is completed within 150

s or

less, a new time out period begins. Each write cycle restarts the
delay period. The write cycles can be continued as long as the
interval is less than the time out period.

The usual procedure is to increment the least significant
address lines from A0 through A6 at each write cycle. In this
manner a page of up to 128 bytes can be loaded in to the
EEPROM in a burst mode before beginning the relatively long
interval programming cycle.

After the 150

s time out is completed, the EEPROM begins an

internal write cycle. During this cycle the entire page of bytes
will be written at the same time. The internal programming
cycle is the same regardless of the number of bytes accessed.

EEPROM PAGE WRITE CHARACTERISTICS

= 5.0V, V

= 0V, T

= -55

C to +125

FIG. 11

EEPROM PAGE MODE
WRITE WAVEFORMS

1. Page address must remain valid for duration of write cycle.

Page Mode Write Characteristics

Symbol

Unit

Parameter

Min

Max

Write Cycle Time, TYP = 6ms

Address Set-up Time

Address Hold Time (1)

100

Data Set-up Time

100

Data Hold Time

Write Pulse Width

150

Byte Load Cycle Time

BLC

150

Write Pulse Width High

WPH

BYTE 0

BYTE 1

BYTE 2

BYTE 3

VALID DATA

VALID

ADDRESS

BLC

WPH

ADDRESS

EEPROM

DATA

ECS

1-2

EWE

1-2

BYTE 127

WSE128K16-XXX

White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA A0

ADDRESS 5555

LOAD DATA XX

ANY ADDRESS

(4)

LOAD LAST BYTE

LAST ADDRESS

FIG. 12

EEPROM SOFTWARE DATA PROTECTION
ENABLE ALGORITHM

(1)

WRITES ENABLED

(2)

NOTES:
1. Data Format: ED

- ED

(Hex);

Address Format: A

- A

(Hex).

2. Write Protect state will be activated at end of write even if no other

data is loaded.

3. Write Protect state will be deactivated at end of write period even if

no other data is loaded.

4. 1 to 128 bytes of data may be loaded.

ENTER DATA

PROTECT STATE

White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520

WSE128K16-XXX

EEPROM HARDWARE DATA PROTECTION

These features protect against inadvertent writes to the
WSE128K16-XXX. These are included to improve reliability
during normal operation:

a) V

power on delay

As V

climbs past 3.8V typical the device will wait 5msec

typical before allowing write cycles.

b) V

sense

While below 3.8V typical write cycles are inhibited.

c) Write inhibiting

Holding OE low and either ECS or EWE high inhibits write
cycles.

d) Noise filter

Pulses of <8ns (typ) on EWE or ECS will not initiate a write
cycle.

EEPROM SOFTWARE DATA PROTECTION

A software write protection feature may be enabled or disabled
by the user. When shipped by WEDC, the WSE128K16-XXX has
the feature disabled. Write access to the device is unre-
stricted.

To enable software write protection, the user writes three
access code bytes to three special internal locations. Once
write protection has been enabled, each write to the EEPROM
must use the same three byte write sequence to permit writing.
After setting software data protection, any attempt to write to
the device without the three-byte command sequence will start
the internal write timers. No data will be written to the device,
however, for the duration of t

. The write protection feature

can be disabled by a six byte write sequence of specific data to
specific locations. Power transitions will not reset the
software write protection.

Each 128K byte block of the EEPROM has independent write
protection. One or more blocks may be enabled and the rest
disabled in any combination. The software write protection
guards against inadvertent writes during power transitions, or
unauthorized modification using a PROM programmer.

FIG. 13

EEPROM SOFTWARE DATA PROTECTION
DISABLE ALGORITHM

(1)

EXIT DATA

PROTECT STATE

NOTES:
1. Data Format: ED

- ED

(Hex);

Address Format: A

- A

(Hex).

2. Write Protect state will be activated at end of write even if no other

data is loaded.

3. Write Protect state will be deactivated at end of write period even if

no other data is loaded.

4. 1 to 128 bytes of data may be loaded.

(3)

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 80

ADDRESS 5555

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 20

ADDRESS 5555

LOAD DATA XX

ANY ADDRESS

(4)

LOAD LAST BYTE

LAST ADDRESS

White Electronic Designs Corporation · Phoenix, AZ · (602) 437-1520

WSE128K16-XXX

PACKAGE 509:

68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)

0.38 (0.015)

0.05 (0.002)

0.27 (0.011)

0.04 (0.002)

25.15 (0.990)

0.26 (0.010) SQ

1.27 (0.050) TYP

24.03 (0.946)

0.26 (0.010)

22.36 (0.880)

0.26 (0.010) SQ

20.3 (0.800) REF

4.57 (0.180) MAX

0.19 (0.007)

0.06 (0.002)

23.87

(0.940) REF

1.0 (0.040)

0.127 (0.005)

0.25 (0.010) REF

/ 7

R 0.25

(0.010)

DETAIL A

SEE DETAIL "A"

Pin 1

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

0.940"

TYP

The WEDC 68 lead G2T CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2T has the TCE
and lead inspection advantage
of the CQFP form.

WSE128K16-XXX

White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com

LEAD FINISH:

Blank = Gold plated leads

A = Solder dip leads

DEVICE GRADE:

M = Military Screened

-55

C to +125

I = Industrial

-40

C to +85

C = Commercial

C to +70

PACKAGE TYPE:

H1 = 1.075" sq. Ceramic Hex-In-line Package, HIP (Package 400)
G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509)

ACCESS TIME (ns)

35 = 35ns SRAM and 150ns EEPROM
42 = 45ns SRAM and 120ns EEPROM
73 = 70ns SRAM and 300ns EEPROM

ORGANIZATION, 128K x 16

EEPROM

SRAM

WHITE ELECTRONIC DESIGNS CORP.

ORDERING INFORMATION

W S E 128K16 - XXX X X X

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