1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WSF128K32-XH2X
White Electronic Designs
128K
X
32 SRAM/FLASH MODULE
PRELIMINARY*
FEATURES
Access Times of 25ns (SRAM) and 70, 90 and 120ns
(FLASH)
Packaging:
66-pin, PGA Type, 1.385 inch square HIP, Hermetic
Ceramic HIP (Package 402)
128Kx32 SRAM
128Kx32 5V Flash
Organized as 128Kx32 of SRAM and 128Kx32 of
Flash Memory with common Data Bus
Low Power CMOS
Commercial, Industrial and Military Temperature Ranges
TTL Compatible Inputs and Outputs
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight - 13 grams typical
FLASH MEMORY FEATURES
10,000 Erase/Program Cycles
Sector Architecture
8 equal size sectors of 16K bytes each
Any combination of sectors can be concurrently
erased. Also supports full chip erase
5 Volt Programming; 5V 10% Supply
Embedded Erase and Program Algorithms
Hardware Write Protection
Page Program Operation and Internal Program
Control Time.
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note: Programming information available upon request.
FIG. 1 PIN CONFIGURATION FOR WSF128K32-XH2X
B
LOCK
D
IAGRAM
P
IN
D
ESCRIPTION
D
0-31
Data Inputs/Outputs
A
0-16
Address Inputs
SWE
1-4
SRAM Write Enables
SCS
SRAM Chip Select
OE
Output Enable
V
CC
Power Supply
GND
Ground
NC
Not Connected
FWE
1-4
Flash Write Enables
FCS
Flash Chip Select
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
NC
I/O
0
I/O
1
I/O
2
FWE
2
SWE
2
GND
I/O
11
A
10
A
9
A
15
V
CC
FCS
SCS
I/O
3
I/O
15
I/O
14
I/O
13
I/O
12
OE
NC
FWE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
7
A
12
SWE
1
A
13
A
8
I/O
16
I/O
17
I/O
18
V
CC
SWE
4
FWE
4
I/O
27
A
4
A
5
A
6
FWE
3
SWE
3
GND
I/O
19
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
I/O
22
I/O
21
I/O
20
11 22 33 44 55 66
1 12 23 34 45 56
T
OP
V
IEW
O E
F C S
S C S
A 0 - 1 6
F W E
1
S W E
1
128K x 8 Flash
128K x 8 SRAM
I/O0-7
F W E
2
S W E
2
128K x 8 Flash
128K x 8 SRAM
I/O8-15
F W E
3
S W E
3
128K x 8 Flash
128K x 8 SRAM
I/O16-23
F W E
4
S W E
4
128K x 8 Flash
128K x 8 SRAM
I/O24-31
October 2002 Rev. 4
2
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WSF128K32-XH2X
White Electronic Designs
NOTE:
1. FCS must remain high when SCS is low.
Parameter
Symbol
Min
Max
Unit
Operating Temperature
T
A
-55
+125
C
Storage Temperature
T
STG
-65
+150
C
Signal Voltage Relative to GND
V
G
-0.5
7.0
V
Junction Temperature
T
J
150
C
Supply Voltage
V
CC
-0.5
7.0
V
A
BSOLUTE
M
AXIMUM
R
ATINGS
DC C
HARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55C
TO
+125C)
Parameter
Symbol
ConditionsMin
Max
Unit
Input Leakage Current
I
LI
V
CC
= 5.5, V
IN
= GND to V
CC
10
A
Output Leakage Current
I
LO
SCS = V
IH
, OE = V
IH,
V
OUT
= GND to V
CC
10
A
SRAM Operating Supply Current x 32 Mode
I
CCx32
SCS = V
IL
, OE = FCS = V
IH,
f = 5MHz, V
CC
= 5.5
670
mA
Standby Current
I
SB
FCS = SCS = V
IH
, OE = V
IH,
f = 5MHz, V
CC
= 5.5
80
mA
SRAM Output Low Voltage
V
OL
I
OL
= 8mA, V
CC
= 4.5
0.4
V
SRAM Output High Voltage
V
OH
I
OH
= -4.0mA, V
CC
= 4.5
2.4
V
Flash V
CC
Active Current for Read (1)
I
CC1
FCS = V
IL
, OE = SCS = V
IH
220
mA
Flash V
CC
Active Current for Program or
I
CC2
FCS = V
IL
, OE = SCS = V
IH
280
mA
Erase (2)
Flash Output Low Voltage
V
OL
I
OL
= 8.0mA, V
CC
= 4.5
0.45
V
Flash Output High Voltage
V
OH1
I
OH
= -2.5 mA, V
CC
= 4.5
0.85 x V
CC
V
Flash Output High Voltage
V
OH2
I
OH
= -100 A, V
CC
= 4.5
V
CC
-0.4
V
Flash Low V
CC
Lock Out Voltage
V
LKO
3.2
V
Parameter
Flash Data Retention
10 years
Flash Endurance (write/erase cycles)
10,000
NOTE:
1. Stresses above the absolute maximum rating may cause
permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
4.5
5.5
V
Input High Voltage
V
IH
2.2
V
CC
+ 0.3
V
Input Low Voltage
V
IL
-0.5
+0.8
V
R
ECOMMENDED
O
PERATING
C
ONDITIONS
NOTES:
1. The I
CC
current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at V
IH
.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
SRAM T
RUTH
T
ABLE
SCS
OE
SWE
Mode
Data I/O
Power
H
X
X
Standby
High Z
Standby
L
L
H
Read
Data Out
Active
L
H
H
Read
High Z
Active
L
X
L
Write
Data In
Active
C
APACITANCE
(T
A
= +25C)
Test
Symbol
Condition
Max Unit
OE Capacitance
C
OE
V
IN
= 0V, f = 1.0MHz 80
pF
F/S WE 1-4 Capacitance
C
WE
V
IN
= 0V, f = 1.0MHz 30
pF
F/S CS Capacitance
C
CS
V
IN
= 0V, f = 1.0MHz 50
pF
D
0
-
31
Capacitance
C
I
/
O
V
IN
= 0V, f = 1.0MHz 30
pF
A
0
- A
16
Capacitance
C
AD
V
IN
= 0V, f = 1.0MHz 80
pF
This parameter is guaranteed by design but not tested.
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WSF128K32-XH2X
White Electronic Designs
Parameter
Symbol
-25
Unit
Read Cycle
Min
Max
Read Cycle Time
t
RC
25
ns
Address Access Time
t
AA
25
ns
Output Hold from Address Change
t
OH
0
ns
Chip Select Access Time
t
ACS
25
ns
Output Enable to Output Valid
t
OE
15
ns
Chip Select to Output in Low Z
t
CLZ
1
3
ns
Output Enable to Output in Low Z t
OLZ
1
0
ns
Chip Disable to Output in High Z
t
CHZ
1
12
ns
Output Disable to Output in High Z
t
OHZ
1
12
ns
1. This parameter is guaranteed by design but not tested.
SRAM AC CHARACTERISTICS
(V
CC
= 5.0V, T
A
= -55C
TO
+125C)
Parameter
Symbol -25
Unit
Write Cycle
Min
Max
Write Cycle Time
t
WC
25
ns
Chip Select to End of Write
t
CW
20
ns
Address Valid to End of Write
t
AW
20
ns
Data Valid to End of Write
t
DW
15
ns
Write Pulse Width
t
WP
20
ns
Address Setup Time
t
AS
0
ns
Address Hold Time
t
AH
0
ns
Output Active from End of Write
t
OW
1
3
ns
Write Enable to Output in High Z
t
WHZ
1
15
ns
Data Hold from Write Time
t
DH
0
ns
1. This parameter is guaranteed by design but not tested.
SRAM AC CHARACTERISTICS
(V
CC
= 5.0V, T
A
= -55C
TO
+125C)
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75 W.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
AC T
EST
C
ONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 3.0 V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
I
Current Source
D.U.T.
C = 50 pf
eff
I
OL
V
1.5V
(Bipolar Supply)
Z
Current Source
OH
FIG. 2 AC TEST CIRCUIT
4
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WSF128K32-XH2X
White Electronic Designs
FIG. 4 SRAM WRITE CYCLE - SWE CONTROLLED
ADDRESS
DATA I/O
t
AW
t
CW
t
AH
t
WP
t
DW
t
WHZ
t
AS
t
OW
t
DH
t
WC
DATA VALID
SCS
SWE
WS32K32-XHX
FIG. 5 SRAM WRITE CYCLE - SCS CONTROLLED
ADDRESS
DATA I/O
t
AW
t
AS
t
CW
t
AH
t
WP
t
DH
t
DW
t
WC
SCS
SWE
DATA VALID
ADDRESS
DATA I/O
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
OHZ
t
RC
DATA VALID
HIGH IMPEDANCE
SCS
SOE
t
CHZ
ADDRESS
DATA I/O
t
AA
t
OH
t
RC
DATA VALID
PREVIOUS DATA VALID
READ CYCLE 1, (SCS = OE = V
IL
, SWE = FCS = V
IH
)
READ CYCLE 2, (SWE = FCS = V
IH
)
WRITE CYCLE 1, SWE CONTROLLED (FCS = V
IH
)
WRITE CYCLE 2, SCS CONTROLLED (FCS = V
IH
)
FIG. 3 SRAM TIMING WAVEFORM - READ CYCLE
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WSF128K32-XH2X
White Electronic Designs
FLASH AC C
HARACTERISTICS
W
RITE
/E
RASE
/P
ROGRAM
O
PERATIONS
, FWE C
ONTROLLED
(V
CC
= 5.0V, T
A
= -55C
TO
+125C)
Parameter
Symbol
-70
-90
-120
Unit
Min Max Min Max Min Max
Write Cycle Time
t
AVAV
t
WC
70
90
120
ns
Chip Select Setup Time
t
ELWL
t
CS
0
0
0
ns
Write Enable Pulse Width
t
WLWH
t
WP
35
45
50
ns
Address Setup Time
t
AVWL
t
AS
0
0
0
ns
Data Setup Time
t
DVWH
t
DS
30
45
50
ns
Data Hold Time
t
WHDX
t
DH
0
0
0
ns
Address Hold Time
t
WLAX
t
AH
45
45
50
ns
Chip Select Hold Time
t
WHEH
t
CH
0
0
0
ns
Write Enable Pulse Width High
t
WHWL
t
WPH
20
20
20
ns
Duration of Byte Programming Operation (min)
t
WHWH1
14
14
14
s
Chip and Sector Erase Time
t
WHWH2
2.2
60
2.2
60
2.2
60
sec
Read Recovery Time Before Write
t
GHWL
0
0
0
s
V
CC
Set-up Time
t
VCS
50
50
50
s
Chip Programming Time
12.5
12.5
12.5
sec
Output Enable Setup Time
t
OES
0
0
0
ns
Output Enable Hold Time (1)
t
OEH
10
10
10
ns
1. For Toggle and Data Polling.
FLASH AC C
HARACTERISTICS
R
EAD
O
NLY
O
PERATIONS
(V
CC
= 5.0V, T
A
= -55C
TO
+125C)
Parameter
Symbol
-70
-90
-120
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
AVAV
t
RC
70
90
120
ns
Address Access Time
t
AVQV
t
ACC
70
90
120
ns
Chip Select Access Time
t
ELQV
t
CE
70
90
120
ns
OE to Output Valid
t
GLQV
t
OE
35
40
50
ns
Chip Select to Output High Z (1)
t
EHQZ
t
DF
20
25
30
ns
OE High to Output High Z (1)
t
GHQZ
t
DF
20
25
30
ns
Output Hold from Address, FCS or OE Change,
t
AXQX
t
OH
0
0
0
ns
whichever is first
1. Guaranteed by design, not tested.
6
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WSF128K32-XH2X
White Electronic Designs
Parameter
Symbol
-70
-90
-120
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
AVAV
t
WC
70
90
120
ns
FWE Setup Time
t
WLEL
t
WS
0
0
0
ns
FCS Pulse Width
t
ELEH
t
CP
35
45
50
ns
Address Setup Time
t
AVEL
t
AS
0
0
0
ns
Data Setup Time
t
DVEH
t
DS
30
45
50
ns
Data Hold Time
t
EHDX
t
DH
0
0
0
ns
Address Hold Time
t
ELAX
t
AH
45
45
50
ns
FWE Hold from FWE High
t
EHWH
t
WH
0
0
0
ns
FCS Pulse Width High
t
EHEL
t
CPH
20
20
20
ns
Duration of Programming Operation
t
WHWH1
14
14
14
s
Duration of Erase Operation
t
WHWH2
2.2
60
2.2
60
2.2
60
sec
Read Recovery before Write
t
GHEL
0
0
0
ns
Chip Programming Time
12.5
12.5
12.5
sec
FLASH AC C
HARACTERISTICS
W
RITE
/E
RASE
/P
ROGRAM
O
PERATIONS
, FCS C
ONTROLLED
(V
CC
= 5.0V, T
A
= -55C
TO
+125C)
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WSF128K32-XH2X
White Electronic Designs
FIG. 6 AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS
A
ddresses
FCS
OE
FWE
Outputs
High Z
Addresses Stable
t
OE
t
RC
Output Valid
t
CE
t
ACC
t
OH
High Z
t
DF
NOTE: SCS = V
IH
8
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WSF128K32-XH2X
White Electronic Designs
FIG. 7 WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE
CONTROLLED
NOTES:
1. PA is the address of the memory location
to be programmed.
2. PD is the data to be programmed at byte
address.
3. D
7
is the output of the complement of the
data written to the device.
4. D
OUT
is the output of the data written to
the device.
5. Figure indicates last two bus cycles of four
bus cycle sequence.
6. SCS = V
IH
A
ddresses
FCS
OE
FWE
Data
5.0 V
5555H
P
A
P
A
t
WC
t
CS
PD
D
7
D
OUT
t
AH
t
WPH
t
DH
t
DS
Data Polling
t
AS
t
RC
t
WP
A0H
t
OE
t
DF
t
OH
t
CE
t
GHWL
t
WHWH1
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WSF128K32-XH2X
White Electronic Designs
FIG. 8 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR
FLASH MEMORY
Notes:
1. SA is the sector address
for Sector Erase.
2. SCS = V
IH
A
ddresses
FCS
OE
FWE
Data
V
CC
5555H
2AAAH
2
AAAH
S
A
5555H
5555H
t
WP
t
CS
t
VCS
10H/30H
55H
80H
55H
AAH
AAH
t
AH
t
AS
t
GHWL
t
WPH
t
DH
t
DS
10
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WSF128K32-XH2X
White Electronic Designs
FIG. 9 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED
ALGORITHM OPERATIONS FOR FLASH MEMORY
FCS
OE
FWE
t
OE
t
OE
D7
D7
Valid Data
t
CE
t
CH
t
OH
High Z
D7
D7 =
Valid Data
High Z
D0-D6 = Invalid
D0-D7
Valid Data
t
DF
D7
D7
D0-D6
t
OEH
t
WHWH 1 or 2
t
WHWH 1 or 2
Note: SCS = V
IH
11
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WSF128K32-XH2X
White Electronic Designs
FIG. 10 WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS
CONTROLLED
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D
7
is the output of the complement of the data written to the device.
4. D
OUT
is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
6. SCS = V
IH
A
ddresses
FWE
OE
FCS
Data
5.0 V
5555H
P
A
P
A
t
WC
t
WS
PD
D
7
D
OUT
t
AH
t
CPH
t
CP
t
DH
t
DS
Data Polling
t
AS
t
GHEL
A0H
t
WHWH1
12
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WSF128K32-XH2X
White Electronic Designs
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
M = Military Screened
-55C to +125C
I = Industrial
-40C to +85C
C = Commercial
0C to +70C
PACKAGE TYPE:
H2 = Ceramic Hex In-line Package, HIP (Package 402)
ACCESS TIME (ns)
22 = 25ns SRAM and 120ns FLASH
29 = 25ns SRAM and 90ns FLASH
27 = 25ns SRAM and 70ns FLASH
ORGANIZATION, 128K x 32
Flash PROM
SRAM
WHITE ELECTRONIC DESIGNS CORP.
ORDERING INFORMATION
W S F 128K32 - XX H2 X X
PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2)
35.2 (1.385) 0.38 (0.015) SQ
25.4 (1.0) TYP
15.24 (0.600) TYP
0.76 (0.030) 0.1 (0.005)
5.7 (0.223)
MAX
3.81 (0.150)
0.1 (0.005)
2.54 (0.100)
TYP
25.4 (1.0) TYP
1.27 (0.050) 0.1 (0.005)
1.27 (0.050) TYP DIA
0.46 (0.018) 0.05 (0.002) DIA
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PDF 
ZIP