WSF41632-22XX
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
October, 2002
Rev. 4
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
128K
X
32 SRAM & 512Kx32 FLASH MIXED MODULE
Built-in decoupling caps and multiple ground pins
for low noise operation
Weight - 13 grams typical
FLASH MEMORY FEATURES
100,000 erase/program cycles minimum
Sector architecture
8 equal size sectors of 64KBytes each
Any combination of sectors can be concurrently
erased. Also supports full chip erase
5V programming; 5V 10% supply
Embedded erase and program algorithms
Hardware write protection
Page program operation and internal program
control time.
Note: For programming information refer to fl ash programming 4M5 application note.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
FEATURES
Access times of 25ns (SRAM) and 120ns (FLASH)
Packaging
66 pin, PGA Type, 1.385" square HIP, hermetic
ceramic HIP (Package 402)
68 lead, hermetic CQFP (G2T), 22.4mm (0.880")
square (Package 509) 4.57mm (0.180") height
Designed to fi t JEDEC 68 lead 0.990" CQFJ
footprint (FIGURE 2). Package to be developed.
128Kx32
SRAM
512Kx32
5V
Flash
Organized as 128Kx32 of SRAM and 512Kx32 of
Flash Memory with common data bus
Low power CMOS
Commercial, industrial and military temperature
ranges
TTL compatible inputs and outputs
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
A
18
I/O
0
I/O
1
I/O
2
FWE
2
#
SWE
2
#
GND
I/O
11
A
10
A
9
A
15
V
CC
FCS#
SCS#
I/O
3
I/O
15
I/O
14
I/O
13
I/O
12
OE#
A
17
FWE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
7
A
12
SWE
1
#
A
13
A
8
I/O
16
I/O
17
I/O
18
V
CC
SWE
4
#
FWE
4
#
I/O
27
A
4
A
5
A
6
FWE
3
#
SWE
3
#
GND
I/O
19
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
I/O
22
I/O
21
I/O
20
11 22 33 44 55 66
1 12 23 34 45 56
PIN CONFIGURATION FOR WSF41632-22H2X
Block Diagram
Pin Description
D0-31
Data Inputs/Outputs
A0-18
Address Inputs
SWE#1-4
SRAM Write Enables
SCS#
SRAM Chip Select
OE#
Output Enable
VCC
Power Supply
GND
Ground
NC Not
Connected
FWE#1-4
Flash Write Enables
FCS
Flash Chip Select
O E #
F C S #
S C S #
A
0-18
F W E
1
#
S W E
1
#
F W E
2
#
S W E
2
#
F W E
3
#
S W E
3
#
F W E
4
#
S W E
4
#
128K x 8 Flash
128K x 8 SRAM
I/O
0-7
128K x 8 Flash
128K x 8 SRAM
I/O
8-15
128K x 8 Flash
128K x 8 SRAM
I/O
16-23
128K x 8 Flash
128K x 8 SRAM
I/O
24-31
Top View
WSF41632-22XX
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
October, 2002
Rev. 4
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FIGURE 2 PIN CONFIGURATION FOR WSF41632-22G2TX
Block Diagram
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
FCS#
OE#
SWE
2
#
NC
FWE
2
#
FWE
3
#
FWE
4
#
NC
SCS#
SWE
1
#
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
NC
A
0
A
1
A
2
A
3
A
4
A
5
SWE
3
#
GND
SWE
4
#
FWE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
0.940"
The WEDC 68 lead G2T CQFP fi lls the same fi t and function
as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has
the TCE and lead inspection advantage of the CQFP form.
O E #
F C S #
S C S #
A
0-18
F W E
1
#
S W E
1
#
F W E
2
#
S W E
2
#
F W E
3
#
S W E
3
#
F W E
4
#
S W E
4
#
128K x 8 Flash
128K x 8 SRAM
I/O
0-7
128K x 8 Flash
128K x 8 SRAM
I/O
8-15
128K x 8 Flash
128K x 8 SRAM
I/O
16-23
128K x 8 Flash
128K x 8 SRAM
I/O
24-31
Pin Description
D0-31
Data Inputs/Outputs
A0-18
Address Inputs
SWE#1-4
SRAM Write Enables
SCS#
SRAM Chip Select
OE#
Output Enable
VCC
Power Supply
GND
Ground
NC Not
Connected
FWE#1-4
Flash Write Enables
FCS
Flash Chip Select
WSF41632-22XX
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
October, 2002
Rev. 4
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
DC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55C T
A
+125C
Parameter
Symbol
Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
CC
= 5.5, V
IN
= GND to V
CC
10
A
Output Leakage Current
I
LO
SCS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
10
A
SRAM Operating Supply Current x 32 Mode
I
CCx32
SCS# = V
IL
, OE# = FCS# = V
IH
, f = 5MHz, V
CC
= 5.5
620
mA
Standby Current
I
SB
FCS# = SCS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
80
mA
SRAM Output Low Voltage
V
OL
I
OL
= 8mA, V
CC
= 4.5
0.4
V
SRAM Output High Voltage
V
OH
I
OH
= -4.0mA, V
CC
= 4.5
2.4
V
Flash V
CC
Active Current for Read (1)
I
CC1
FCS# = V
IL
, OE# = SCS# = V
IH
260
mA
Flash V
CC
Active Current for Program or Erase (2)
I
CC2
FCS# = V
IL
, OE# = SCS# = V
IH
300
mA
Flash Output Low Voltage
V
OL
I
OL
= 8.0mA, V
CC
= 4.5
0.45
V
Flash Output High Voltage
V
OH1
I
OH
= -2.5 mA, V
CC
= 4.5
0.85 x V
CC
V
Flash Output High Voltage
V
OH2
I
OH
= -100 A, V
CC
= 4.5
V
CC
-0.4
V
Flash Low V
CC
Lock Out Voltage
V
LKO
3.2
4.2
V
NOTES:
1. The
I
CC
current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2mA/MHz, with OE# at V
IH
.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
SRAM TRUTH TABLE
SCS#
OE#
SWE#
Mode
Data I/O
Power
H
X
X
Standby
High Z
Standby
L
L
H
Read
Data Out
Active
L
H
H
Read
High Z
Active
L
X
L
Write
Data In
Active
NOTE:
1. FCS# must remain high when SCS# is low.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Max
Unit
Operating Temperature
T
A
-55 +125
C
Storage Temperature
T
STG
-65
+150
C
Signal Voltage Relative to GND
V
G
-0.5
7.0
V
Junction Temperature
T
J
150
C
Supply Voltage
V
CC
-0.5
7.0
V
Parameter
Flash Data Retention
20 years
Flash Endurance (write/erase cycles)
100,000 min
NOTE:
1. Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and
affect reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
4.5
5.5
V
Input High Voltage
V
IH
2.2
V
CC
+ 0.3
V
Input Low Voltage
V
IL
-0.5
+0.8
V
CAPACITANCE
Ta = +25C
Parameter
Symbol
Conditions Max Unit
OE# capacitance
C
OE
V
IN
= 0 V, f = 1.0 MHz
80
pF
F/S WE
1-4
# capacitance
C
WE
V
IN
= 0 V, f = 1.0 MHz
30
pF
F/S CS# capacitance
C
CS
V
IN
= 0 V, f = 1.0 MHz
50
pF
D
0-31
capacitance
C
I/O
V
IN
= 0 V, f = 1.0 MHz
30
pF
A
0-16
capacitance
C
AD
V
IN
= 0 V, f = 1.0 MHz
80
pF
This parameter is guaranteed by design but not tested.
WSF41632-22XX
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
October, 2002
Rev. 4
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
I
Current Source
D.U.T.
C = 50 pf
eff
I
OL
V 1.5V
(Bipolar Supply)
Z
Current Source
OH
SRAM AC CHARACTERISTICS
V
CC
= 5.0V, -55C T
A
+125C
Parameter
Read Cycle
Symbol
-25
Units
Min
Max
Read Cycle Time
t
RC
25
ns
Address Access Time
t
AA
25
ns
Output Hold from Address Change
t
OH
0
ns
Chip Select Access Time
t
ACS
25
ns
Output Enable to Output Valid
t
OE
15
ns
Chip Select to Output in Low Z
t
CLZ
1
3
ns
Output Enable to Output in Low Z
t
OLZ
1
0
ns
Chip Disable to Output in High Z
t
CHZ
1
12
ns
Output Disable to Output in High Z
t
OHZ
1
12
ns
1. This parameter is guaranteed by design but not tested.
SRAM AC CHARACTERISTICS
V
CC
= 5.0V, -55C T
A
+125C
Parameter
Write Cycle
Symbol
-25
Units
Min
Max
Write Cycle Time
t
WC
25
ns
Chip Select to End of Write
t
CW
20
ns
Address Valid to End of Write
t
AW
20
ns
Data Valid to End of Write
t
DW
15
ns
Write Pulse Width
t
WP
20
ns
Address Setup Time
t
AS
3
ns
Address Hold Time
t
AH
0
ns
Output Active from End of Write
t
OW
1
3
ns
Write Enable to Output in High Z
t
WHZ
1
15
ns
Data Hold from Write Time
t
DH
0
ns
1. This parameter is guaranteed by design but not tested.
FIGURE 2 AC TEST CIRCUIT
AC Test Conditions
Parameter
Typ
Unit
Input Pulse Levels
V
IL
= 0, V
IH
= 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75 .
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
WSF41632-22XX
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
October, 2002
Rev. 4
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ADDRESS
DATA I/O
t
AW
t
AS
t
CW
t
AH
t
WP
t
DH
t
DW
t
WC
SCS#
SWE#
DATA VALID
FIGURE 3 SRAM TIMING WAVEFORM - READ CYCLE
FIGURE 4 SRAM WRITE CYCLE - SWE# CONTROLLED
FIGURE 5 SRAM WRITE CYCLE - SCS# CONTROLLED
ADDRESS
DATA I/O
t
AA
t
OH
t
RC
DATA VALID
PREVIOUS DATA VALID
READ CYCLE 1, (SCS# = OE# = V
IL
, SWE# = FCS# = V
IH
)
READ CYCLE 2, (SWE# = FCS# = V
IH
)
WRITE CYCLE 2, SCS# CONTROLLED (FCS# = V
IH
)
WRITE CYCLE 1, SWE# CONTROLLED (FCS# = V
IH
)
ADDRESS
DATA I/O
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
OHZ
t
RC
DATA VALID
HIGH IMPEDANCE
SCS#
SOE#
t
CHZ
ADDRESS
DATA I/O
t
AW
t
CW
t
AH
t
WP
t
DW
t
WHZ
t
AS
t
OW
t
DH
t
WC
DATA VALID
SCS#
SWE#
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