WV3DG7266V-D1
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 1
PRELIMINARY*
512MB 2x32Mx72 SDRAM, UNBUFFERED, w/PLL
FEATURES
PC100
and
PC133
Burst
Mode
Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
3.3V 0.3V Power Supply
Dual
Rank
144
Pin
SO-DIMM
JEDEC
PCB: 31.75mm (1.25")
DESCRIPTION
The WV3DG7266V is a 2x32Mx72 synchronous DRAM
module which consists of nine stacked 64Mx8 with 4 banks
SDRAM components in TSOP II package, and one 2Kb
EEPROM for Serial Presence Detect which are mounted
on a 144 pin SO-DIMM multilayer FR4 Substrate.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
PIN NAMES
A0 A12
Address Input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CLK0, CLK1
Clock Input
CB0-7
Check Bit (Data-In/Data-Out)
CKE0
Clock Enable Input
CS0#, CS1#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
#Write Enable
DQM0-7
DQM
V
CC
Power Supply (3.3V)
V
SS
Ground
SDA
Serial Data I/O
SCL
Serial Clock
DNU
Do Not Use
NC
No Connect
* These pins are not used in this module
** These pins should be NC in the system which does
not support SPD.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PINOUT
PIN
FRONT
PIN
BACK
PIN
FRONT
PIN
BACK
PIN
FRONT
PIN
BACK
1
V
SS
2
V
SS
49
DQ13
50
DQ45
97
DQ22
98
DQ54
3
DQ0
4
DQ32
51
DQ14
52
DQ46
99
DQ23
100
DQ55
5
DQ1
6
DQ33
53
DQ15
54
DQ47
101
V
CC
102
V
CC
7
DQ2
8
DQ34
55
V
SS
56
V
SS
103
A6
104
A7
9
DQ3
10
DQ35
57
CB0
58
CB4
105
A8
106
BA0
11
V
CC
12
V
CC
59
CB1
60
CB5
107
V
SS
108
V
SS
13
DQ4
14
DQ36
61
CLK0
62
CKE0
109
A9
110
BA1
15
DQ5
16
DQ37
63
V
CC
64
V
CC
111
A10
112
A11
17
DQ6
18
DQ38
65
RAS#
66
CAS#
113
V
CC
114
V
CC
19
DQ7
20
DQ39
67
WE#
68
CKE1
115
DQM2
116
DQM6
21
V
SS
22
V
SS
69
CS0#
70
A12
117
DQM3
118
DQM7
23
DQM0
24
DQM4
71
CS1#*
72
NC
119
V
SS
120
V
SS
25
DQM1
26
DQM5
73
NC
74
CLK1
121
DQ24
122
DQ56
27
V
CC
28
V
CC
75
V
SS
76
V
SS
123
DQ25
124
DQ57
29
A0
30
A3
77
CB2
78
CB6
125
DQ26
126
DQ58
31
A1
32
A4
79
CB3
80
CB7
127
DQ27
128
DQ59
33
A2
34
A5
81
V
CC
82
V
CC
129
V
CC
130
V
CC
35
V
SS
36
V
SS
83
DQ16
84
DQ48
131
DQ28
132
DQ60
37
DQ8
38
DQ40
85
DQ17
86
DQ49
133
DQ29
134
DQ61
39
DQ9
40
DQ41
87
DQ18
88
DQ50
135
DQ30
136
DQ62
41
DQ10
42
DQ42
89
DQ19
90
DQ51
137
DQ31
138
DQ63
43
DQ11
44
DQ43
91
V
SS
92
V
SS
139
V
SS
140
V
SS
45
V
CC
46
V
CC
93
DQ20
94
DQ52
141
SDA
142
SCL
47
DQ12
48
DQ44
95
DQ21
96
DQ53
143
V
CC
144
V
CC
WV3DG7266V-D1
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 1
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
CAS#
RAS#
CKE0
CKE0: SDRAM
CAS#: SDRAM
RAS#: SDRAM
A0-A12: SDRAM
A0-A12
BA0-BA1
BA0-BA1: SDRAM
WE#
WE#: SDRAM
CS0#
CS0#: SDRAM
CS1#
CS1#: SDRAM
V
SS
V
CC
SDRAM
SDRAM
Two 0.1uf capacitors per each SDRAM
Serial PD
SDA
SCL
A2
A1
A0
10
CLK0
PLL CLOCK
DRIVER
CK0
10pF
12pF
CLK1
10pF
10
DQn
Every DQPin of SDRAM
10
DQM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#
DQM
CS#
DQM
CS#
DQM
CS#
DQM
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#
DQM
CS#
DQM
CS#
DQM
CS#
DQM
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#
DQM
CS#
DQM
CS#
DQM
CS#
DQM
DQM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#
DQM
CS#
DQM
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS#
DQM
CS#
DQM
CS#
DQM
CS#
DQM
WV3DG7266V-D1
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 1
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
, V
CCQ
-1.0 ~ 4.6
V
Storage Temperature
T
STG
-55 ~ +150
C
Power Dissipation
P
D
18
W
Short Circuit Current
I
OS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, 0C
T
A
+70C
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
V
CC
3.0
3.3 3.6
V
Input High Voltage
V
IH
2.0
3.0
V
CCQ
+0.3
V
1
Input Low Voltage
V
IL
-0.3
--
0.8
V
2
Output High Voltage
V
OH
2.4
--
--
V
I
OH
= -2mA
Output Low Voltage
V
OL
--
--
0.4
V
I
OL
= -2mA
Input Leakage Current
I
LI
-10
--
10
A
3
Notes:
1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is 3ns.
2. V
IL
(min)= -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V V
IN
V
CCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
T
A
= 25C, f = 1MHz, V
CC
= 3.3V, V
REF
= 1.4V 200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
C
IN1
95
pF
Input Capacitance (RAS#,CAS#,WE#)
C
IN2
95
pF
Input Capacitance (CKE0)
C
IN3
95
pF
Input Capacitance (CLK0)
C
IN4
18
pF
Input Capacitance (CS0#, CS1#)
C
IN5
50
pF
Input Capacitance (DQM0-DQM7)
C
IN6
10
pF
Input Capacitance (BA0-BA1)
C
IN7
95
pF
Data Input/Output Capacitance (DQ0-DQ63)
C
OUT
16
pF
Data Input/Output Capacitance (CB0-7)
C
OUT1
16
pF
WV3DG7266V-D1
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 1
PRELIMINARY
OPERATING CURRENT CHARACTERISTICS
(V
CC
= 3.3V, T
A
= 0C +70C)
Parameter
Symbol
Conditions
Value
Units
Note
7
75
10
Operating current
(One bank active)
I
CC1
Burst Length = 1
t
RC
t
RC
(min)
I
O
= 0mA
1170
1080
1080
mA
1
Precharge standby current in
power-down mode
I
CC2P
CKE V
IL
(max), t
CC
= 10ns
36
mA
3
I
CC2PS
CKE & CLK
V
IL
(max), t
CC
=
36
Precharge standby current in
non power-down mode
Icc
2N
CKE
V
IH
(min), CS# V
IH
(min), tcc =10ns
Input signals are charged one time during 20ns
360
mA
3
I
CC2NS
CKE V
IH
(min), CLK V
IL
(max), t
CC
=
Input signals are stable
180
Active standby current in
power-down mode
I
CC3P
CKE V
IL
(max), t
CC
= 10ns
108
mA
3
I
CC3PS
CKE & CLK
V
IL
(max), t
CC
=
108
Active Standby Current in
Non-Power Down Mode
I
CC3N
CKE V
IH
(min), CS# V
IH
(min), tcc = 10ns Input
signals are changed one time during 20ns
540
mA
3
I
CC3NS
CKE V
IH
(min), CLK V
IL
(max), tcc =
Input signals are stable
450
mA
3
Operating Current (Burst mode)
I
CC4
Io = mA
Page burst
4 Banks activated
t
CCD
= 2CLK
1260
1260
1170
mA
1
Refresh Current
I
CC5
t
RC
t
RC
(min)
2250
2070
1980
mA
2
Self Refresh Current
I
CC6
CKE 0.2V
54
mA
3
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1 PLL & 3 Drive ICs.
WV3DG7266V-D1
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 1
PRELIMINARY
OPERATING AC PARAMETER
Parameter
Symbol
Version
Unit
Note
7
75
10
Row active to row active delay
t
RRD(min)
15
15
20
ns
1
RAS# to CAS# delay
t
RCD(min)
15
20
20
ns
1
Row precharge time
t
RP(min)
15
20
20
ns
1
Row active time
t
RAS(min)
45
45
50
ns
1
t
RAS(max)
100
us
Row cycle time
t
RC(min)
60
65
70
ns
1
Last data in to row precharge
t
RDL(min)
2
CLK
2
Last data in to Active delay
t
DAL(min)
2 CLK + tRP
--
Last data in to new col. address delay
t
CDL(min)
1
CLK
2
Last data in to burst stop
t
BDL(min)
1
CLK
2
Col. address to col. address delay
t
CCD(min)
1
CLK
3
Number of valid output data
CAS latency=3
2
ea
4
CAS latency=2
1
Notes:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC OPERATING TEST CONDITIONS
V
CC
= 3.3v, 0C - 70C
Parameter
Value
Unit
AC input levels (V
IH
/V
IL
)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
t
R
/t
F
= 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
DC OUTPUT LOAD CIRCUIT
AC OUTPUT LOAD CIRCUIT
3.3V
1200
870
Output
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
50pF
Z0 = 50
WV3DG7266V-D1
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 1
PRELIMINARY
OPERATING AC PARAMETERS
Parameter
Symbol
7
75
10
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
CC
7.5
1000
7.5
1000
10
1000
ns
1
CAS latency=2
7.5
10
10
CLK to valid output delay
CAS latency=3
t
SAC
5.4
5.4
6
ns
1, 2
CAS latency=2
5.4
6
6
Output data hold time
CAS latency=3
t
OH
3
3
3
ns
2
CAS latency=2
3
3
3
CLK high pulse width
t
CH
2.5
2.5
3
ns
3
CLK low pulse width
t
CL
2.5
2.5
3
ns
3
Input setup time
t
SS
1.5
1.5
2
ns
3
Input hold time
t
SH
0.8
0.8
1
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
ns
2
CLK to outpu in Hi-Z
CAS latency=3
t
SHZ
5.4
5.4
6
ns
CAS latency=2
5.4
6
6
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
WV3DG7266V-D1
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 1
PRELIMINARY
Ordering Information
Speed
CAS Latency
Height*
WV3DG7266V10D1
100MHz
CL=2
31.75 (1.250")
WV3DG7266V7D1
133MHz
CL=2
31.75 (1.250")
WV3DG7266V75D1
133MHz
CL=3
31.75 (1.250")
NOTES:
Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is
shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult
factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR D1
67.56 (2.66)
63.60 (2.50)
4.60 (0.18)
23.20
(0.91)
32.80 (1.29)
3.30
(0.13)
2 - 1.80
(0.07)
2 - R 2.00
(0.078) Min
1.00 0.10
(0.04 0.0039)
31.75
(1.25)
3.20
(0.125) Min
4.00
(0.157) Min
20.00
(0.79)
4.00
0.10
(0.16 0.039)
6.00
(0.24)
2.10 (0.083)
2.50
(0.10)
3.80
(0.15)
1
59
61
143
2
144
6.35 (0.250) Max
PACKAGE DIMENSIONS FOR D1
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
WV3DG7266V-D1
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
August 2005
Rev. 1
PRELIMINARY
Document Title
512MB 2x32Mx72 SDRAM UNBUFFERED, w/PLL
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
4-05
Preliminary
Rev 1
1.1 Update functional block diagram
8-05
Preliminary
PDF 
ZIP