1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
April 2005
Rev. 0
ADVANCED*
WV3EG232M64EFSU-D4
White Electronic Designs
512MB 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA
FEATURES
Fast data transfer rate: PC-2100 and PC-2700
Clock speeds of 133 MHz and 166 MHz
Two data transfers per clock cycle
Supports ECC error detection and correction
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2 and 2.5 (clock)
Programmable Burst Length (2, 4 or 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect (SPD) with EEPROM
Dual
Rank
Power supply: V
CC
= V
CCQ
= +2.5V 0.2V (133 and
166MHz)
Gold edge contacts
200 pin, small-outline, SO-DIMM package
PCB height option:
31.75 mm (1.25")
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
DESCRIPTION
The WV3EG232M64EFSU is a 2x32Mx64 Double Data
Rate SDRAM memory module based on 256Mb DDR
SDRAM components. The module consists of sixteen
32Mx8 4 banks DDR SDRAMs in FBGA packages
mounted on a 200 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system ap pli ca tions.
* This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
OPERATING FREQUENCIES
DDR333@CL=2.5
DDR266@CL=2
DDR266@CL=2.5
Clock Speed
166MHz
133MHz
133MHz
CL-t
RCD
-t
RP
2.5-3-3
2-2-2
2.5-3-3
WV3EG232M64EFSU-D4
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
April 2005
Rev. 0
ADVANCED
PIN NAMES
Symbol
Description
A0-A12
Address input
BA0, BA1
Bank Address
DQ0-DQ63
Input/Output: Data I/Os, Data bus
CK0, CK0#
Clock Input
CKE0-CKE1
Clock Enable Input
CS0#-CS1#
Chip Select Input
WE#, CAS#, RAS# Command Input
DQS0-DQS7
Data Strobe
DM0-DM7
Data Write Mask
V
CC
Supply: Power Supply: +2.5V 0.2V
V
CCQ
Power Supply for DQS
V
CCSPD
Supply: Serial EEPROM Positive
Power Supply
V
REF
Supply: SSTL_2 reference voltage
V
SS
Supply: Ground
SCL
Serial Clock
SA0-SA2
Presence Detect Address Input
V
CCID
V
CC
Identifi cation Flag
SDA
Input/Output: Serial Presence-Detect
Data
NC
No Connect
DNU
Do Not Use
RESET#
Reset Enable
* These pins are not used in this module.
PIN CONFIGURATION
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
1
V
REF
51
V
SS
101
A9
151
DQ42
2
V
REF
52
V
SS
102
A8
152
DQ46
3
V
SS
53
DQ19
103
V
SS
153
DQ43
4
V
SS
54
DQ23
104
V
SS
154
DQ47
5
DQ0
55
DQ24
105
A7
155
V
CC
6
DQ4
56
DQ28
106
A6
156
V
CC
7
DQ1
57
V
CC
107
A5
157
V
CC
8
DQ5
58
V
CC
108
A4
158
*CK1#
9
V
CC
59
DQ25
109
A3
159
V
SS
10
V
CC
60
DQ29
110
A2
160
*CK1
11
DQS0
61
DQS3
111
A1
161
V
SS
12
DM0
62
DM3
112
A0
162
V
SS
13
DQ2
63
V
SS
113
V
CC
163
DQ48
14
DQ6
64
V
SS
114
V
CC
164
DQ52
15
V
SS
65
DQ26
115
A10/AP
165
DQ49
16
V
SS
66
DQ30
116
BA1
166
DQ53
17
DQ3
67
DQ27
117
BA0
167
V
CC
18
DQ7
68
DQ31
118
RAS#
168
V
CC
19
DQ8
69
V
CC
119
WE#
169
DQS6
20
DQ12
70
V
CC
120
CAS#
170
DM6
21
V
CC
71
NC
121
CS0#
171
DQ50
22
V
CC
72
NC
122
CS1#
172
DQ54
23
DQ9
73
NC
123
NC
173
V
SS
24
DQ13
74
NC
124
NC
174
V
SS
25
DQS1
75
V
SS
125
V
SS
175
DQ51
26
DM1
76
V
SS
126
V
SS
176
DQ55
27
V
SS
77
DNU
127
DQ32
177
DQ56
28
V
SS
78
DNU
128
DQ36
178
DQ60
29
DQ10
79
NC
129
DQ33
179
V
CC
30
DQ14
80
NC
130
DQ37
180
V
CC
31
DQ11
81
V
CC
131
V
CC
181
DQ57
32
DQ15
82
V
CC
132
V
CC
182
DQ61
33
V
CC
83
NC
133
DQS4
183
DQS7
34
V
CC
84
NC
134
DM4
184
DM7
35
CK0
85
NC
135
DQ34
185
V
SS
36
V
CC
86
NC
136
DQ38
186
V
SS
37
CK0#
87
V
SS
137
V
SS
187
DQ58
38
V
SS
88
V
SS
138
V
SS
188
DQ62
39
V
SS
89
CK2*
139
DQ35
189
DQ59
40
V
SS
90
V
SS
140
DQ39
190
DQ63
41
DQ16
91
CK2#*
141
DQ40
191
V
CC
42
DQ20
92
V
CC*
142
DQ44
192
V
CC
43
DQ17
93
V
CC
143
V
CC
193
SDA
44
DQ21
94
V
CC
144
V
CC
194
SA0
45
V
CC
95
CKE1
145
DQ41
195
SCL
46
V
CC
96
CKE0
146
DQ45
196
SA1
47
DQS2
97
NC
147
DQS5
197
V
CCSPD
48
DM2
98
NC
148
DM5
198
SA2
49
DQ18
99
A12
149
V
SS
199
NC
50
DQ22
100
A11
150
V
SS
200
NC
WV3EG232M64EFSU-D4
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
April 2005
Rev. 0
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
BA0, BA1
A0-A12
RAS#
BA0, BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
WE#: DDR SDRAMs
CAS#
WE#
CS0# CKE0
CS1# CKE1
V
REF
V
SS
DDR SDRAMs
DDR SDRAMs
V
CCSPD
V
CC
DDR SDRAMs
SPD
A0
SA0
SERIAL PD
SDA
A1
SA1
A2
SA2
WP
SCL
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM0
DQS0
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM4
DQS4
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM1
DQS1
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM5
DQS5
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM2
DQS2
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM6
DQS6
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM2
DQS2
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM7
DQS7
DM
S0#
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
CK0
CK0#
PLL
NOTE: 1.All resistor values are 22 unless otherwise specifi ed.
WV3EG232M64EFSU-D4
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
April 2005
Rev. 0
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
CC
supply relative to Vss
V
CC
-1.0 ~ 3.6
V
Voltage on V
CCQ
supply relative to Vss
V
CCQ
-0.5 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
16
W
Short circuit current
I
OS
50
mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
T
A
= 0C to 70C
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal V
CC
of 2.5V)
V
CC
2.3
2.7
v
I/O Supply voltage
V
CCQ
2.3
2.7
V
I/O Reference voltage
V
REF
V
CCQ
/2-50mV
V
CCQ
/2+50mV
V
1
I/O Termination voltage(system)
V
TT
V
REF
-0.04
V
REF
+0.04
V
2
Input logic high voltage
V
IH
(DC)
V
REF
+0.15
V
CCQ
+0.3
V
4
Input logic low voltage
V
IL
(DC)
-0.3
V
REF
-0.15
V
4
Input Voltage Level, CK and CK# inputs
V
IN
(DC)
-0.3
V
CCQ
+0.3
V
Input Differential Voltage, CK and CK# inputs
V
ID
(DC)
0.3
V
CCQ
+0.6
V
3
Input crossing point voltage, CK and CK# inputs
V
IX
(DC)
1.15
1.35
V
5
Input leakage current
I
I
-2
2
uA
Output leakage current
I
OZ
-5
5
uA
Output High Current(Normal strengh driver); V
OUT
= V
TT
+ 0.84V
I
OH
-16.8
mA
Output High Current(Normal strengh driver); V
OUT
= V
TT
- 0.84V
I
OL
16.8
mA
Output High Current(Half strengh driver); V
OUT
= V
TT
+ 0.45V
I
OH
-9
mA
Output High Current(Half strengh driver); V
OUT
= V
TT
- 0.45V
I
OL
9
mA
Notes:
1. Includes 25mV margin for DC offset on V
REF
, and a combined total of 50mV margin for all AC noise and DC offset on V
REF
, bandwidth limited to 20MHz. The DRAM must
accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled TO V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of 3nH.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
, and must track variations in the DC level of V
REF
.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK#.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifi cations are relative
to a V
REF
envelop that has been bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*V
CCQ
of the transmitting device and must track variations in the dc level of the same.
CAPACITANCE
V
CC
= 2.5, V
CCQ
= 2.5V, T
A
= 25 C, f = 1MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A12, BA0 ~ BA1,RAS#, CAS#, WE#)
C
IN1
38
47
pF
Input capacitance (CKE0,CKE1)
C
IN2
38
47
pF
Input capacitance ( CS0#, CS1#)
C
IN3
36
44
pF
Input capacitance ( CK0, CK0#)
C
IN4
36
40
pF
Input capacitance (DM0~DM7)
C
IN5
12
14
pF
Data & DQS input/output capacitance (DQ0~DQ63)
C
OUT1
12
14
pF
WV3EG232M64EFSU-D4
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
April 2005
Rev. 0
ADVANCED
I
DD
SPECIFICATIONS AND CONDITIONS
0C T
A
+70C; V
CC
, V
CCQ
= +2.5V 0.2V
PARAMETER/CONDITION
SYMBOL
MAX
UNITS
DDR333
@CL=2.5
DDR266
@CL=2
DDR266
@CL=2.5
Operating current One bank Active-Precharge; t
RC
= t
RC
(min); t
CK
= 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
I
DD0
1160
1000
1000
mA
Operating current One bank operation ; One bank open, BL=4, Reads -- Refer to the following
page for detailed test condition
I
DD1
1360
1200
1200
mA
Percharge power-down standby current; All banks idle; power-down mode; CKE V
IL
(max); t
CK
= 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; V
IN
= V
REF
for DQ, DQS and DM
I
DD2P
48
48
48
mA
Precharge Floating standby current; CS# V
IH
(min);All banks idle; CKE V
IH
(min); t
CK
=
100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs
changing once per clock cycle; V
IN
= V
REF
for DQ,DQS and DM
I
DD2F
400
320
320
mA
Precharge Quiet standby current; CS# V
IH
(min); All banks idle; CKE V
IH
(min); t
CK
= 100Mhz
for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with
keeping V
IH
(min) or V
IL
(max); V
IN
= V
REF
for DQ ,DQS and DM
I
DD2Q
320
290
290
mA
Active power - down standby current ; one bank active; power-down mode; CKE VIL (max);
t
CK
= 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; V
IN
= V
REF
for DQ, DQS and DM
I
DD3P
560
480
480
mA
Active standby current; CS# V
IH
(min); CKE V
IH
(min); one bank active; active - precharge;
t
RC
= t
RAS
(max); t
CK
= 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and
DM inputs changing twice per clock cycle; address and other control inputs changing once per
clock cycle
I
DD3N
880
720
720
mA
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active;
address and control inputs changing once per clock cycle; CL = 2 at t
CK
= 100Mhz for DDR200,
CL = 2 at t
CK
= 133Mhz for DDR266A, CL = 2.5 at t
CK
= 133Mhz for DDR266B ; 50% of data
changing at every burst; l
OUT
= 0mA
I
DD4R
1720
1480
1480
mA
Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active
address and control inputs changing once per clock cycle; CL = 2 at t
CK
= 100Mhz for DDR200,
CL = 2 at t
CK
= 133Mhz for DDR266A, CL = 2.5 at t
CK
= 133Mhz for DDR266B; DQ, DM and
DQS inputs changing twice per clock cycle, 50% of input data changing at every burst
I
DD4W
1720
1440
1440
mA
Auto refresh current; t
RC
= t
RFC
(min) - 8*t
CK
for DDR200 at 100Mhz, 10*t
CK
for DDR266A &
DDR266B at 133Mhz; distributed refresh
I
DD5
1800
1640
1640
mA
Self refresh current; CKE 0.2V; External clock should be on; t
CK
= 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B
I
DD6
48
48
48
mA
Orerating current - Four bank operation ; Four bank interleaving with BL=4
-- Refer to the following page for detailed test condition
I
DD7A
2680
2360
2360
mA
Note: I
DD
specifi cation is based on Samsung components. Other DRAM Manufacturers specifi cation may be different.
WV3EG232M64EFSU-D4
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
April 2005
Rev. 0
ADVANCED
AC OPERATIONG TEST CONDITIONS
V
CC
= 2.5V, V
CCQ
= 2.5V, 0c T
A
+70C
Parameter
Value
Unit
Input reference voltage for Clock
0.5 * V
CCQ
V
Input signal maximum peak swing
1.5
V
Input Levels(V
IH
/V
IL
)
V
REF
+0.31/V
REF
-0.31
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
TT
V
Output load condition
See Load Circuit
OUTPUT LOAD CIRCUIT)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
CCQ
R
T
=50
V
TT
=0.5*V
CCQ
WV3EG232M64EFSU-D4
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
April 2005
Rev. 0
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0C T
A
+70C; V
CC
= V
CCQ
= +2.5V 0.2V
AC Operating Test Conditions
Parameter
Symbol
335
262
265
Unit
Note
Min
Max
Min
Max
Min
Max
Row cycle time
t
RC
60
65
65
ns
Refresh row cycle time
t
RFC
72
75
75
ns
Row active time
t
RAS
42
70K
45
120K
45
120K
ns
RAS to CAS delay
t
RCD
18
20
20
ns
Row precharge time
t
RP
18
20
20
ns
Row active to Row active delay
t
RRD
12
15
15
ns
Write recovery time
t
WR
15
15
15
ns
Last data in to Read command
t
WTR
1
1
1
t
CK
Col. address to Col. address delay
t
CCD
1
1
1
t
CK
Clock cycle time
CL=2.0
t
CK
7.5
12
7.5
12
10
12
ns
5
CL=2.5
6
12
7.5
12
7.5
12
ns
5
Clock high level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
Clock low level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
DQS-out access time from CK/CK#
t
DQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK#
t
AC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
t
DQSQ
0.45
0.5
0.5
ns
5
Read Preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Read Postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
CK to valid DQS-in
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS-in setup time
t
WPRES
0
0
0
ns
2
DQS-in hold time
t
WPRE
0.25
0.25
0.25
t
CK
DQS falling edge to CK rising-setup time
t
DSS
0.2
0.2
0.2
t
CK
DQS falling edge from CK rising-hold time
t
DSH
0.2
0.2
0.2
t
CK
DQS-in high level width
t
DQSH
0.35
0.35
0.35
t
CK
DQS-in low level width
t
DQSL
0.35
0.35
0.35
t
CK
DQS-in cycle time
t
DSC
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Address and Control Input setup time(fast)
t
IS
0.75
0.9
0.9
ns
6
Address and Control Input hold time(fast)
t
IH
0.75
0.9
0.9
ns
6
Address and Control Input setup time(slow)
t
IS
0.8
1.0
1.0
ns
6
Address and Control Input hold time(slow)
t
IH
0.8
1.0
1.0
ns
6
Data-out high impedence time from CK/CK#
t
HZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data-out low impedence time from CK/CK#
t
LZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Input Slew Rate(for input only pins)
t
SL(I)
0.5
0.5
0.5
V/ns
6
Input Slew Rate(for I/O pins)
t
SL(IO)
0.5
0.5
0.5
V/ns
7
Output Slew Rate(x4,x8)
t
SL(O)
1.0
4.5
1.0
4.5
1.0
4.5
V/ns
Output Slew Rate Matching Ratio(rise to fall)
t
SLMR
0.67
1.5
0.67
1.5
0.67
1.5
AC Timing Parameters are based on Samsung components. Other DRAM Manufacturers parameters may be different.
WV3EG232M64EFSU-D4
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
April 2005
Rev. 0
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS (Continued)
0C T
A
70C, V
CC
= +2.5V 0.2V, V
CCQ
= +2.5V 0.2V
Parameter
Symbol
335
262
265
Unit
Note
Min
Max
Min
Max
Min
Max
Mode register set cycle time
t
MRD
12
15
15
ns
DQ & DM setup time to DQS
t
DS
0.45
0.5
0.5
ns
7
DQ & DM hold time to DQS
t
DH
0.45
0.5
0.5
ns
7
Control & Address input pulse width
t
IPW
2.2
2.2
2.2
ns
DQ & DM input pulse width
t
DIPW
1.75
1.75
1.75
ns
Power down exit time
t
PDEX
6
7.5
7.5
ns
Exit self refresh to non-Read command
t
XSNR
75
75
75
ns
4
Exit self refresh to read command
t
XSRD
200
200
200
t
CK
Refresh interval time
t
REFI
7.8
7.8
7.8
us
1
Output DQS valid window
t
QH
t
HP
-t
QHS
--
t
HP
-t
QHS
--
t
HP
-t
QHS
--
ns
5
Clock half period
t
HP
t
CLmin or
t
CHmin
--
t
CLmin or
t
CHmin
--
t
CLmin or
t
CHmin
--
ns
Data hold skew factor
t
QHS
0.55
0.75
0.75
ns
DQS write postamble time
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
3
Active to Read with Auto precharge command
t
RAP
18
20
20
Autoprecharge write recovery + Precharge
time
t
DAL
(t
WR
/t
CK
) +
(t
RP
/t
CK
)
(t
WR
/t
CK
) +
(t
RP
/t
CK
)
(t
WR
/t
CK
) +
(t
RP
/t
CK
)
t
CK
1. Maximum burst refresh cycle : 8
2. The specifi c requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were
previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on t
DQSS
.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade
accordingly.
4. A write command can be applied with t
RCD
satisfi ed after this command.
5. For registered DIMMs, t
CL
and t
CH
are 45% of the period including both the half period jitter (t
JIT(HP)
) of the PLL and the half period jitter due to crosstalk (t
JIT(crosstalk)
) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
t
IS
t
IH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+50
+50
0.3
+100
+100
This derating table is used to increase t
IS
/t
IH
in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate
and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
t
DS
t
DH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+75
+75
0.3
+150
+150
This derating table is used to increase t
DS
/t
DH
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate
and DC-DC slew rate.
WV3EG232M64EFSU-D4
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
April 2005
Rev. 0
ADVANCED
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
200-PIN DDR2 SODIMM DIMENSIONS
ORDERING INFORMATION FOR D4
Part Number
Speed
CAS Latency
t
RCD
t
RP
Height*
WV3EG232M64EFSU335D4xG
166MHz/333Mbps
2.5
3
3
31.75 (1.25") MAX
WV3EG232M64EFSU262D4xG
133MHz/266Mbps
2
2
2
31.75 (1.25") MAX
WV3EG232M64EFSU265D4xG
133MHz/266Mbps
2.5
3
3
31.75 (1.25") MAX
NOTES:
Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
3.80 (0.150)
MAX
1.10 (0.043)
Full R 2X
1
39
41
199
4.00 0.10
(0.16 0.039)
6.00
(0.24)
2.15
(0.086)
2.45
(0.098)
4.00 0.10
(0.16 0.0039)
1.00 0.1
(0.04 0.0039)
0.45 0.03
(0.018 0.001)
0.60
(0.024)
11.40
(0.456)
1.80 (0.07)
2.40 (0.096)
4.20 (0.17)
47.40
(1.896)
2- 1.80
(0.07)
31.75
(1.25)
20.00
(0.79)
63.60
(2.50)
67.60
(2.66)
2.55 Min
(0.102 Min)
0.25
(0.01)
WV3EG232M64EFSU-D4
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
April 2005
Rev. 0
ADVANCED
PART NUMBERING GUIDE
WV 3 E G 232M 64 E F S U xxx D4 x G
WEDC
MEMORY
DDR
GOLD
DEPTH (Dual Rank)
BUS WIDTH
x8
FBGA
2.5V
UNBUFFERED
SPEED (MHz)
PACKAGE 200 PIN
COMPONENT VENDOR
NAME
(M = MICRON)
(S = SAMSUNG)
RoHS COMPLIANT
WV3EG232M64EFSU-D4
11
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
April 2005
Rev. 0
ADVANCED
Document Title
512MB 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
4-05
Advanced
PDF 
ZIP