WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED*
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
1GB 2x64Mx72 DDR SDRAM REGISTERED, w/PLL
DESCRIPTION
The WV3EG264M72ESFR is a 2x64Mx72 Double Data
Rate DDR SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit with 4 banks DDR
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.
* This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
FEATURES
200-pin SO-DIMM, dual in-line memory module
Fast data transfer rates: PC2100 and PC2700
Utilizes 266 and 333 Mb/s DDR SDRAM
components
V
CC
= V
CCQ
= 2.5V 0.2V
Bidirectional data strobe (DQS) option
Differential clock inputs (CK and CK#)
DLL to align DQ and DQS transitions with CK
Programmable burst: length (2, 4, 8)
Programmable READ# latency (CL): 2 and 2.5
(clock)
Serial Presence Detect (SPD) with EEPROM
Auto and self refresh: 64ms/ 8,192 cycle refresh
Gold
edge
contacts
Dual
Rank
Package
option
200 Pin SO-DIMM
PCB 31.75mm (1.25") Max
OPERATING FREQUENCIES
DDR333@CL = 2.5
DDR266@CL = 2
DDR266@CL = 2.5
Clock Speed
166MHz
133MHz
133MHz
CL-t
RCD
-t
RP
2.5-3-3
2-2-2
2.5-3-3
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PIN NAMES
Pin Name
Function
A0-A12
Address Inputs
BA0, BA1
SDRAM Bank Address
DQ0-DQ63
Data Input/Output
CB0-CB7
Check Bits
DQS0-DQS8
Data strobes
CK0,CK0#
Clock inputs, positive/negative
CKE0, CKE1
Clock enable input
CS0#, CS1#
Chip select input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
V
CC
Core Power
V
CCQ
I/O Power
V
SS
Ground
SA0-SA2
EEPROM address
SDA
Serial Data Input/Output
V
REF
Input/Output Reference
DM0-DM8
Data-in mask
V
CCSPD
Serial EEPROM power supply
SCL
Serial Presence Detect(SPD) Clock Input
RESET#
Reset enable
NC
Spare pins, No connect
PIN CONFIGURATION
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
1
V
REF
51
V
SS
101
A9
151
DQ42
2
V
REF
52
V
SS
102
A8
152
DQ46
3
V
SS
53
DQ19
103
V
SS
153
DQ43
4
V
SS
54
DQ23
104
V
SS
154
DQ47
5
DQ0
55
DQ24
105
A7
155
V
CC
6
DQ4
56
DQ28
106
A6
156
V
CC
7
DQ1
57
V
CC
107
A5
157
V
CC
8
DQ5
58
V
CC
108
A4
158
NC
9
V
CC
59
DQ25
109
A3
159
V
SS
10
V
CC
60
DQ29
110
A2
160
NC
11
DQS0
61
DQS3
111
A1
161
V
SS
12
DM0
62
DM3
112
A0
162
V
SS
13
DQ2
63
V
SS
113
V
CC
163
DQ48
14
DQ6
64
V
SS
114
V
CC
164
DQ52
15
V
SS
65
DQ26
115
A10/AP
165
DQ49
16
V
SS
66
DQ30
116
BA1
166
DQ53
17
DQ3
67
DQ27
117
BA0
167
V
CC
18
DQ7
68
DQ31
118
RAS#
168
V
CC
19
DQ8
69
V
CC
119
WE#
169
DQS6
20
DQ12
70
V
CC
120
CAS#
170
DM6
21
V
CC
71
CB0
121
CS0#
171
DQ50
22
V
CC
72
CB4
122
CS1#
172
DQ54
23
DQ9
73
CB1
123
NC
173
V
SS
24
DQ13
74
CB5
124
NC
174
V
SS
25
DQS1
75
V
SS
125
V
SS
175
DQ51
26
DM1
76
V
SS
126
V
SS
176
DQ55
27
V
SS
77
DQS8
127
DQ32
177
DQ56
28
V
SS
78
DM8
128
DQ36
178
DQ60
29
DQ10
79
CB2
129
DQ33
179
V
CC
30
DQ14
80
CB6
130
DQ37
180
V
CC
31
DQ11
81
V
CC
131
V
CC
181
DQ57
32
DQ15
82
V
CC
132
V
CC
182
DQ61
33
V
CC
83
CB3
133
DQS4
183
DQS7
34
V
CC
84
CB7
134
DM4
184
DM7
35
CK0
85
NC
135
DQ34
185
V
SS
36
V
CC
86
RESET#
136
DQ38
186
V
SS
37
CK0#
87
V
SS
137
V
SS
187
DQ58
38
V
SS
88
V
SS
138
V
SS
188
DQ62
39
V
SS
89
NC
139
DQ35
189
DQ59
40
V
SS
90
V
SS
140
DQ39
190
DQ63
41
DQ16
91
NC
141
DQ40
191
V
CC
42
DQ20
92
V
CC
142
DQ44
192
V
CC
43
DQ17
93
V
CC
143
V
CC
193
SDA
44
DQ21
94
V
CC
144
V
CC
194
SA0
45
V
CC
95
CKE1
145
DQ41
195
SCL
46
V
CC
96
CKE0
146
DQ45
196
SA1
47
DQS2
97
NC
147
DQS5
197
V
CCSPD
48
DM2
98
NC
148
DM5
198
SA2
49
DQ18
99
A12
149
V
SS
199
NC
50
DQ22
100
A11
150
V
SS
200
NC
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
CS0#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
S0#
A0
Serial PD
A1
A2
SA1 SA2
SCL
SDA
WP
DM
DQS0
DM0
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S0#
DM
DQS4
DM4
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
S0#
DM
DQS1
DM1
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S0#
DM
DQS5
DM5
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS
S0#
DM
DQS2
DM2
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S0#
DM
DQS6
DM6
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
S0#
DM
DQS3
DM3
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S0#
DM
DQS7
DM7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CS1#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S1#
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S1#
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S1#
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S1#
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S1#
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S1#
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S1#
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS
S1#
DM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQS8
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DM8
CS# DQS
DM
CS# DQS
DM
DDR SDRAM X 2
120 Ohms
CK0#
PLL
CK0
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
REGISTER X 2
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
V
CCSPD
V
CCQ
/V
CC
V
REF
V
SS
SPD
CS0#
CS1#
BA0-BA1
A0-A12
RAS#
CAS#
CKE0
CKE1
WE#
BA0-BA1:
DDR SDRAMs
A0-A12:
DDR SDRAMs
RAS#:
DDR SDRAMs
CAS#:
DDR SDRAMs
CKE:
DDR SDRAMs
CKE:
DDR SDRAMs
WE#:
DDR SDRAMs
RCS0#
RCS1#
RBA0-RBA1
RA0-RA12
RRAS#
RCAS#
RCKE0
RCKE1
RWE#
PCK
PCK#
RESET#
R
E
G
I
S
T
E
R
NOTE: All resistor values are 22 ohms unless otherwise specifi ed.
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DC OPERATING CONDITIONS
0C T
A
70C
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage (for device with a nominal V
CC
of 2.5V)
V
CC
2.3
2.7
I/O Supply voltage
V
CCQ
2.3
2.7
V
I/O Reference voltage
V
REF
0.49*V
CCQ
0.51*V
CCQ
V
1
I/O Termination voltage (system)
V
TT
V
REF
-0.04
V
REF
+0.04
V
2
Input logic high voltage
V
IH
(DC)
V
REF
+0.15
V
CCQ
+0.3
V
4
Input logic low voltage
V
IL
(DC)
-0.3
V
REF
-0.15
V
4
Input Voltage Level, CK and CK# inputs
V
IN
(DC)
-0.3
V
CCQ
+0.3
V
Input Differential Voltage, CK and CK# inputs
V
ID
(DC)
0.3
V
CCQ
+0.6
V
3
Input leakage current
I
I
-2
2
uA
Output leakage current
I
OZ
-5
5
uA
Output High Current(Normal strengh driver); V
OUT
= V
TT
+ 0.84V
I
OH
-16.8
mA
Output High Current(Normal strengh driver); V
OUT
= V
TT
- 0.84V
I
OL
16.8
mA
Output High Current(Half strengh driver); V
OUT
= V
TT
+ 0.45V
I
OH
-9
mA
Output High Current(Half strengh driver); V
OUT
= V
TT
- 0.45V
I
OL
9
mA
Notes:
1. Includes 25mV margin for DC offset on V
REF
, and a combined total of 50mV margin for all AC noise and DC offset on V
REF
, bandwidth limited to 20MHz. The DRAM must
accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled to V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of 3nH.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK#.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifi cations are relative
to a V
REF
envelop that has been bandwidth limited to 200MHz.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.3
V
Voltage on V
CC
& V
CCQ
pin relative to V
SS
V
CC
, V
CCQ
-1.0 ~ 3.6
V
Storage Temperature
T
STG
-55 ~ +150
C
Operating Temperature
T
A
0 ~ +70
C
Power dissipation 1GB single mezzanine memory
P
D
18
W
Short circuit current
I
OS
50
mA
NOTE:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
CAPACITANCE
V
CC
2.5V, V
CCQ
= 2.5V 0.2V, T
A
= 25C, f = 1MHz
Parameter
Symbol
Min
Max
Units
Input capacitance (A0 ~ A12, BA0 ~ BA1,RAS#,CAS#, WE# )
C
IN1
9
11
pF
Input capacitance (CKE0, CKE1)
C
IN2
9
11
pF
Input capacitance ( CS0#, CS1#)
C
IN3
9
11
pF
Input capacitance ( CLK0, CLK0#)
C
IN4
11
12
pF
Input capacitance ( DM0 ~ DM8)
C
IN5
10
11
pF
Data & DQS input/output capacitance (DQ0~DQ63)
C
OUT1
10
11
pF
Data input/output capacitance (CB0 ~ CB7)
C
OUT2
10
11
pF
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DDR I
DD
SPECIFICATIONS AND CONDITIONS
0C T
CASE
< +70C; V
CCQ
= +2.5V 0.2V, V
CC
= +2.5V 0.2V
Symbol
Conditions
335
262
265
Unit
I
DD0
Operating current - One bank Active-Precharge;
t
RC
= t
RC
(min); t
CK
= 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DM and DQS
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
1,215
1,215
1,080
mA
I
DD1
Operating current - One bank operation;
One bank open, BL = 4, Reads - Refer to the following page for detailed test condition
1,485
1,485
1,350
mA
I
DD2P
Percharge power-down standby current;
All banks idle; power - down mode; CKE = <V
IL
(max); t
CK
= 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B; V
IN
= V
REF
for DQ, DQS and DM
90
90
90
mA
I
DD2F
Precharge Floating standby current;
CS# > = V
IH
(min);All banks idle; CKE > = V
IH
(min); t
CK
= 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B; Address and other control inputs changing once per clock cycle;
V
IN
= V
REF
for DQ, DQS and DM
810
810
720
mA
I
DD3P
Active power - down standby current;
one bank active; power-down mode; CKE = < V
IL
(max); t
CK
= 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B; V
IN
= V
REF
for DQ, DQS and DM
630
630
540
mA
I
DD3N
Active standby current;
CS# > = V
IH
(min); CKE> = V
IH
(min); one bank active; active - precharge; t
RC
= t
RAS
max; t
CK
=
100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing
twice per clock cycle; address and other control inputs changing once per clock cycle
900
900
810
mA
I
DD4R
Operating current - burst read;
Burst length = 2; reads; continguous burst; One bank active; address and control inputs
changing once per clock cycle; CL = 2 at t
CK
= 100Mhz for DDR200, CL = 2 at t
CK
= 133Mhz for
DDR266A, CL = 2.5 at t
CK
= 133Mhz for DDR266B ; 50% of data changing at every burst;
l
OUT
= 0 m A
1.530
1.530
1,350
mA
I
DD4W
Operating current - burst write;
Burst length = 2; writes; continuous burst; One bank active address and control inputs
changing once per clock cycle; CL = 2 at t
CK
= 100Mhz for DDR200, CL = 2 at t
CK
= 133Mhz for
DDR266A, CL = 2.5 at t
CK
= 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every burst
1,440
1,440
1,260
mA
I
DD5
Auto refresh current;
t
RC
= t
RFC
(min) - 8*t
CK
for DDR200 at 100Mhz, 10*t
CK
for DDR266A & DDR266B at 133Mhz;
distributed refresh
5,220
5,220
5,040
mA
I
DD6
Self refresh current;
CKE = < 0.2V; External clock should be on; t
CK
= 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B
90
90
90
mA
I
DD7A
Orerating current - Four bank operation;
Four bank interleaving with BL = 4 -Refer to the following page for detailed test condition
3,690
3,645
3,195
mA
Typical case: V
CC
= 2.5V, T = 25C
Worst case: V
CC
= 2.7V, T = 10C
Note: I
DD
specifi cations are based on Micron components. Other DRAM manufacturers specifi caitons may be different.
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS
0C T
CASE
< +70C; V
CCQ
= +2.5V 0.2V, V
CC
= +2.5V 0.2V
Parameter
Symbol
335
262
265
Unit
Min
Max
Min
Max
Min
Max
Row cycle time
t
RC
60
65
65
ns
Refresh row cycle time
t
RFC
72
75
75
ns
Row active time
t
RAS
42
70K
45
120K
45
120K
ns
RAS# to CAS# delay
t
RCD
18
20
20
ns
Row precharge time
t
RP
18
20
20
ns
Row active to Row active
t
RRD
12
15
15
ns
Write recovery time
t
WR
15
15
15
ns
Last data in to Read command
t
WTR
1
1
1
t
CK
Col. address to Col. address
t
CCD
1
1
1
t
CK
Clock cycle time
CL=2.0
t
CK
7.5
12
7.5
12
10
12
ns
CL=2.5
6
12
7.5
12
7.5
12
ns
Clock high level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
Clock low level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
DQS-out access time from
t
DQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time
t
AC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput
t
DQSQ
--
0.4
--
0.5
--
0.5
ns
Read Preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Read Postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
CK to valid DQS-in
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS-in setup time
t
WPRE
0
0
0
ns
DQS-in hold time
t
WPRE
0.25
0.25
0.25
t
CK
DQS falling edge to CK ris-
t
DSS
0.2
0.2
0.2
t
CK
DQS falling edge from CK
t
DSH
0.2
0.2
0.2
t
CK
DQS-in high level width
t
DQSH
0.35
0.35
0.35
t
CK
DQS-in low level width
t
DQSL
0.35
0.35
0.35
t
CK
DQS-in cycle time
t
DSC
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Address and Control Input
t
IS
0.75
0.9
0.9
ns
Address and Control Input
t
IH
0.75
0.9
0.9
ns
Address and Control Input
t
IS
0.8
1.0
1.0
ns
Address and Control Input
t
IH
0.8
1.0
1.0
ns
Data-out high impedence time from CK/CK#
t
HZ
+0.7
+0.75
+0.75
ns
Data-out low impedence time from CK/CK#
t
LZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Input Slew Rate (for input)
t
SL(I)
0.5
0.5
0.5
V/ns
Input Slew Rate (for I/O pins)
t
SL(IO)
0.5
0.5
0.5
V/ns
Output Slew Rate (x4,x8)
Output Slew Rate Matching
t
SL(O)
1.0
4.5
1.0
4.5
1.0
4.5
V/ns
t
SLMR
0.67
1.5
0.67
1.5
0.67
1.5
Note: AC specifi cations are based on Micron components. Other DRAM manufacturers specifi caitons may be different.
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
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AC TIMING PARAMETERS
0C T
CASE
< +70C; V
CCQ
= +2.5V 0.2V, V
CC
= +2.5V 0.2V
Parameter
Symbol
335
262
265
Unit
Min
Max
Min
Max
Min
Max
Mode register set cycle time
t
MRD
12
15
15
ns
DQ & DM setup time to DQS
t
DS
0.45
0.5
0.5
ns
DQ & DM hold time to DQS
t
DH
0.45
0.5
0.5
ns
Control & Address input
t
IPW
2.2
2.2
2.2
ns
DQ & DM input pulse width
t
DIPW
1.75
1.75
1.75
ns
Power down exit time
t
PDEX
6
7.5
7.5
ns
Exit self refresh to non-Read
t
XSNR
75
75
75
ns
Exit self refresh to read command
t
XSRD
200
200
200
tCK
Refresh interval time
t
REFI
7.8
7.8
7.8
us
Output DQS valid window
t
QH
t
HP
-t
QHS
--
t
HP
-t
QHS
--
t
HP
-t
QHS
--
ns
Clock half period
t
HP
t
CL
min or
t
CH
min
--
t
CL
min or
t
CH
min
--
t
CL
min or
t
CH
min
--
ns
Data hold skew factor
t
QHS
0.5
0.75
0.75
ns
DQS write postamble time
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
Active to Read with Auto precharge
command
t
RAP
15
15
20
Autoprecharge write recovery +
Precharge time
t
DAL
(t
WR
/t
CK
) +
(t
RP
/t
CK
)
(t
WR
/t
CK
) +
(t
RP
/t
CK
)
(t
WR
/t
CK
) +
(t
RP
/t
CK
)
t
CK
Note: AC specifi cations are based on Micron components. Other DRAM manufacturers specifi caitons may be different.
SERIAL PRESENT DETECT INFORMATION
Byte #
Function described
Function Supported
Hex value
265
262
335
265
262
335
0
Defi nes # of Bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of Bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM DDR
07h
3
# of row address on this assembly
13
0Dh
4
# of column address on this assembly
11
0Bh
5
# of module Rows on this assembly
2 Row
02h
6
Data width of this assembly
64 bits
48h
7
Data width of this assembly
--
00h
8
VDDQ and interface standard of this assembly
SSTL 2.5V
04h
9
DDR SDRAM cycle time at CAS Latency =2.5
7.5ns
7ns
6ns
75h
70h
60h
10
DDR SDRAM Access time from clock at CL=2.5
0.75
0.75
0.7
75h
75h
70h
11
DIMM confi guration type(Non-parity, Parity, ECC)
ECC
02h
12
Refresh rate & type
7.8us & Self refresh
82h
WV3EG264M72ESFR-D4
August 2005
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SERIAL PRESENT DETECT INFORMATION (cont'd)
Byte #
Function described
Function Supported
Hex value
265
262
335
265
262
335
13
Primary DDR SDRAM width
x8
08h
14
Error checking DDR SDRAM data width
x8
08h
15
Minimum clock delay for back-to-back random column address
t
CCD
= 1
CLK
01h
16
DDR SDRAM device attributes: Burst lengths supported
2,4,8
0Eh
17
DDR SDRAM device attributes: # of banks on each DDR SDRAM
4 banks
04h
18
DDR SDRAM device attributes: CAS Latency supported
2,2.5
0Ch
19
DDR SDRAM device attributes: CS Latency
0CLK
01h
20
DDR SDRAM device attributes: WE Latency
1CLK
02h
21
DDR SDRAM module attributes
Registered address & control inputs
and On-card DLL
26h
22
DDR SDRAM device attributes: General
+/-0.2V voltage tolerance
C0h
23
DDR SDRAM cycle time at CL =2
10ns
7.5ns
7.5ns
A0h
75h
75h
24
DDR SDRAM Access time from clock at CL =2
0.75
0.75
0.7
75h
75h
70h
25
DDR SDRAM cycle time at CL =1.5
--
--
--
00h
26
DDR SDRAM Access time from clock at CL =1.5
--
--
--
00h
27
Minimum row precharge time (=t
RP
)
20ns
20ns
18ns
50h
50h
48h
28
Minimum row activate to row active delay (=t
RRD
)
15ns
15ns
12ns
3Ch
3Ch
30h
29
Minimum RAS to CAS delay (=t
RCD
)
20ns
20ns
18ns
50h
50h
48h
30
Minimum active to precharge time (=t
RAS
)
45ns
45ns
42ns
2Dh
2Dh
2Ah
31
Module ROW density
512MB
80h
32
Command and address signal input setup time
0.9ns
0.9ns
0.8ns
A0h
A0h
80h
33
Command and address signal input hold time
0.9ns
0.9ns
0.8ns
A0h
A0h
80h
34
Data signal input setup time
0.5ns
0.5ns
0.45ns
50h
50h
45h
35
Data signal input hold time
0.5ns
0.5ns
0.45ns
50h
50h
45h
36-40
Superset information (may be used in future)
--
00h
41
DDR SDRAM Minimum Active to Active/Auto Refresh Time (t
RC
)
65ns
65ns
60ns
41h
41h
3Ch
42
DDR SDRAM Minimim Auto-Refresh to Active/Auto-Refresh
Commmand Period (t
RFC
)
75ns
75ns
72ns
4Bh
4Bh
48h
43
DDR SDRAM Maximum Device Cycle Time (t
CK
max)
13ns
13ns
12ns
34h
34h
30h
44
DDR SDRAM DQS-DQ Skew for DQS and associated DQ signals
(t
DQSQmax
)
0.50ns
0.50ns
0.45ns
50h
50h
45h
45
DDR SDRAM Read Data Hold Skew Factor (t
QHS
)
0.75ns
0.75ns
0.50ns
75h
75h
50h
46
Reserved
00
00
00
00h
00h
00h
47
DIMM Height
Standard/Low profi le
01h
48-61
Superset information (may be used in future)
--
00h
62
SPD data revision code
Initial release
10h
63
Checksum for Bytes 0 ~ 62
--
69h
39h
6Fh
64 - 127
Manufacturer INFO
--
00h
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
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White Electronic Designs
67.60
(2.661)
63.60
(2.504)
1.0 0.1
(0.04 0.0039)
3.80
(0.150) MAX.
2.15
(0.085)
6.0
0.236
4.20 (0.165)
1.8
(0.071)
4.00
(0.158) MIN.
47.40
(1.866)
2- 1.80
(0.071)
11.40
(0.449)
1
39
41
199
31.75
(1.25)
Full R 2x
2.40 (0.094)
4.00 0.10
(0.158 0.039)
20
(0.787)
2.45
(0.098)
4.00 0.10
(0.158 0.039)
1.00 0.1
(0.04 0.0039)
0.45 0.03
(0.018 0.001)
0.60
(0.024)
2.55 Min
(0.102 Min)
0.25
(0.01)
PACKAGE DIMENSIONS FOR D4
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
Tolerances: 0.15 (0.006) unless otherwise specifi ed
ORDERING INFORMATION FOR D4
Part Number
Speed
CAS Latency
t
RCD
t
RP
Height*
WV3EG264M72ESFR335D4-x
166MHz/333Mb/s
2.5
3
3
31.75mm (1.25")
WV3EG264M72ESFR262D4-x
133MHz/266Mb/s
2
2
2
31.75mm (1.25")
WV3EG264M72ESFR265D4-x
133MHz/266Mb/s
2.5
3
3
31.75mm (1.25")
NOTES:
Consult Factory for availability of RoHS compliant products. ("G" = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "-x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualifi ed sourcing options.
(M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PART NUMBERING GUIDE
WV 3 E G 264M 72 E S F R xxx D4 -x G
WEDC
MEMORY
DDR 2
GOLD
DEPTH (Dual Rank)
BUS WIDTH
x8
2.5V
FBGA
REGISTERED
SPEED (MHz)
PACKAGE 200 PIN SO-DIMM
COMPONENT VENDOR
NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
11
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
Document Title
1GB 2x64Mx72 DDR SDRAM REGISTERED, w/PLL
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
August 2005
Advanced
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