1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
May 2006
Rev. 0
ADVANCED*
WV3EG265M72EFSU-D4
White Electronic Designs
1GB 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA
FEATURES
Unbuffered 200-pin (SO-DIMM), small-outline, dual-
in-line module
Fast data transfer rate: PC-2100, and PC-2700
Clock speeds of 133MHz, and 166MHz
Supports ECC error detection and correction
V
CC
= V
CCQ
= +2.5V 0.2V(133 and 166MHz)
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency: DDR 266 (2, 2.5
clock), DDR333 (2.5 clock)
Programmable Burst Length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh, 7.8s refresh interval
(8K/64ms refresh)
Serial presence detect (SPD) with EEPROM
Dual
Rank
Leaded & lead-free/RoHS compliant
Gold edge contacts
JEDEC standard 200 pin, small-outline, SO-DIMM
package
PCB height option:
31.75 mm (1.25")
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
DESCRIPTION
The WV3EG265M72EFSU is a 2x64Mx72 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM components. The module consists of eighteen
64Mx8 DDR SDRAMs in FBGA packages mounted on a
200 pin FR4 substrate.
* This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
OPERATING FREQUENCIES
DDR333@CL=2.5
DDR266@CL=2
DDR266@CL=2.5
Clock Speed
166MHz
133MHz
133MHz
CL-t
RCD
-t
RP
2.5-3-3
2-2-2
2.5-3-3
WV3EG265M72EFSU-D4
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
PIN NAMES
Symbol
Description
A0-A12
Address input
BA0, BA1
Bank Address
DQ0-DQ63
Data Input/Output
CB0-CB7
Check Bits
DQS0-DQS8
Data Strobe
CK0, CK0#
Clock Input
CKE0-CKE1
Clock Enable Input
CS0#-CS1#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Input
WE#
Write Enable
DM0-DM8
Data Write Mask
V
CC
Power Supply
V
SS
Ground
V
REF
SSTL_2 reference voltage
V
CCSPD
Serial EEPROM Positive Power
Supply
SDA
Input/Output: Serial Presence-
Detect Data
SCL
Serial Clock
SA0-SA2
Presence Detect Address Input
NC
No Connect
PIN CONFIGURATION
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
1
V
REF
51
V
SS
101
A9
151
DQ42
2
V
REF
52
V
SS
102
A8
152
DQ46
3
V
SS
53
DQ19
103
V
SS
153
DQ43
4
V
SS
54
DQ23
104
V
SS
154
DQ47
5
DQ0
55
DQ24
105
A7
155
V
CC
6
DQ4
56
DQ28
106
A6
156
V
CC
7
DQ1
57
V
CC
107
A5
157
V
CC
8
DQ5
58
V
CC
108
A4
158
NC
9
V
CC
59
DQ25
109
A3
159
V
SS
10
V
CC
60
DQ29
110
A2
160
NC
11
DQS0
61
DQS3
111
A1
161
V
SS
12
DM0
62
DM3
112
A0
162
V
SS
13
DQ2
63
V
SS
113
V
CC
163
DQ48
14
DQ6
64
V
SS
114
V
CC
164
DQ52
15
V
SS
65
DQ26
115
A10
165
DQ49
16
V
SS
66
DQ30
116
BA1
166
DQ53
17
DQ3
67
DQ27
117
BA0
167
V
CC
18
DQ7
68
DQ31
118
RAS#
168
V
CC
19
DQ8
69
V
CC
119
WE#
169
DQS6
20
DQ12
70
V
CC
120
CAS#
170
DM6
21
V
CC
71
CB0
121
CS0#
171
DQ50
22
V
CC
72
CB4
122
CS1#
172
DQ54
23
DQ9
73
CB1
123
NC
173
V
SS
24
DQ13
74
CB5
124
NC
174
V
SS
25
DQS1
75
V
SS
125
V
SS
175
DQ51
26
DM1
76
V
SS
126
V
SS
176
DQ55
27
V
SS
77
DQS8
127
DQ32
177
DQ56
28
V
SS
78
DM8
128
DQ36
178
DQ60
29
DQ10
79
CB2
129
DQ33
179
V
CC
30
DQ14
80
CB6
130
DQ37
180
V
CC
31
DQ11
81
V
CC
131
V
CC
181
DQ57
32
DQ15
82
V
CC
132
V
CC
182
DQ61
33
V
CC
83
CB3
133
DQS4
183
DQS7
34
V
CC
84
CB7
134
DM4
184
DM7
35
CK0
85
NC
135
DQ34
185
V
SS
36
V
CC
86
NC
136
DQ38
186
V
SS
37
CK0#
87
V
SS
137
V
SS
187
DQ58
38
V
SS
88
V
SS
138
V
SS
188
DQ62
39
V
SS
89
NC
139
DQ35
189
DQ59
40
V
SS
90
V
SS
140
DQ39
190
DQ63
41
DQ16
91
NC
141
DQ40
191
V
CC
42
DQ20
92
V
CC
142
DQ44
192
V
CC
43
DQ17
93
V
CC
143
V
CC
193
SDA
44
DQ21
94
V
CC
144
V
CC
194
SA0
45
V
CC
95
CKE1
145
DQ41
195
SCL
46
V
CC
96
CKE0
146
DQ45
196
SA1
47
DQS2
97
NC
147
DQS5
197
V
CCSPD
48
DM2
98
NC
148
DM5
198
SA2
49
DQ18
99
A12
149
V
SS
199
NC
50
DQ22
100
A11
150
V
SS
200
NC
WV3EG265M72EFSU-D4
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
A0
SA0
SERIAL PD
SDA
A1
SA1
A2
SA2
BA0, BA1
A0-A12
RAS#
BA0, BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE0: DDR SDRAMs
CKE1: DDR SDRAMs
WE#: DDR SDRAMs
CAS#
CKE0
CKE1
WE#
V
REF
V
SS
DDR SDRAMs
DDR SDRAMs
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM0
CS0#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
WP
SCL
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS1#
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQS0
DM7
DQS7
DM1
DQS1
DM6
DQS6
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DM2
DQS2
DM5
DQS5
DM CS# DQS
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQ
DM3
DQS3
DM4
DQS4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
V
CCSPD
V
CC
DDR SDRAMs
SPD/EEPROM
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM8
DQS8
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
PLL
CK0
CK0#
120
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
NOTE: All resistor values are 22 5% unless otherwise specifi ed.
WV3EG265M72EFSU-D4
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
DC ELECTRICAL CHARACTERISTICS
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Notes
Supply Voltage DRR266/DDR333 (nominal V
CC
2.5V)
V
CC
2.3
2.7
V
I/O Supply Voltage DRR266/DDR333 (nominal V
CC
2.5V
V
CCQ
2.3
2.7
V
I/O Reference Voltage
V
REF
0.49 V
CC
0.51 V
CC
V
1
I/O Termination Voltage
V
TT
V
REF
- 0.04
V
REF
+ 0.04
V
2
Input Logic High Voltage
V
IH(DC)
V
REF
+ 0.15
V
CC
+ 0.30
V
Input Logic Low Voltage
V
IL(DC)
-0.3
V
REF
- 0.15
V
Input voltage level, CK and CK#
V
IN(DC)
-0.3
V
REF
+ 0.30
V
Input differential voltage, CK and CK#
V
ID(DC)
0.3
V
REF
+ 0.60
V
3
Input crossing point voltage, CK and CK#
V
IX(DC)
0.3
V
REF
- 0.60
V
Input leakage current
Addr CAS#,
RAS#, WE#
I
I
-36
36
A
CS#, CKE
-18
18
A
CK, CK#
-10
10
A
DM
-4
4
A
Output leakage current
I
OZ
-10
10
A
Output high current (normal strength) V
OUT
= v +0.84V
I
OH
-16.8
mA
Output high current (normal strength) V
OUT
= V
TT
- 0.84V
I
OL
16.8
mA
Output high current (half strength) V
OUT
= V
TT
- 0.45V
I
OH
-9
mA
Output high current (half strength) V
OUT
= V
TT
- 0.45V
I
OL
9
mA
Notes:
1 V
REF
is expected to equal to 0.5*V
CCQ
of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V
REF
may not exceed +/-2 percent of the
DC value.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level of CK#.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Units
V
IN
, V
OUT
Voltage on V
CC
pin relative to V
SS
-0.5 ~ 3.6
V
V
CC
, V
CCQ
Voltage on V
CC
& V
CCQ
supply relative to V
SS
-1.0 ~ 3.6
V
V
REF
Voltage of V
REF
supply relative to V
SS
-1.0 ~ 3.6
V
T
STG
Storage Temperature
-55 ~ +150
C
T
A
Operating temperature
0 ~ 70
C
P
D
Power dissipation
18
W
I
OS
Short circuit output current
50
mA
Notes:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceed.
Functional ioeration should be restricted to recommended operation conditions.
Exposing to higher than recommended voltage for extended periods of time could affect device reliability.
WV3EG265M72EFSU-D4
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
INPUT/OUTPUT CAPACITANCE
TA=25C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A12, BA0~BA1, RAS#, CAS#, WE#)
C
IN
1
31
49
pF
Input capacitance (CKE0, CKE1)
C
IN
2
17.5
26.5
pF
Input capacitance (CS0# - CS1#)
C
IN
3
17.5
26.5
pF
Input capacitance (CLK0, CLK0#)
C
IN
4
6
7.5
pF
Input capacitance (DM0~DM8)
C
IN
5
11
13
pF
Input capacitance (DQ0~DQ63), (CB0~CB7)
C
OUT
1
11
13
pF
AC OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage
V
IH
(AC)
V
REF
+ 0.31
-
V
AC Input High (Logic 0) Voltage
V
IL
(AC)
-
V
REF
- 0.31
V
Input Differential Voltafe, CK and CK# inputs
V
ID
(AC)
0.7
V
CC
+ 0.6
V
Input Crossing Point Voltage, CK and CK# input
VIX(AC)
0.5*V
CC
- 0.2
0.5*V
CC
+ 0.2
V
WV3EG265M72EFSU-D4
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
I
CC
SPECIFICATIONS AND CONDITIONS
V
CC
, V
CCQ
= +2.5V 0.2V
SYM
PARAMETER/CONDITION
MAX
UNITS
DDR333
@CL=2.5
DDR266
@CL=2
DDR266
@CL=2.5
I
CC0*
OPERATING CURRENT: One device bank; Active-Precharge; t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN);
DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
1,270
1,180
1,180
mA
I
CC1*
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; t
RC
= t
RC
(MIN);
t
CK
= t
CK
(MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
1,540
1,450
1,450
mA
I
CC2P**
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
mode; t
CK
= t
CK
(MIN); CKE = (LOW)
370
370
370
mA
I
CC2F**
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; t
CK
= t
CK
(MIN); CKE =
HIGH; Address and other control inputs changing once per clock cycle. VI
N
= V
REF
for DQ,
DQS, and DM
820
820
820
mA
I
CC3P**
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode;
t
CK
= t
CK
(MIN); CKE = LOW
820
820
820
mA
I
CC3N**
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; t
RC
= t
RAS
(MAX); t
CK
= t
CK
(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
1,090
1,090
1,090
mA
I
CC4R*
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); I
OUT
= 0mA
1,585
1,450
1,450
mA
I
CC4W*
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); DQ, DM, and DQS
inputs changing twice per clock cycle
1,675
1,495
1,495
mA
I
CC5**
AUTO REFRESH BURST CURRENT:
t
REFC
= t
RFC
(MIN)
3,970
3,790
3,790
mA
I
CC6**
SELF REFRESH CURRENT: CKE 0.2V
370
370
370
mA
I
CC7*
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto
precharge, t
RC
= minimum t
RC
allowed; t
CK
= t
CK
(MIN); Address and control inputs change only
during Active READ, or WRITE commands
3,565
3,250
3,250
mA
Note: I
CC
specifi cation is based on SAMSUNG components. Other DRAM Manufacturers specifi cation may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in I
CC2P
(CKE LOW) mode.
**: Value calculated refl ects all module ranks in this operating condition.
WV3EG265M72EFSU-D4
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
V
CC
= V
CCQ
= +2.5V 0.2V
AC CHARACTERISTICS
335
262
265
UNITS
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
Row cycle time
tRC
60
65
65
t
CK
Refresh row cycle time
tRFC
72
75
75
ps
Row active
tRAS
42
70K
45
120K
45
120K
ps
RAS# to CAS# delay
tRCD
18
20
20
t
CK
Row precharge time
tRP
18
20
20
ns
Row active to row active delay
tRRD
12
15
15
ns
Write recovery time
tWR
15
15
15
ns
Last data in to READ command
tWTR
1
1
1
ns
Clock cycle time
CL = 2.5
t
CK (2.5)
6
12
7.5
12
7.5
12
ns
CL =2
t
CK (2)
7.5
12
7.5
12
10
12
ns
Clock high level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
Clock low level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
DQS-out access time from CK/CK#
t
DQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK#
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data stobe edge to output data edge
t
DQSQ
0.45
0.5
0.5
ns
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
CK to vaild DQS-in
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS-in setup time
tWPRES
0
0
0
ns
DQS-in hold time
tWPRE
0.25
0.25
0.25
t
CK
DQS falling edge to CK rising-setup time
t
DSS
0.2
0.2
0.2
t
CK
DQS falling edge to CK rising-hold time
tDHS
0.2
0.2
0.2
t
CK
DQS-in high level width
tDQHS
0.35
0.35
0.35
t
CK
DQS-in low level width
TDQSL
0.35
0.35
0.35
t
CK
Address and control input setup time (fast)
tISF
0.75
0.9
0.9
ns
Address and control input hold time (fast)
tIHF
0.75
0.9
0.9
ns
Address and control input setup time (slow)
tISS
0.8
1.0
1.0
ns
Address and control input hold time (slow)
tIHS
0.8
1.0
1.0
ns
Data-out high impedance time from CK/CK#
tHZ
-0.70
+0.70
-0.75
+0.75
-0.75
+0.75
ns
Data-out low impedance time to CK/CK#
tLZ
-0.70
+0.70
-0.75
+0.75
-0.75
+0.75
ns
Mode register set cycle
tMRD
12
15
15
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
0.5
ns
DQ & DM hold time to DQS
tDH
0.45
0.5
0.5
ns
Control & address input pulse width
tIPW
2.2
2.2
2.2
ns
DQ & DM input pulse width
tDIPW
1.75
1.75
1.75
ns
Exit self refresh to non-read command
tXSNR
75
75
75
ns
* AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.
Continued on next page
WV3EG265M72EFSU-D4
8
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White Electronic Designs
May 2006
Rev. 0
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
V
CC
= V
CCQ
= +2.5V 0.2V
AC CHARACTERISTICS
335
262
265
UNITS
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
Exit self regresh to read command
t
XSRD
200
200
200
t
CK
Refresh interval time
t
REFI
7.8
7.8
7.8
s
Output DQS vaild window
t
QH
t
HP
-t
QHS
t
HP
-t
QHS
t
HP
-t
QHS
ns
Clock half period
t
HP
t
CLmin or
t
CHmin
t
CLmin or
t
CHmin
t
CLmin or
t
CHmin
ns
Data hold skew factor
t
QHS
0.55
0.75
0.75
ns
DQS write postamble
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
ns
Active Read with auto precharge command
t
RAP
18
20
20
ns
Auto precharge Write recovery + Precharge time
t
RAL
t
WR
/t
CK
+
t
RP
/t
CK
t
WR
/t
CK
+
t
RP
/t
CK
t
WR
/t
CK
+
t
RP
/t
CK
t
CK
* AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
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ADVANCED
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
200-PIN DDR SO-DIMM DIMENSIONS
ORDERING INFORMATION FOR D4
Part Number
Speed
CAS Latency
t
RCD
t
RP
Height*
WV3EG265M72EFSU335D4xxx
166MHz/333Mbps
2.5
3
3
31.75 (1.25") MAX
WV3EG265M72EFSU262D4xxx
133MHz/266Mbps
2
2
2
31.75 (1.25") MAX
WV3EG265M72EFSU265D4xxx
133MHz/266Mbps
2.5
3
3
31.75 (1.25") MAX
NOTES:
Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
3.80 (0.150 )
MAX
1.10 (0.043)
0.90 (0.035)
PIN 1
67.75 (2.667)
67.45 (2.656)
20.00 (0.787)
TYP
1.80 (0.071)
(2X)
0.60 (0.024)
TYP
0.45 (0.018)
TYP
4.10 (0.161) 2X
3.90 (0.154)
PIN 199
PIN 200
PIN 2
FRONT VIEW
2.15 (0.085
6.00 (0.236)
63.60 (2.504)
47.40 (1.866) TYP
4.2 (0.165) TYP
11.40 (0.449) TYP
2.55 (1.00)
1.00 (0.039)
TYP
31.90 (1.256)
31.60 (1.244)
TYP
BACK VIEW
WV3EG265M72EFSU-D4
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
PART NUMBERING GUIDE
WV 3 E G 2 65M 72 E F S U xxx D4 x x x
WEDC
MEMORY (SDRAM)
DDR
GOLD
DUAL RANK
DEPTH (x64 "5"indicates with PLL)
BUS WIDTH
COMPONENT WIDTH x8
FBGA
2.5V
UNBUFFERED
SPEED (Mb/s)
PACKAGE 200 PIN
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M
=
MICRON)
(S
=
SAMSUNG)
(N = NANYA)
G = RoHS COMPLIANT
(Add "G" for RoHS,leave
"blank" for leaded)
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
Document Title
1GB 2x64Mx72 DDR SDRAM, UNBUFFERED, with PLL, FBGA
DRAM DIE OPTIONS:
SAMSUNG: C-Die
MICRON: T27Z: D-Die, will move to T37Z:F Q2'06
NANYA: B-Die
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
May 2006
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