White Electronic Designs
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
ADVANCED*
July 2005
Rev. 0
WV3EG32M64ETSU-D3
FEATURES
Double-data-rate architecture
PC2700 @ CL 2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply:
V
CC
= V
CCQ
= +2.5V 0.2V
184 pin DIMM package
D3 PCB height: 28.58mm (1.125")
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
DESCRIPTION
The WV3EG32M64ETSU is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of eight 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
256MB 32Mx64 DDR SDRAM UNBUFFERED
OPERATING FREQUENCIES
DDR333 @CL=2.5
Clock Speed
166MHz
CL-t
RCD
-t
RP
2.5-3-3
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ADVANCED
WV3EG32M64ETSU-D3
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
1
V
REF
47
NC
93
V
SS
139
V
SS
2
DQ0
48
A0
94
DQ4
140
NC
3
V
SS
49
NC
95
DQ5
141
A10
4
DQ1
50
V
SS
96
V
CCQ
142
NC
5
DQS0
51
NC
97
DM0
143
V
CCQ
6
DQ2
52
BA1
98
DQ6
144
NC
7
V
CC
53
DQ32
99
DQ7
145
V
SS
8
DQ3
54
V
CCQ
100
V
SS
146
DQ36
9
NC
55
DQ33
101
NC
147
DQ37
10
NC
56
DQS4
102
NC
148
V
CC
11
V
SS
57
DQ34
103
NC
149
DM4
12
DQ8
58
V
SS
104
V
CCQ
150
DQ38
13
DQ9
59
BA0
105
DQ12
151
DQ39
14
DQS1
60
DQ35
106
DQ13
152
V
SS
15
V
CCQ
61
DQ40
107
DM1
153
DQ44
16
CK1
62
V
CCQ
108
V
CC
154
RAS#
17
CK1#
63
WE#
109
DQ14
155
DQ45
18
V
SS
64
DQ41
110
DQ15
156
V
CCQ
19
DQ10
65
CAS#
111
NC
157
CS0#
20
DQ11
66
V
SS
112
V
CCQ
158
NC
21
CKE0
67
DQS5
113
NC
159
DM5
22
V
CCQ
68
DQ42
114
DQ20
160
V
SS
23
DQ16
69
DQ43
115
A12
161
DQ46
24
DQ17
70
V
CC
116
V
SS
162
DQ47
25
DQS2
71
NC
117
DQ21
163
NC
26
V
SS
72
DQ48
118
A11
164
V
CCQ
27
A9
73
DQ49
119
DM2
165
DQ52
28
DQ18
74
V
SS
120
V
CC
166
DQ53
29
A7
75
CK2#
121
DQ22
167
NC
30
V
CCQ
76
CK2
122
A8
168
V
CC
31
DQ19
77
V
CCQ
123
DQ23
169
DM6
32
A5
78
DQS6
124
V
SS
170
DQ54
33
DQ24
79
DQ50
125
A6
171
DQ55
34
V
SS
80
DQ51
126
DQ28
172
V
CCQ
35
DQ25
81
V
SS
127
DQ29
173
NC
36
DQS3
82
V
CCID
128
V
CCQ
174
DQ60
37
A4
83
DQ56
129
DM3
175
DQ61
38
V
CC
84
DQ57
130
A3
176
V
SS
39
DQ26
85
V
CC
131
DQ30
177
DM7
40
DQ27
86
DQS7
132
V
SS
178
DQ62
41
A2
87
DQ58
133
DQ31
179
DQ63
42
V
SS
88
DQ59
134
NC
180
V
CCQ
43
A1
89
V
SS
135
NC
181
SA0
44
NC
90
NC
136
V
CCQ
182
SA1
45
NC
91
SDA
137
CK0
183
SA2
46
V
CC
92
SCL
138
CK0#
184
V
CCSPD
PIN CONFIGURATION
A0-A12
Address input (Multiplexed)
BA0-BA1
Bank Select Address
DQ0-DQ63
Data Input/Output
DQS0-DQS7
Data Strobe Input/Output
CK0, CK1, CK2
Clock Input
CK0#, CK1#, CK2#
Clock Input
CKE0
Clock Enable input
CS0#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DM0-DM7
Data-in-mask
V
CC
Power Supply
V
CCQ
Power Supply for DQS
V
SS
Ground
V
REF
Power Supply for Reference
V
CCSPD
Serial EEPROM Power Supply
SDA
Serial data I/O
SCL
Serial clock
SA0-SA2
Address in EEPROM
V
CCID
V
CC
Indentifi cation Flag
NC
No Connect
PIN NAMES
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Rev. 0
ADVANCED
WV3EG32M64ETSU-D3
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0
DM0
DQS4
DM4
DQS1
DM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQS2
DM2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQS3
DM3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQS5
DM5
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQS6
DM6
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQS7
DM7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
CS#
DQS
SERIAL PD
SCL
WP
A0
A1
A2
SA0
SA1
SA2
SDA
RAS#
CAS#
BA0-BA1
WE#
A0-A12
CKE0
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
BA0-BA1: DDR SDRAMs
WE#: DDR SDRAMs
A0-A12: DDR SDRAMs
CKE0: DDR SDRAMs
CLOCK INPUT
2 SDRAMS
3 SDRAMS
3 SDRAMS
CK0, CK0#
CK1, CK1#
CK2, CK2#
SPD
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
V
CCSPD
V
CC
/V
CCQ
V
REF
V
SS
*Clock Net Wiring
Card
Edge
DRAM 1
1.5PF
DRAM 5
1.5PF
R = 120 Ohm
DRAM 3
1.5PF
1.5PF
NOTE: All datalines are terminated through a 22 ohm series resistor.
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ADVANCED
WV3EG32M64ETSU-D3
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 to 3.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
-1.0 to 3.6
V
Voltage on V
CCQ
supply relative to V
SS
V
CCQ
-0.5 to 3.6
V
Storage Temperature
T
STG
-55 to +150
C
Power Dissipation
P
D
8
W
Short Circuit Current
I
OS
50
mA
Note: Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0C
T
A
70C, V
CC
= V
CCQ
= 2.5V 0.2V
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage (for device with a nominal V
CC
of 2.5V)
V
CC
2.3
2.7
I/O Supply voltage
V
CCQ
2.3
2.7
V
I/O Reference voltage
V
REF
V
CCQ
/2 -50mV
V
CCQ
/2 +50mV
V
1
I/O Termination voltage(system)
V
TT
V
REF
-0.04
V
REF
+0.04
V
2
Input logic high voltage
V
IH(DC)
V
REF
+0.15
V
CCQ
+0.3
V
4
Input logic low voltage
V
IL(DC)
-0.3
V
REF
-0.15
V
4
Input Voltage Level, CK and CK# inputs
V
IN(DC)
-0.3
V
CCQ
+0.3
V
Input Differential Voltage, CK and CK# inputs
V
ID(DC)
0.36
V
CCQ
+0.6
V
3
Input crossing point voltage, CK and CK# inputs
V
IX(DC)
1.15
1.35
V
5
Input leakage current
I
I
-2
2
uA
Output leakage current
I
OZ
-5
5
uA
Output High Current (Normal strengh driver); V
OUT
= V
TT
+ 0.84V
I
OH
-16.8
mA
Output High Current (Normal strengh driver); V
OUT
= V
TT
+ 0.84V
I
OL
16.8
mA
Output High Current (Half strengh driver); V
OUT
= V
TT
+ 0.84V
I
OH
-9
mA
Output High Current (Half strengh driver); V
OUT
= V
TT
+ 0.84V
I
OL
9
mA
Notes:
1. Includes 25mV margin for DC offset on V
REF
, and a combined total of 50mV margin for all AC noise and DC offset on V
REF
, bandwidth limited to 20MHz. The DRAM must
accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled to V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of 3nH.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
, and must track variations in the DC level of V
REF
.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK#.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifi cations are relative
to a V
REF
envelop that has been bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*V
CCQ
of the transmitting device and must track variations in the DC level of the same.
CAPACITANCE
T
A
= 25C, f = 1MHz, V
CC
= V
CCQ
= 2.5V
Parameter
Symbol
Min
Max
Unit
Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#)
C
IN1
49
57
pF
Input Capacitance (CKE0)
C
IN2
42
50
pF
Input Capacitance (CS0#)
C
IN3
42
50
pF
Input Capacitance (CLK0, CLK1, CLK2)
C
IN4
25
30
pF
Input Capacitance (DM0-DM7)
C
IN5
6
7
pF
Data and DQS input/output capacitance (DQ0-DQ63)
C
OUT1
6
7
pF
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WV3EG32M64ETSU-D3
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0C
T
A
70C, V
CC
= V
CCQ
= 2.5V 0.2V
Includes DDR SDRAM component only
Parameter
Symbol
Conditions
DDR333@
CL = 2.5
Units
Operating one bank active-
precharge current;
I
DD0
t
CK
= t
CK
(I
DD
), t
RC
= t
RC
(I
DD
), t
RAS
= t
RAS
min(I
DD
); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs
are SWITCHING
720
mA
Operating one bank active-
read-precharge current;
I
DD1
I
OUT
= 0mA; BL = 4, CL = CL(I
DD
), AL = 0; t
CK
= t
CK
(I
DD
), t
RC
= t
RC
(I
DD
), t
RAS
=
t
RAS
min(I
DD
), t
RCD
= t
RCD
(I
DD
); CKE is HIGH, CS is HIGH between valid commands;
Address businputs are SWITCHING; Data pattern is same as I
DD4W
920
mA
Precharge power-down
current;
I
DD2P
All banks idle; t
CK
= t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
24
mA
Precharge quiet standby
current;
I
DD2Q
All banks idle; t
CK
= t
CK
(I
DD
); CKE is HIGH, CS is HIGH; Other control and address
bus inputsare STABLE; Data bus inputs are FLOATING
160
mA
Precharge standby current;
I
DD2F
All banks idle; t
CK
= t
CK
(I
DD
); CKE is HIGH, CS is HIGH; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
200
mA
Active power-down current;
I
DD3P
All banks open; t
CK
= t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
280
mA
Active standby current;
I
DD3N
All banks open; t
CK
= t
CK
(I
DD
), t
RAS
= t
RAS
max(I
DD
), t
RP
= t
RP
(I
DD
); CKE is HIGH,
CS - is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
440
mA
Operating burst write current;
I
DD4W
All banks open, Continuous burst writes; BL = 4, CL = CL(I
DD
), AL = 0; t
CK
=
t
CK
(I
DD
), t
RAS
= t
RAS
-max(I
DD
), t
RP
= t
RP
(I
DD
); CKE is HIGH, CS is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
1280 mA
Operating burst read current;
I
DD4R
All banks open, Continuous burst reads, I
OUT
= 0mA; BL = 4, CL = CL(I
DD
), AL
= 0; t
CK
= t
CK
(I
DD
), t
RAS
= t
RAS
max(I
DD
), t
RP
= t
RP
(I
DD
); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as I
DD4W
1280
mA
Burst auto refresh current;
I
DD5
t
CK
= t
CK
(I
DD
); Refresh command at every t
RFC
(I
DD
) interval; CKE is HIGH, CS
is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
1360
mA
Self refresh current;
I
DD6
CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
24
mA
Operating bank interleave
read current;
I
DD7
All bank interleaving reads, I
OUT
= 0mA; BL = 4, CL = CL(I
DD
), AL = t
RCD
(I
DD
)-
1*t
CK
(I
DD
); t
CK
= t
CK
(I
DD
), t
RC
= t
RC
(I
DD
), t
RRD
= t
RRD
(I
DD
), t
RCD
= 1*t
CK
(I
DD
); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE
during DESELECTs; Data pattern is same as I
DD4R
; Refer to the following page for
detailed timing conditions
2240
mA
Note: These specifi cations apply to modules built with Samsung components only.
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Rev. 0
ADVANCED
WV3EG32M64ETSU-D3
I
DD1
: OPERATING CURRENT : ONE BANK
1. Typical
Case
:
V
CC
=2.5V, T=25C
2. Worst
Case
:
V
CC
=2.7V, T=10C
3. Only one bank is accessed with t
RC
(min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I
OUT
= 0mA
4. Timing
Patterns
:
DDR333 (166MHz, CL=2.5) : t
CK
=6ns, BL=4,
t
RCD
=10*t
CK
, t
RAS
=7*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
I
DD7A
: OPERATING CURRENT : FOUR BANKS
1. Typical
Case
:
V
CC
=2.5V, T=25C
2. Worst
Case
:
V
CC
=2.7V, T=10C
3. Four banks are being interleaved with t
RC
(min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing
Patterns
:
DDR333 (166MHz, CL=2.5) : t
CK
=6ns,
BL=4, t
RRD
=3*t
CK
, t
RCD
=3*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DETAILED TEST CONDITIONS FOR DDR SDRAM I
DD1
& I
DD7A
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
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ADVANCED
WV3EG32M64ETSU-D3
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
Parameter
Symbol
335
Unit
Note
Min
Max
Row cycle time
t
RC
60
ns
Refresh row cycle time
t
RFC
72
ns
Row active time
t
RAS
42
70K
ns
RAS to CAS delay
t
RCD
18
ns
Row precharge time
t
RP
18
ns
Row active to Row active delay
t
RRD
12
ns
Write recovery time
t
WR
15
ns
Last data into Read command
t
WTR
1
t
CK
Col. address to Col. address delay
t
CCD
1
t
CK
Clock cycle time
t
CK
6
12
ns
Clock high level width
t
CH
0.45
0.55
t
CK
Clock low level width
t
CL
0.45
0.55
t
CK
DQS-out access time from CK/CK
t
DQSCK
-0.6
+0.6
ns
Output data access time from CK/CK
t
AC
-0.7
+0.7
ns
Data strobe edge to ouput data edge
t
DQSQ
--
0.45
ns
12
Read Preamble
t
RPRE
0.9
1.1
t
CK
Read Postamble
t
RPST
0.4
0.6
t
CK
CK to valid DQS-in
t
DQSS
0.75
1.25
t
CK
DQS-in setup time
t
WPRES
0
ns
3
DQS-in hold time
t
WPRE
0.25
t
CK
DQS falling edge to CK rising-setup time
t
DSS
0.2
t
CK
DQS falling edge from CK rising-hold time
t
DSH
0.2
t
CK
DQS-in high level width
t
DQSH
0.35
t
CK
DQS-in low level width
t
DQSL
0.35
t
CK
DQS-in cycle time
t
DSC
0.9
1.1
t
CK
Address and Control Input setup time(fast)
t
IS
0.75
ns
5.7~9
Address and Control Input hold time(fast)
t
IH
0.75
ns
5.7~9
Address and Control Input setup time(slow)
t
IS
0.8
ns
6~9
Address and Control Input hold time(slow)
t
IH
0.8
ns
6~9
Data-out high impedence time from CK/CK
t
HZ
+0.7
ns
1
Data-out low impedence time from CK/CK
t
LZ
-0.7
+0.7
ns
1
Output Slew Rate Matching Ratio(rise to fall)
t
SLMR
0.67
1.5
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WV3EG32M64ETSU-D3
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
Parameter
Symbol
B3
Unit
Note
Min
Max
Mode register set cycle time
t
MRD
12
ns
DQ & DM setup time to DQS
t
DS
0.45
ns
DQ & DM hold time to DQS
t
DH
0.45
ns
Control & Address input pulse width
t
IPW
2.2
ns
8
DQ & DM input pulse width
t
DIPW
1.75
ns
8
Power down exit time
t
PDEX
6
ns
Exit self refresh to non-Read command
t
XSNR
75
ns
Exit self refresh to read command
t
XSRD
200
t
CK
Refresh interval time
t
REFI
7.8
us
4
Output DQS valid window
t
QH
t
HP
-t
QHS
--
ns
11
Clock half period
t
HP
t
CLmin
or t
CHmin
--
ns
10, 11
Data hold skew factor
t
QHS
0.55
ns
11
DQS write postamble time
t
WPST
0.4
0.6
t
CK
2
Active to Read with Auto precharge command
t
RAP
18
Autoprecharge write recovery + Precharge time
t
DAL
(t
WR
/t
CK
) +
(t
RP
/t
CK
)
t
CK
13
AC OPERATING TEST CONDITIONS
V
CC
= 2.5V, V
CCQ
= 2.5V, 0C
T
A
70C
Parameter
Value
Unit
Note
Input reference voltage for Clock
0.5 * V
CCQ
V
Input signal maximum peak swing
1.5
V
Input Levels (V
IH
/V
IL
)
V
REF
+0.31/V
REF
-0.31
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
TT
V
Output load condition
See Load Circuit
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
CCQ
R
T
=50
V
TT
=0.5*V
CCQ
OUTPUT LOAD CIRCUIT (SSTL_2)
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Component Notes
1. t
HZ
and t
LZ
transitions occur in the same access
time windows as valid data transitions. these
parameters are not referenced to a specifi c voltage
level but specify when the device output in no
longer driving (HZ), or begins driving (LZ).
2. The maximum limit for this parameter is not a
device limit. The device will operate with a greater
value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
3. The specifi c requirement is that DQS be valid
(HIGH, LOW, or at some point on a valid transition)
on or before this CK edge. A valid transition is
defi ned as monotonic and meeting the input slew
rate specifi cations of the device. when no writes
were previously in progress on the bus, DQS will
be tran sitioning from High- Z to logic LOW. If a
previous write was in progress, DQS could be
HIGH, LOW, or transitioning from HIGH to LOW at
this time, depending on t
DQSS
.
4. A maximum of eight AUTO REFRESH commands
can be posted to any given DDR SDRAM device.
5. For command/address input slew rate: 1.0 V/ns
6. For command/address input slew rate: 0.5 V/ns
and 1.0 V/ns
7. For CK & CK# slew rate 1.0 V/ns
8. These parameters guarantee device timing, but
they are not necessarily tested on each device.
They may be guaranteed by device design or tester
correlation.
9. Slew Rate is measured between V
OH(ac)
and V
OL(ac)
.
10. Min (t
CL
, t
CH
) refers to the smaller of the actual clock
low time and the actual clock high time as provided
to the device (i.e. this value can be greater than the
minimum specifi cation limits for t
CL
and t
CH
).....For
example, t
CL
and t
CH
are = 50% of the period, less
the half period jitter (t
JIT(HP)
) of the clock source,
and less the half period jitter due to crosstalk
(t
JIT(crosstalk)
) into the clock traces.
11. t
QH
= t
HP
- t
QHS
, where:
t
HP
= minimum half clock period for any given cycle
and is defi ned by clock high or clock low (t
CH
, t
CL
).
t
QHS
accounts for 1) The pulse duration distortion
of on-chip clock circuits; and 2) The worst case
push-out of DQS on one tansition followed by the
worst case pull-in of DQ on the next transition, both
of which are, separately, due to data pin skew and
output pattern effects, and pchannel to n-channel
variation of the output drivers.
12. t
DQSQ
Consists of data pin skew and output pattern
effects, and p-channel to n-channel variation of the
output drivers for any given cycle.
13. t
DAL
= (t
WR
/t
CK
) + (t
RP
/t
CK
)
For each of the terms above, if not already an
integer, round to the next highest integer. Example:
For DDR266B at CL=2.5 and t
CK
=7.5ns t
DAL
= (15
ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) t
DAL
= 5
clocks
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WV3EG32M64ETSU-D3
1.27 (0.050)
4.00
(0.158 (2x))
17.80
(0.70)
133.35 0.15
(5.25 0.006)
128.95
(5.077")
10.00
(0.393)
64.77
(2.550)
49.53
(1.95)
1.80
(0.071)
2.175
(0.085)
28.58 0.15
(1.125 0.006)
2.30
(0.10)
(2x)
3.00
(0.118)
(4x)
3.30
(0.130)
MAX
1.27 0.10
(0.050 0.004)
PACKAGE DIMENSIONS FOR D3
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency
t
RCD
t
RP
Height*
Temperature
WV3EG32M64ETSU335D3xG
166MHz/333Mb/s
2.5
3
3
28.58 (1.125")
0C to 70C
NOTES:
Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
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WV3EG32M64ETSU-D3
PART NUMBERING GUIDE
WV 3 E G 32M 64 E T S U xxx D3 x G
WEDC
MEMORY
DDR
GOLD
DEPTH
BUS WIDTH
x8
TSOP
2.5V
UNBUFFERED
SPEED (MHz)
PACKAGE 184 PIN
COMPONENT VENDOR
NAME
(M = Micron)
(S = Samsung)
G = ROHS COMPLIANT
Document Title
256MB 32Mx64 DDR SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
7-05
Advanced
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WV3EG32M64ETSU-D3
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