White Electronic Designs
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
PRELIMINARY*
August 2005
Rev. 1
WV3EG64M64ETSU-D3
FEATURES
Double-data-rate architecture
PC2700 @ CL 2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply:
V
CC
= V
CCQ
= +2.5V 0.2V
184 pin DIMM package
D3 PCB height: 28.58mm (1.125")
NOTE: Consult factory for availability of:
RoHS compliant products
Vendor source control options
Industrial temperature option
DESCRIPTION
The WV3EG64M64ETSU is a 64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eight 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualifi ed or characterized and is subject to
change without notice.
512MB 64Mx64 DDR SDRAM UNBUFFERED
OPERATING FREQUENCIES
DDR333 @CL=2.5
Clock Speed
166MHz
CL-t
RCD
-t
RP
2.5-3-3
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
August 2005
Rev. 1
PRELIMINARY
WV3EG64M64ETSU-D3
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
1
V
REF
47
NC
93
V
SS
139
V
SS
2
DQ0
48
A0
94
DQ4
140
NC
3
V
SS
49
NC
95
DQ5
141
A10
4
DQ1
50
V
SS
96
V
CCQ
142
NC
5
DQS0
51
NC
97
DM0
143
V
CCQ
6
DQ2
52
BA1
98
DQ6
144
NC
7
V
CC
53
DQ32
99
DQ7
145
V
SS
8
DQ3
54
V
CCQ
100
V
SS
146
DQ36
9
NC
55
DQ33
101
NC
147
DQ37
10
NC
56
DQS4
102
NC
148
V
CC
11
V
SS
57
DQ34
103
NC
149
DM4
12
DQ8
58
V
SS
104
V
CCQ
150
DQ38
13
DQ9
59
BA0
105
DQ12
151
DQ39
14
DQS1
60
DQ35
106
DQ13
152
V
SS
15
V
CCQ
61
DQ40
107
DM1
153
DQ44
16
CK1
62
V
CCQ
108
V
CC
154
RAS#
17
CK1#
63
WE#
109
DQ14
155
DQ45
18
V
SS
64
DQ41
110
DQ15
156
V
CCQ
19
DQ10
65
CAS#
111
NC
157
CS0#
20
DQ11
66
V
SS
112
V
CCQ
158
NC
21
CKE0
67
DQS5
113
NC
159
DM5
22
V
CCQ
68
DQ42
114
DQ20
160
V
SS
23
DQ16
69
DQ43
115
A12
161
DQ46
24
DQ17
70
V
CC
116
V
SS
162
DQ47
25
DQS2
71
NC
117
DQ21
163
NC
26
V
SS
72
DQ48
118
A11
164
V
CCQ
27
A9
73
DQ49
119
DM2
165
DQ52
28
DQ18
74
V
SS
120
V
CC
166
DQ53
29
A7
75
CK2#
121
DQ22
167
NC
30
V
CCQ
76
CK2
122
A8
168
V
CC
31
DQ19
77
V
CCQ
123
DQ23
169
DM6
32
A5
78
DQS6
124
V
SS
170
DQ54
33
DQ24
79
DQ50
125
A6
171
DQ55
34
V
SS
80
DQ51
126
DQ28
172
V
CCQ
35
DQ25
81
V
SS
127
DQ29
173
NC
36
DQS3
82
V
CCID
128
V
CCQ
174
DQ60
37
A4
83
DQ56
129
DM3
175
DQ61
38
V
CC
84
DQ57
130
A3
176
V
SS
39
DQ26
85
V
CC
131
DQ30
177
DM7
40
DQ27
86
DQS7
132
V
SS
178
DQ62
41
A2
87
DQ58
133
DQ31
179
DQ63
42
V
SS
88
DQ59
134
NC
180
V
CCQ
43
A1
89
V
SS
135
NC
181
SA0
44
NC
90
NC
136
V
CCQ
182
SA1
45
NC
91
SDA
137
CK0
183
SA2
46
V
CC
92
SCL
138
CK0#
184
V
CCSPD
PIN CONFIGURATION
A0-A12
Address input (Multiplexed)
BA0-BA1
Bank Select Address
DQ0-DQ63
Data Input/Output
DQS0-DQS7
Data Strobe Input/Output
CK0, CK1, CK2
Clock Input
CK0#, CK1#, CK2#
Clock Input
CKE0
Clock Enable input
CS0#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DM0-DM7
Data-in-mask
V
CC
Power Supply
V
CCQ
Power Supply for DQS
V
SS
Ground
V
REF
Power Supply for Reference
V
CCSPD
Serial EEPROM Power Supply
SDA
Serial data I/O
SCL
Serial clock
SA0-SA2
Address in EEPROM
V
CCID
V
CC
Indentifi cation Flag
NC
No Connect
PIN NAMES
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
August 2005
Rev. 1
PRELIMINARY
WV3EG64M64ETSU-D3
FUNCTIONAL BLOCK DIAGRAM
SERIAL PD
SCL
WP
A0
A1
A2
SA0 SA1
SA2
SDA
BA0-BA1
A0-A12
RAS#
CAS#
CKE0
WE#
BA0-BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE: DDR SDRAMs
WE#: DDR SDRAMs
Clock Wiring
2 DDR SDRAMs
3 DDR SDRAMs
3 DDR SDRAMs
Clock
Input
DDR SDRAMs
CK0, CK0#
CK1, CK1#
CK2, CK2#
*Clock Net Wiring
Card
Edge
DRAM 1
1.5PF
DRAM 5
1.5PF
R = 120 Ohm
DRAM 3
1.5PF
DDR SDRAMs
DDR SDRAMs
V
CCSPD
V
CC
/V
CCQ
V
REF
V
SS
DDR SDRAMs
SPD
CS0#
DQS0
DM0
DQS4
DM4
DQS1
DM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DM
CS#
DQS
DQS2
DM2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DM
CS#
DQS
DQS3
DM3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DM
CS#
DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DM
CS#
DQS
DQS5
DM5
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DM
CS#
DQS
DQS6
DM6
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DM
CS#
DQS
DQS7
DM7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DM
CS#
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ7
DQ6
DQ1
DQ0
DQ5
DQ4
DQ3
DQ2
DM
CS#
DQS
NOTE: All datalines are terminated through a 22 ohm series resistor.
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS# relationships must be maintained as shown.
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August 2005
Rev. 1
PRELIMINARY
WV3EG64M64ETSU-D3
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 to 3.6
V
Voltage on V
CC
supply relative to V
SS
V
CC
-1.0 to 3.6
V
Voltage on V
CCQ
supply relative to V
SS
V
CCQ
-1.0 to 3.6
V
Storage Temperature
T
STG
-55 to +150
C
Operating Temperature
T
A
0 to +70
C
Power Dissipation
P
D
8
W
Short Circuit Current
I
OS
50
mA
Note: Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0C
T
A
70C, V
CC
= V
CCQ
= 2.5V 0.2V
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage DDR266/DDR333 (nominal V
CC
of 2.5V)
V
CC
2.3
2.7
I/O Supply voltage DDR266/DDR333 (nominal V
CC
of 2.5V)
V
CCQ
2.3
2.7
V
I/O Reference voltage
V
REF
0.49*V
CCQ
0.51*V
CCQ
V
1
I/O Termination voltage
V
TT
V
REF
-0.04
V
REF
+0.04
V
2
Input logic high voltage
V
IH
(DC)
V
REF
+0.15
V
CCQ
+0.30
V
Input logic low voltage
V
IL
(DC)
-0.3
V
REF
-0.15
V
Input voltage level, CK and CK#
V
IN
(DC)
-0.3
V
CCQ
+0.30
V
Input differential voltage, CK and CK#
V
ID
(DC)
0.36
V
CCQ
+0.60
V
3
Input crossing point voltage, CK and CK#
V
IX
(DC)
0.3
V
CCQ
+0.60
V
Input leakage current
Addr, CAS#,
RAS#, WE#
I
I
-16
16
uA
CS#, CKE
-16
16
uA
CK, CK#
-6
6
uA
DM
-2
2
uA
Output leakage current
I
OZ
-5
5
uA
Output high current (normal strengh); V
OUT
= V +0.84V
I
OH
-16.8
--
mA
Output high current (normal strengh); V
OUT
= V
TT
-0.84V
I
OL
16.8
--
mA
Output high current (half strengh); V
OUT
= V
TT
+0.45V
I
OH
-9
--
mA
Output high current (half strengh); V
OUT
= V
TT
-0.45V
I
OL
9
--
mA
NOTES:
1. V
REF
is expected to be equal to 0.5*V
CCQ
of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on V
REF
may not exceed 2% of the DC
value
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK#.
CAPACITANCE
T
A
= 25C, f = 1MHz, V
CC
= V
CCQ
= 2.5V
Parameter
Symbol
Min
Max
Unit
Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#)
C
IN1
20
28
pF
Input Capacitance (CKE0)
C
IN2
20
28
pF
Input Capacitance (CS0#)
C
IN3
20
28
pF
Input Capacitance (CK0 to CK2, CK0# to CK2#)
C
IN4
10
13
pF
Input Capacitance (DM0-DM7)
C
IN5
8
9
pF
Data and DQS input/output capacitance (DQ0-DQ63)
C
OUT1
8
9
pF
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August 2005
Rev. 1
PRELIMINARY
WV3EG64M64ETSU-D3
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0C
T
A
70C, V
CC
= V
CCQ
= 2.5V 0.2V
Includes DDR SDRAM component only
Parameter
Symbol
Conditions
DDR333 @
CL = 2.5
Unit
Operating current
I
DD0*
One device bank active; Active-Precharge; t
RC
= t
RC(MIN)
; t
CK
= t
CK(MIN)
;
DQ, DM and DQS inputs change once per clock cycle; Address and control
inputs change once every two clock cycles
1000
mA
Operating current
I
DD1*
One device bank; Active-Read-Precharge; BL = 4; t
RC
= t
RC(MIN)
; t
CK
= t
CK(MIN)
;
I
OUT
= 0mA; Address and control inputs change once per clock cycle
1200
mA
Percharge power-
down standby current
I
DD2P**
All device banks are idle; Power-down mode; t
CK
= t
CK(MIN)
; CKE = LOW
40
mA
Idle standby current
I
DD2F**
CS# = HIGH; All device banks are idle; t
CK
= t
CK(MIN)
; CKE = HIGH; Address
and other control inputs changing once per clock cycle. V
IN
= V
REF
for DQ,
DQS and DM
240
mA
Active power-down
standby current
I
DD3P**
One device bank active; Power-down mode; t
CK
= t
CK(MIN)
; CKE = LOW
240
mA
Active standby
current
I
DD3N**
CS# = HIGH; CKE = HIGH; One device bank active; t
RC
= t
RAS(MAX)
;
t
CK
= t
CK(MIN)
; DQ, DM and DQS inputs change twice per clock cycle; Address
and other control inputs changing once per clock cycle
400
mA
Operating current
I
DD4R*
Burst = 2; Reads; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; t
CK
= t
CK(MIN)
; I
OUT
= 0mA
1440
mA
Operating current
I
DD4W*
Burst = 2; Writes; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; t
CK
= t
CK(MIN)
; DQ, DM and
DQS inputs change twice per clock cycle
1480
mA
Auto refresh current
I
DD5**
t
RC
= t
RFC(MIN)
2000
mA
Self refresh current
I
DD6**
CKE < 0.2V
40
mA
Orerating current
I
DD7*
Four device bank interleaving Reads Burst = 4 with auto precharge;
t
RC
= t
RFC(MIN)
; t
CK
= t
CK(MIN)
; Address and control inputs change only during
Active READ, or WRITE commands
3120
mA
Note: These specifi cations apply to modules built with Samsung components only.
* Value calculated as one module rank in this operation condition and other module rank in I
DD2P
(CKE low) mode.
** Value calculated as all module ranks in this operation condition.
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August 2005
Rev. 1
PRELIMINARY
WV3EG64M64ETSU-D3
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
Parameter
Symbol
335
Unit
Min
Max
Row cycle time
t
RC
60
ns
Refresh row cycle time
t
RFC
72
ns
Row active time
t
RAS
42
70K
ns
RAS to CAS delay
t
RCD
18
ns
Row precharge time
t
RP
18
ns
Row active to Row active delay
t
RRD
12
ns
Write recovery time
t
WR
15
ns
Last data into Read command
t
WTR
1
t
CK
Clock cycle time
CL = 2.5
t
CK
6
12
ns
Clock high level width
t
CH
0.45
0.55
t
CK
Clock low level width
t
CL
0.45
0.55
t
CK
DQS-out access time from CK/CK
t
DQSCK
-0.6
+0.6
ns
Output data access time from CK/CK
t
AC
-0.7
+0.7
ns
Data strobe edge to ouput data edge
t
DQSQ
--
0.45
ns
Read Preamble
t
RPRE
0.9
1.1
t
CK
Read Postamble
t
RPST
0.4
0.6
t
CK
CK to valid DQS-in
t
DQSS
0.75
1.25
t
CK
DQS-in setup time
t
WPRES
0
ns
DQS-in hold time
t
WPRE
0.25
t
CK
DQS falling edge to CK rising-setup time
t
DSS
0.2
t
CK
DQS falling edge from CK rising-hold time
t
DSH
0.2
t
CK
DQS-in high level width
t
DQSH
0.35
t
CK
DQS-in low level width
t
DQSL
0.35
t
CK
Address and Control Input setup time (fast)
t
IS
0.75
ns
Address and Control Input hold time (fast)
t
IH
0.75
ns
Address and Control Input setup time (slow)
t
ISF
0.8
ns
Address and Control Input hold time (slow)
t
IHF
0.8
ns
Data-out high impedence time from CK/CK
t
HZS
-0.7
+0.7
ns
Data-out low impedence time from CK/CK
t
LZS
-0.7
+0.7
ns
Output Slew Rate Matching Ratio (rise to fall)
t
SLMR
0.67
1.5
Note: These specifi cations apply to modules built with Samsung components only.
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Rev. 1
PRELIMINARY
WV3EG64M64ETSU-D3
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
Parameter
Symbol
335
Unit
Min
Max
Mode register set cycle time
t
MRD
12
ns
DQ & DM setup time to DQS
t
DS
0.45
ns
DQ & DM hold time to DQS
t
DH
0.45
ns
Control & Address input pulse width
t
IPW
2.2
ns
DQ & DM input pulse width
t
DIPW
1.75
ns
Exit self refresh to non-Read command
t
XSNR
75
ns
Exit self refresh to read command
t
XSRD
200
t
CK
Refresh interval time
t
REFI
7.8
us
Output DQS valid window
t
QH
t
HP
-t
QHS
--
ns
Clock half period
t
HP
t
CLmin
or t
CHmin
--
ns
Data hold skew factor
t
QHS
0.55
ns
DQS write postamble time
t
WPST
0.4
0.6
ns
Active to Read with Auto precharge command
t
RAP
18
Autoprecharge write recovery + Precharge time
t
DAL
(t
WR
/t
CK
) +
(t
RP
/t
CK
)
t
CK
AC OPERATING TEST CONDITIONS
V
CC
= 2.5V, V
CCQ
= 2.5V, 0C
T
A
70C
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage
V
IH(AC)
V
REF
+0.31
V
1
Input Low (Logic 0) Voltage
V
IL(AC)
V
REF
-0.31
V
1
Input Differential Voltage, CK and CK# inputs
V
ID(AC)
0.7
V
CCQ
+0.6
V
Input Crossing Point Voltage, CK and CK# inputs
V
IX(AC)
0.5*V
CCQ
-0.2
0.5*V
CCQ
+0.2
V
NOTES:
1.
V
IH
overshoot: V
IH
= V
CCQ
+1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
V
IL
undershoot: V
IL
= -1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
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Rev. 1
PRELIMINARY
WV3EG64M64ETSU-D3
1.27 (0.050)
4.00
(0.158 (2x))
17.80
(0.70)
133.35 0.15
(5.25 0.006)
128.95
(5.077")
10.00
(0.393)
64.77
(2.550)
49.53
(1.95)
1.80
(0.071)
2.175
(0.085)
28.58 0.15
(1.125 0.006)
2.30
(0.10)
(2x)
3.00
(0.118)
(4x)
3.30
(0.130)
MAX
1.27 0.10
(0.050 0.004)
PACKAGE DIMENSIONS FOR D3
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency
t
RCD
t
RP
Height*
Temperature
WV3EG64M64ETSU335D3xG
166MHz/333Mb/s
2.5
3
3
28.58 (1.125")
0C to 70C
NOTES:
Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
White Electronic Designs
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
August 2005
Rev. 1
PRELIMINARY
WV3EG64M64ETSU-D3
PART NUMBERING GUIDE
WV 3 E G 64M 64 E T S U xxx D3 x G
WEDC
MEMORY
DDR
GOLD
DEPTH
BUS WIDTH
x8
TSOP
2.5V
UNBUFFERED
SPEED (MHz)
PACKAGE 184 PIN
COMPONENT VENDOR
NAME
(M = Micron)
(S = Samsung)
G = ROHS COMPLIANT
Document Title
512MB 64Mx64 DDR SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
7-05
Advanced
Rev 1
1.1 Update to DC, I
DD
and AC specifi cations
1.2 Changed from Advanced to Preliminary
8-05
Preliminary
White Electronic Designs
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
August 2005
Rev. 1
PRELIMINARY
WV3EG64M64ETSU-D3
PDF 
ZIP