May 2006
Rev. 0
ADVANCED*
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WV3HG128M72EEU-PD4
1GB 128Mx72 DDR2 SDRAM UNBUFFERED, SO-DIMM w/PLL
DESCRIPTION
The WV3HG128M72EEU is a 128Mx72 Double Data Rate
DDR2 SDRAM high density module. This memory module
consists of nine 128Mx8 bit DDR2 Synchronous DRAMs
in FBGA packages, mounted on a 200-pin SO-DIMM FR4
substrate.
* This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
Vendor source control options
Industrial temperature option
FEATURES
Unbuffered 200-pin (SO-DIMM) small-outline dual
in-line memory module
Support ECC detection and correction
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
V
CC
= V
CCQ
= 1.8V 0.1V
V
CCSPD
= 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Differential clock input (CK,CK#)
Four-bit
prefetch
architecture
Multiple internal device banks for concurrent
operation
Programmable CAS# latency (CL): 3 4, 5*, and 6*
Adjustable data-output drive strength
7.8s average periodic refresh interval
On-die
termination
(ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms: 8,192 cycle refresh)
Gold edge contacts
RoHS
compliant
JEDEC proposed pin-out
Package
option
200 Pin SO-DIMM: 30.00mm (1.181") TYP
OPERATING FREQUENCIES
PC2-3200
PC2-4200
PC2-5300*
PC2-6400*
Clock Speed
200MHz
266MHz
333MHz
400MHz
CL-t
RCD
-t
RP
3-3-3
4-4-4
5-5-5
6-6-6
* Consult factory for availability
WV3HG128M72EEU-PD4
May 2006
Rev. 0
ADVANCED
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PIN CONFIGURATION
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
1
V
REF
51
DQ18
101
V
CC
151
V
SS
2
V
SS
52
V
SS
102
A6
152
V
SS
3
DQ0
53
DQ19
103
A5
153
DQS5#
4
DQ4
54
DQ28
104
A4
154
DM5
5
V
SS
55
V
SS
105
A3
155
DQS5
6
DQ5
56
DQ29
106
V
CC
156
V
SS
7
DQ1
57
DQ24
107
A2
157
V
SS
8
V
SS
58
V
SS
108
A1
158
DQ46
9
DQS0#
59
DQ25
109
V
CC
159
DQ42
10
DM0
60
DM3
110
A0
160
DQ47
11
DQS0
61
V
SS
111
A10/AP
161
DQ43
12
V
SS
62
V
SS
112
BA1
162
V
SS
13
V
SS
63
DQS3#
113
BA0
163
V
SS
14
DQ6
64
DQ30
114
V
CC
164
DQ52
15
DQ2
65
DQS3
115
RAS#
165
DQ48
16
DQ7
66
DQ31
116
WE#
166
DQ53
17
DQ3
67
V
SS
117
V
CC
167
DQ49
18
V
SS
68
V
SS
118
CS0#
168
V
SS
19
V
SS
69
DQ26
119
CAS#
169
V
SS
20
DQ12
70
CB4
120
ODT0
170
DM6
21
DQ8
71
DQ27
121
NC
171
DQS6#
22
DQ13
72
CB5
122
A13
172
V
SS
23
DQ9
73
V
SS
123
V
CC
173
DQS6
24
V
SS
74
V
SS
124
V
CC
174
DQ54
25
V
SS
75
CB0
125
NC
175
V
SS
26
DM1
76
DM8
126
CK
176
DQ55
27
DQS1#
77
CB1
127
NC
177
DQ50
28
V
SS
78
V
SS
128
CK#
178
V
SS
29
DQS1
79
V
SS
129
DQ32
179
DQ51
30
DQ14
80
CB6
130
V
SS
180
DQ60
31
V
SS
81
DQS8#
131
V
SS
181
V
SS
32
DQ15
82
CB7
132
DQ36
182
DQ61
33
DQ10
83
DQS8
133
DQ33
183
DQ56
34
V
SS
84
V
SS
134
DQ37
184
V
SS
35
DQ11
85
V
SS
135
DQS4#
185
DQ57
36
DQ20
86
CB2
136
V
SS
186
DM7
37
V
SS
87
CKE0
137
DQS4
187
V
SS
38
DQ21
88
CB3
138
DM4
188
DQ62
39
DQ16
89
NC
139
V
SS
189
DQS7#
40
V
SS
90
V
SS
140
V
SS
190
V
SS
41
DQ17
91
NC
141
DQ34
191
DQS7
42
NC
92
NC
142
DQ38
192
DQ63
43
V
SS
93
V
CC
143
DQ35
193
DQ58
44
DM2
94
NC
144
DQ39
194
SDA
45
DQS2#
95
A12
145
V
SS
195
V
SS
46
V
SS
96
A11
146
V
SS
196
SCL
47
DQS2
97
A9
147
DQ40
197
DQ59
48
DQ22
98
V
CC
148
DQ44
198
SA1
49
V
SS
99
A7
149
DQ41
199
VCCSPD
50
DQ23
100
A8
150
DQ45
200
SA0
PIN NAMES
Pin Name
Function
A0-A13
Address Inputs
BA0, BA2
SDRAM Bank Address
DQ0-DQ63
Data Input/Output
CB0-CB7
Check Bits
DQS0-DQS8
Data strobes
DQS0#-DQS8#
Data strobes complement
ODT0
On-die termination controls
CK,CK#
Clock inputs
CKE0
Clock enable inputs
CS0#
Chip select inputs
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
V
CC
Core Power
V
SS
Ground
SA0-SA1
SPD address
SDA
Serial Data Input/Output
V
REF
Input/Output Reference Voltage
DM0-DM8
Data-in mask
V
CCSPD
Serial EEPROM power supply
SCL
SPD Clock Input
NC
No connect
WV3HG128M72EEU-PD4
May 2006
Rev. 0
ADVANCED
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
A0
Serial PD
A1
A2
SA0 SA1 SA2
SDA
SCL
WP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/ CS# DQS DQS#
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
CS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DQS1
DQS1#
DM1
DQS5
DQS5#
DM5
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DQS3
DQS3#
DM3
DQS7
DQS7#
DM7
DQS8
DQS8#
DM8
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
P
L
L
V
REF
V
SS
DDR2 SDRAMs
DDR2 SDRAMs
V
CC\
V
CCSPD
Serial PD
V
CCQ
DDR2 SDRAMs
DM/ CS# DQS DQS#
RDQS
DM/ CS# DQS DQS#
RDQS
DM/ CS# DQS DQS#
RDQS
DM/ CS# DQS DQS#
RDQS
DM/ CS# DQS DQS#
RDQS
DM/ CS# DQS DQS#
RDQS
DM/ CS# DQS DQS#
RDQS
DM/ CS# DQS DQS#
RDQS
CS0#
BA0-BA2
A0-A13
RAS#
CAS#
WE#
CKE0
ODT0
CS0# CS#: DDR2 SDRAMs
CK0
CK0#
PCK0# , PCK4#-PCK6#, PCK9# CK#: DDR2 SDRAMs
PCK0, PCK4-PCK6, PCK9 CK: DDR2 SDRAMs
BA0-RBA2 BA0-BA2: DDR2 SDRAMs
A0-RA13 A0-A13: DDR2 SDRAMs
RAS# RAS#: DDR2 SDRAMs
CAS# CAS#: DDR2 SDRAMs
WE# WE#: DDR2 SDRAMs
CKE0 CKE: DDR2 SDRAMs
ODT0 ODT: DDR2 SDRAMs
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NOTE: Unless otherwise noted, resistor values are 22 Ohms 5%
WV3HG128M72EEU-PD4
May 2006
Rev. 0
ADVANCED
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DC OPERATING CONDITIONS
All voltages referenced to V
SS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Supply Voltage
V
CC
1.7
1.8
1.9
V
3
I/O Reference Voltage
V
REF
0.49 x V
CC
0.50 x V
CC
0.51 x V
CC
V
1
I/O Termination Voltage
V
TT
V
REF
-0.04
V
REF
V
REF
+0.04
V
2
SPD Supply Voltage
V
CCSPD
1.7
-
3.6
V
Notes:
1
V
REF
is expected to equal V
CC/2
of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on
V
REF
may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on V
REF
may not exceed +/-2 percent of V
REF
. This measurement is to be taken at the nearest V
REF
bypass capacitor.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
3. V
CCQ
of all IC's are tied to V
CC
.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
V
CC
Voltage on V
CC
pin relative to V
SS
-0.5
2.3
V
V
IN
, V
OUT
Voltage on any pin relative to V
SS
-0.5
2.3
V
I
L
Input leakage current; Any input 0V<V
IN
<V
CC
; V
REF
input
0V,V
IN
,0.95V; Other pins not under test = 0V
Command/Address,
RAS#, CAS#, WE#,
-45
45
A
CS#, CKE
-45
45
A
CK, CK#
-10
10
A
DM
-5
5
A
I
OZ
Output leakage current; 0V<V
IN
<V
CC
; DQs and ODT are disable
DQ, DQS, DQS#
-5
5
A
I
VREF
V
REF
leakage current; V
REF
= Valid V
REF
level
-18
18
A
INPUT/OUTPUT CAPACITANCE
TA=25C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (0A~A13, BA0~BA1,
RAS#, CAS#, WE#)
C
IN
1
13
22
pF
Input capacitance (CKE0) (ODT0)
C
IN
2
13
22
pF
Input capacitance (CS0#)
C
IN
3
13
22
pF
Input capacitance (CK, CK#)
C
IN
4
6
7
pF
Input capacitance (DM0~DM8),
(DQS0~DQS8)
C
IN
5 (665)
6.5
7.5
pF
C
IN
5 (534, 403)
6.5
8
pF
Input capacitance (DQ0~DQ63),
(CB0~CB7)
C
OUT
1 (665)
6.5
7.5
pF
C
OUT
1 (534, 403)
6.5
8
pF
WV3HG128M72EEU-PD4
May 2006
Rev. 0
ADVANCED
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating temperature (Commercial)
TOPER
0
to 85
C
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
2. At 0C - 85C, operation temperature range, all DRAM specifi cation will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Symbol
Min
Max
Units
Input High (Logic 1) Voltage
V
IH
(DC)
V
REF
+ 0.125
V
CC
+ 0.300
V
Input Low (Logic 0) Voltage
V
IL
(DC)
-0.300
V
REF
- 0.125
V
INPUT AC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage
DDR2-400 & DDR2-533
V
IH
(AC)
V
REF
+ 0.250
-
V
AC Input High (Logic 1) Voltage
DDR2-667
V
IH
(AC)
V
REF
+ 0.200
-
V
AC Input High (Logic 0) Voltage
DDR2-400 & DDR2-533
V
IL
(AC)
-
V
REF
- 0.250
V
AC Input High (Logic 0) Voltage
DDR2-667
V
IL
(AC)
-
V
REF
- 0.200
V
WV3HG128M72EEU-PD4
May 2006
Rev. 0
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DDR2 I
CC
SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
V
CC
= +1.8V 0.1V
Symbol
Proposed Conditions
806
665
534
403
Units
I
CC0*
Operating one bank active-precharge current;
t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS
min(I
CC
); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
1,110
1,065
1,020
mA
I
CC1*
Operating one bank active-read-precharge current;
I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS
min(I
CC
), t
RCD
= t
RCD
(I
CC
); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as I
CC
4W
TBD
1,200
1,115
1,1110
mA
I
CC2P*
Precharge power-down current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
TBD
408
408
408
mA
I
CC2Q**
Precharge quiet standby current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
TBD
660
615
615
mA
I
CC2N**
Precharge standby current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
TBD
705
660
660
mA
I
CC3P**
Active power-down current;
All banks open; t
CK
= t
CK
(I
CC
); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
TBD
570
525
525
mA
Slow PDN Exit MRS(12) = 1
TBD
408
408
408
mA
I
CC3N**
Active standby current;
All banks open; t
CK
= t
CK
(I
CC
), t
RAS
= t
RAS
max(I
CC
), t
RP
= t
RP
(I
CC
); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD
750
705
705
mA
I
CC4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RAS
=
t
RAS
max(I
CC
), t
RP
= t
RP
(I
CC
); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
1,645
1,470
1,362
mA
I
CC4R*
Operating burst read current;
All banks open, Continuous burst reads, I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RAS
= t
RAS
max(I
CC
), t
RP
= t
RP
(I
CC
); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as I
CC
4W
TBD
1,645
1,470
1,335
mA
I
CC5B**
Burst auto refresh current;
t
CK
= t
CK
(I
CC
); Refresh command at every t
RFC
(I
CC
) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD
2,280
2,235
2,190
mA
I
CC6**
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs
are FLOATING; Data bus inputs are FLOATING
Normal
TBD
90
90
90
mA
I
CC7*
Operating bank interleave read current;
All bank interleaving reads, I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = t
RC
D(I
CC
)-1*t
CK
(I
CC
); t
CK
=
t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RRD
= t
RRD
(I
CC
), t
RCD
= 1*t
CK
(I
CC
); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
TBD
3,000
2,820
2,640
mA
I
CC
specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.
Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in I
CC2P
(CKE LOW) mode.
** Value calculated refl ects all module ranks in this operating condition.
WV3HG128M72EEU-PD4
May 2006
Rev. 0
ADVANCED
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS & SPECIFICATIONS
V
CC
= +1.8V 0.1V
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Clock
Clock cycle time
CL = 6
t
CK (6)
TBD
TBD
ps
CL = 5
t
CK (5)
TBD
TBD
3,000
8,000
ps
CL = 4
t
CK (4)
TBD
TBD
3,750
8,000
3,750
8,000
5,000
8,000
ps
CL = 3
t
CK (3)
TBD
TBD
5,000
8,000
5,000
8,000
5,000
8,000
ps
CK high-level width
t
CH
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
CK low-level width
t
CL
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
Half clock period
t
HP
TBD
TBD
MIN
(t
CH,
t
CL
)
MIN
(t
CH,
t
CL
)
MIN
(t
CH,
t
CL
)
ps
Clock jitter
t
J
I
T
TBD
TBD
-125
125
-125
125
-125
125
ps
Data
DQ output access time from CK/CK#
t
AC
TBD
TBD
-450
+450
-500
+500
-600
+600
ps
Data-out high-impedance window from
CK/CK#
t
HZ
TBD
TBD
t
AC(MAX)
t
AC(MAX)
t
AC(MAX)
ps
Data-out low-impedance window from
CK/CK#
t
LZ
TBD
TBD
t
AC(MIN)
t
AC(MAX)
t
AC(MIN)
t
AC(MAX)
t
AC(MIN)
t
AC(MAX)
ps
DQ and DM input setup time relative to
DQS
t
DS
TBD
TBD
100
100
150
DQ and DM input hold time relative to DQS
t
DH
TBD
TBD
225
225
275
DQ and DM input pulse width (for each
input)
t
D
I
PW
TBD
TBD
0.35
0.35
0.35
t
CK
Data hold skew factor
t
QHS
TBD
TBD
340
400
450
ps
DQ...DQS hold, DQS to fi rst DQ to go
nonvalid, per access
t
QH
TBD
TBD
t
HP -
t
QHS
t
HP -
t
QHS
t
HP -
t
QHS
ps
Data valid output window (DVW)
t
DVW
TBD
TBD
t
QH -
t
DQSQ
t
QH -
t
DQSQ
t
QH -
t
DQSQ
ns
Data Strobe
DQS input high pulse width
t
DQSH
TBD
TBD
0.35
0.35
0.35
t
CK
DQS input low pulse width
t
DQSL
TBD
TBD
0.35
0.35
0.35
t
CK
DQS output access time from CK/CK#
t
DQSCK
TBD
TBD
-400
+400
-450
+450
-500
+500
ps
DQS falling edge to CK rising ... setup time
t
DSS
TBD
TBD
0.2
0.2
0.2
t
CK
DQS falling edge from CK rising ... hold
time
t
DSH
TBD
TBD
0.2
0.2
0.2
t
CK
DQS...DQ skew, DQS to last DQ valid, per
group,
per access
t
DQSQ
TBD
TBD
240
300
350
ps
DQS read preamble
t
RPRE
TBD
TBD
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
DQS read postamble
t
RPST
TBD
TBD
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
DQS write preamble setup time
t
WPRES
TBD
TBD
0
0
0
p s
DQS write preamble
t
WPRE
TBD
TBD
0.35
0.35
0.35
t
CK
DQS write postamble
t
WPST
TBD
TBD
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
Write command to fi rst DQS latching
transition
t
DQSS
TBD
TBD
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
t
CK
Address and control input pulse width for
each input
t
IPW
TBD
TBD
0.6
0.6
0.6
t
CK
Address and control input setup time
t
IS
TBD
TBD
200
250
250
ps
Address and control input hold time
t
IH
TBD
TBD
275
375
475
ps
Address and control input hold time
t
CCD
TBD
TBD
2
2
2
t
CK
* AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.
Continued on next page
WV3HG128M72EEU-PD4
May 2006
Rev. 0
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
V
CC
= +1.8V 0.1V
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Command and
Address
ACTIVE to ACTIVE (same bank) command
t
RC
TBD
TBD
55
55
55
ns
ACTIVE bank a to ACTIVE bank b command
t
RRD
TBD
TBD
7.5
7.5
7.5
ns
ACTIVE to READ or WRITE delay
t
RCD
TBD
TBD
15
15
15
ns
Four Bank Activate period
t
FAW
TBD
TBD
37.5
37.5
37.5
37.5
37.5
37.5
ns
ACTIVE to PRECHARGE command
t
RAS
TBD
TBD
45
70,000
45
70,000
45
70,000
ns
Internal READ to precharge command delay
t
RTP
TBD
TBD
7.5
7.5
7.5
ns
Write recovery time
t
WR
TBD
TBD
15
15
15
ns
Auto precharge write recovery + precharge
time
t
DAL
TBD
TBD
t
WR
+
t
RP
t
WR
+
t
RP
t
WR
+
t
RP
ns
Internal WRITE to READ command delay
t
WTR
TBD
TBD
7.5
7.5
10
ns
PRECHARGE command period
t
RP
TBD
TBD
15
15
15
ns
PRECHARGE ALL command period
t
RPA
TBD
TBD
t
RP+
t
CK
t
RP+
t
CK
t
RP+
t
CK
ns
LOAD MODE command cycle time
t
MRD
TBD
TBD
2
2
2
t
CK
CKE low to CK,CK# uncertainty
t
DELAY
TBD
TBD
t
IS
+ t
CK
+ t
IH
t
IS
+ t
CK
+ t
IH
t
IS
+ t
CK
+ t
IH
ns
Self Refresh
REFRESH to Active of Refresh to Refresh
command interfal
t
RFC
TBD
TBD
105
70,000
105
70,000
105
70,000
ns
Average periodic refresh interval
t
REF
I
TBD
TBD
7.8
7.8
7.8
s
Exit self refresh to non-READ command
t
XSNR
TBD
TBD
t
RFC
(MIN)
+ 10
t
RFC
(MIN)
+ 10
t
RFC
(MIN)
+ 10
ns
Exit self refresh to READ command
t
XSRD
TBD
TBD
200
200
200
t
CK
Exit self refresh timing reference
tI
SXR
TBD
TBD
t
IS
t
IS
t
IS
ps
ODT
ODT turn-on delay
t
AOND
TBD
TBD
2
2
2
2
2
2
t
CK
ODT turn-on
t
AON
TBD
TBD
t
AC
(MIN)
t
AC
(MAX)
+ 1000
t
AC
(MIN)
t
AC
(MAX)
+ 1000
t
AC
(MIN)
t
AC
(MAX)
+ 1000
ps
ODT turn-off delay
t
AOFD
TBD
TBD
2.5
2.5
2.5
2.5
2.5
2.5
t
CK
ODT turn-off
t
AOF
TBD
TBD
t
AC
(MIN)
t
AC
(MAX)
+ 600
t
AC
(MIN)
t
AC
(MAX)
+ 600
t
AC
(MIN)
t
AC
(MAX)
+ 600
ps
ODT turn-on (power-down mode)
t
AONPD
TBD
TBD
t
AC
(MIN) +
2000
2 x t
CK
+ t
AC
(MAX)
+ 1000
t
AC
(MIN) +
2000
2 x t
CK
+ t
AC
(MAX)
+ 1000
t
AC
(MIN) +
2000
2 x t
CK
+ t
AC
(MAX)
+ 1000
ps
ODT turn-off (power-down mode)
t
AOFPD
TBD
TBD
t
AC
(MIN) +
2000
2.5
x t
CK
+ t
AC
(MAX)
+ 1000
t
AC
(MIN) +
2000
2.5
x t
CK
+ t
AC
(MAX)
+ 1000
t
AC
(MIN) +
2000
2.5
x t
CK
+ t
AC
(MAX)
+ 1000
ps
ODT to power-down entry latency
t
ANPD
TBD
TBD
3
3
3
t
CK
ODT power-down exit latency
t
AXPD
TBD
TBD
8
8
8
t
CK
Power-Down
Exit active power-down to READ command,
MR[bit12=0]
t
XARD
TBD
TBD
2
2
2
t
CK
Exit active power-down to READ command,
MR[bit12=1]
t
XARDS
TBD
TBD
7 - AL
6 - AL
6 - AL
t
CK
A Exit precharge power-down to any non-
READ command.
t
XP
TBD
TBD
2
2
2
t
CK
CKE minimum high/low time
t
CKE
TBD
TBD
3
3
3
t
CK
* AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.
WV3HG128M72EEU-PD4
May 2006
Rev. 0
ADVANCED
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
3.81 (0.150)
MAX
1.10 (0.043)
0.90 (0.035)
PIN 1
67.75 (2.667)
67.45 (2.656)
0.60 (0.024)
TYP
0.45 (0.018)
TYP
PIN 199
PIN 200
PIN 2
2.504 (63.60)
1.00 (0.039)
TYP
TYP
BACK VIEW
47.40 (1.866)
TYP
11.40 (0.449)
TYP
4.2 (0.165)
TYP
1.0 (0.039)
TYP
1.80 (0.071) D
X2
6.0 (0.236)
TYP
2.0 (0.079)
TYP
4.10(0.161) (2X)
3.90(0.154)
2.10(0.083) (2X)
1.90(0.075)
30.15(1.187)
20.0 (0.787)
TYP
10.0 (0.394)
TYP
29.85(1.175)
2.70 (0.106)
4.10(0.161)
3.90(0.154)
TYP
PACKAGE DIMENSIONS FOR PD4
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
Tolerances: 0.13 (0.005) unless otherwise specifi ed
ORDERING INFORMATION FOR PD4
Part Number
Speed/Data Rate
CAS Latency
t
RCD
t
RP
Height*
WV3HG128M72EEU806PD4xxG**
400MHz/800Mb/s
6
6
6
30.00mm (1.81")TYP
WV3HG128M72EEU665PD4xxG**
333MHz/667Mb/s
5
5
5
30.00mm (1.81")TYP
WV3HG128M72EEU534PD4xxG
266MHz/533Mb/s
4
4
4
30.00mm (1.81")TYP
WV3HG128M72EEU403PD4xxG
200MHz/400Mb/s
3
3
3
30.00mm (1.81")TYP
** Consult factory for availability
NOTES:
RoHS product. ("G" = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualifi ed sourcing options.
(M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
WV3HG128M72EEU-PD4
May 2006
Rev. 0
ADVANCED
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PART NUMBERING GUIDE
WV 3 H G 128M 72 E E U xxx PD4 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
UNBUFFERED (UDIMM)
SPEED (Mb/s)
PACKAGE 200 PIN SO-DIMM
(P = JEDEC proposed pin-out)
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
WV3HG128M72EEU-PD4
May 2006
Rev. 0
ADVANCED
11
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
Document Title
1GB 128Mx72 DDR2 SDRAM UNBUFFERED, SO-DIMM w/PLL
DRAM DIE OPTIONS:
SAMSUNG: A-Die, will move to B-Die Q4'06
MICRON: U28A: A-Die, will move to U38Z: D-Die Q4'06 & U48B: E-Die Q2'07
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
May 2006
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