WV3HG2128M72AER-D6

September
2005 Rev. 0

ADVANCED*

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

2GB 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL

DESCRIPTION

The WV3HG2128M72AER is a 128Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of thirty six 128Mx4 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.

* This product is under development, is not qualifi ed or characterized and is subject to

change or cancellation without notice.

NOTE: Consult factory for availability of:

· Vendor source control options
· Industrial temperature option

FEATURES

240-pin, dual in-line memory module

Fast data transfer rates: PC2-4200 and PC2-3200

Utilizes 533 and 400 Mb/s DDR2 SDRAM
components

= V

CCQ

= 1.8V

0.1V

CCSPD

= 1.7V to 3.6V

JEDEC standard 1.8V I/O (SSTL_18-compatible)

Differential data strobe (DQS, DQS#) option

Four-bit

prefetch

architecture

DLL to align DQ and DQS transitions with CK

Multiple internal device banks for concurrent
operation

Supports duplicate output strobe (RDQS/RDQS#)

Programmable CAS# latency (CL): 3 and 4

Adjustable data-output drive strength

On-die

termination

(ODT)

Serial Presence Detect (SPD) with EEPROM

64ms: 8,192 cycle refresh

Gold edge contacts

Product

lead-free

RoHS

compliant

Dual

Rank

Package

option

· 240 Pin DIMM

· PCB 29.97mm (1.18")

OPERATING FREQUENCIES

PC2-3200

PC2-4200

Clock Speed

200MHz

266MHz

CL-t

RCD

-t

3-3-3

4-4-4

WV3HG2128M72AER-D6

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September
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PIN CONFIGURATION

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

REF

121

181

CCQ

122

DQ4

182

DQ0

123

DQ5

183

DQ1

124

184

125

DQS9

185

CK0

DQS0#

126

DQS9#

186

CK0#

DQS0

127

187

128

DQ6

188

DQ2

129

DQ7

189

DQ3

A10/AP

130

190

BA1

BA0

131

DQ12

191

CCQ

DQ8

CCQ

132

DQ13

192

RAS#

DQ9

WE#

133

193

S0#

CAS#

134

DQS10

194

CCQ

DQS1#

CCQ

135

DQS10#

195

ODT0

DQS1

CS1#

136

196

A13

ODT1

137

197

RESET#

CCQ

138

198

139

199

DQ36

DQ32

140

DQ14

200

DQ37

DQ10

DQ33

141

DQ15

201

DQ11

142

202

DQS13

DQS4#

143

DQ20

203

DQS13#

DQ16

DQS4

144

DQ21

204

DQ17

145

205

DQ38

DQ34

146

DQS11

206

DQ39

DQS2#

DQ35

147

DQS11#

207

DQS2

148

208

DQ44

DQ40

149

DQ22

209

DQ45

DQ18

DQ41

150

DQ23

210

DQ19

151

211

DQS14

DQS5#

152

DQ28

212

DQS14#

DQ24

DQS5

153

DQ29

213

DQ25

154

214

DQ46

DQ42

155

DQS12

215

DQ47

DQS3#

DQ43

156

DQS12#

216

DQS3

157

217

DQ52

DQ48

158

DQ30

218

DQ53

DQ26

DQ49

159

DQ31

219

DQ27

100

160

220

101

SA2

161

CB4

221

CB0

102

162

CB5

222

CB1

103

163

223

DQS15

104

DQS6#

164

DQS17

224

DQS15#

DQS8#

105

DQS6

165

DQS17#

225

DQS8

106

166

226

DQ54

107

DQ50

167

CB6

227

DQ55

CB2

108

DQ51

168

CB7

228

CB3

109

169

229

DQ60

110

DQ56

170

CCQ

230

DQ61

CCQ

111

DQ57

171

CKE1

231

CKE0

112

172

232

DQS16

113

DQS7#

173

233

DQS16#

114

DQS7

174

234

115

175

CCQ

235

DQ62

CCQ

116

DQ58

176

A12

236

DQ63

A11

117

DQ59

177

237

118

178

238

SPD

119

SDA

179

239

SA0

120

SCL

180

240

SA1

PIN NAMES

Pin Name

Function

A0-A13

Address Inputs

BA0,BA1

SDRAM Bank Address

DQ0-DQ63

Data Input/Output

CB0-CB7

Check Bits

DQS0-DQS17

Data strobes

DQS0#-DQS17#

Data strobes complement

ODT0, ODT1

On-die termination control

CK0,CK0#

Clock Inputs, positive line

CKE0, CKE1

Clock Enables

CS0#, CSI#

Chip Selects

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

SA0-SA2

SPD Address

Core and I/O Power (1.8V)

CCQ

I/O Power (1.8V)

Ground

A10/AP

Address input/ autoprecharge

REF

Input/Output Reference

SPD

SPD Power

Spare pins, No connect

WV3HG2128M72AER-D6

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September
2005 Rev. 0

FUNCTIONAL BLOCK DIAGRAM

Serial PD

SA0 SA1 SA2

SCL

SDA

CCSPD

CCQ

REF

Serial PD

DDR2 SDRAMs

P
L
L

CK0

CK0#

RESET#

PCK0-PCK6, PCK8, PCK9

CK : DDR2 SDRAMs

PCK0#-PCK6#, PCK8#, PCK9#

CK# : DDR2 SDRAMs

PCK7

CK : Register

PCK7#

CK# : Register

RCS1#

RCS0#

DQD

DQ1
DQ2
DQ3

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS0

DQS0#

DQS1

DQS1#

DQ8
DQ9

DQ10
DQ11

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS2

DQS2#

DQ16
DQ17
DQ18
DQ19

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS3

DQS3#

DQ24
DQ25
DQ26
DQ27

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS4

DQS4#

DQ32
DQ33
DQ34
DQ35

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS5

DQS5#

DQ40
DQ41
DQ42
DQ43

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS6

DQS6#

DQ48
DQ49
DQ50
DQ51

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS7

DQS7#

DQ56
DQ57
DQ58
DQ59

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS8

DQS8#

CB0
CB1
CB2
CB3

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS9

DQS9#

DQ4
DQ5
DQ6
DQ7

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS10

DQS10#

DQ12
DQ13
DQ14
DQ15

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS11

DQS11#

DQ20
DQ21
DQ22
DQ23

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS12

DQS12#

DQ28
DQ29
DQ30
DQ31

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS13

DQS13#

DQ36
DQ37
DQ38
DQ39

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS14

DQS14#

DQ44
DQ45
DQ46
DQ47

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS15

DQ15#

DQ52
DQ53
DQ54
DQ55

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS16

DQ16#

DQ60
DQ61
DQ62
DQ63

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

DQS17

DQ17#

CB4
CB5
CB6
CB7

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3

CS# DQS DQS#

1:4

R
E
G

S
T
E
R

RST#

BA0 - BA1

A0 - A13

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

RESET#

PCK7

PCK7#

RCS0# CS#: DDR2 SDRAMs

RCS1# CS#: DDR2 SDRAMs

RBA0-RBA1# BA0-BA1 : DDR2 SDRAMs

RA0-RA13 A0-A13 : DDR2 SDRAMs

RRAS# RAS# : DDR2 SDRAMs

RCAS# CAS#: DDR2 SDRAMs

RWE# WE#: DDR2 SDRAMs

RCKE0 CKE : DDR2 SDRAMs

RCKE1 CKE : DDR2 SDRAMs

RODT0 DDR2 SDRAMs

RODT1 DDR2 SDRAMs

CS0#

CS1#

NOTE: All resistor values are 22 ohms unless otherwise specifi ed.

WV3HG2128M72AER-D6

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White Electronic Designs

September
2005 Rev. 0

DC OPERATING CONDITIONS

All voltages referenced to V

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Supply voltage

1 .7

1 .8

1 .9

I/O Supply voltage

CCQ

1 .7

1 .8

1 .9

CCL

Supply voltage

CCL

1 .7

1 .8

1 .9

I/O Reference voltage

REF

0.49 x V

CCQ

0.50 x V

CCQ

0.51 x V

CCQ

I/O Termination voltage

REF

-0.04

REF

+ 0.04

Notes:
1. V

CCQ

must track each other. V

CCQ

must be less than or equal to V

2. V

REF

is expected to equal V

CCQ

/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V

REF

may not exceed ±1 percent of the DC

value. Peak-to-peak AC noise on V

REF

may not exceed ±2 percent of V

REF

. This measurement is to be taken at the nearest V

REF

bypass capacitor.

3. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

4. V

CCQ

tracks with V

; V

CCL

track with V

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

MIN

MAX

U nit

Voltage on V

pin relative to V

-1.0

2.3

CCQ

Voltage on V

CCQ

pin relative to V

-0.5

2.3

CCL

Voltage on V

CCL

pin relative to V

-0.5

2.3

, V

OUT

Voltage on any pin relative to V

-0.5

2.3

STG

Storage temperature

-55

100

°C

Input leakage current; Any input 0V<V

; V

REF

input

0V<V

<0.95V; Other pins not under test = 0V

Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
CK, CK#
DM

-5

Output leakage current;
0V<V

OUT

CCQ

; DQs and ODT are disable

DQ, DQS, DQS#

-10

VREF

REF

leakage current; V

REF

= Valid V

REF

level

-72

CAPACITANCE

TA=25°C, f=1MHz, V

CC =

CCQ =

1.8V

Parameter

Symbol

Min

Max

Unit

Input capacitance (A0 ~ A1 3, BA0 ~ BA1 ,RAS#,CAS#,WE#)

IN1

Input capacitance ( CKE0, CKE1), (ODT0, ODT1)

IN2

Input capacitance (CS0#, CS1#)

IN3

Input capacitance (CK0, CK0#)

IN4

Input capacitance (DQS0 ~ DQS8)

IN5

Input capacitance (DQ0 ~ DQ63), (CB0 ~ CB7)

OUT1

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OPERATING TEMPERATURE CONDITION

Parameter

Symbol

Rating

Units

Notes

Operating temperature

OPER

0 to 85

°C

1, 2

Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51 .2
2. At 0 - 85°C, operation temperature range, all DRAM specifi cation will be supported.

INPUT DC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Unit

Input High (Logic 1 ) Voltage

(DC)

REF

+ 0.1 25

REF

+ 0.300

Input Low (Logic 0) Voltage

(DC)

-0.300

REF

- 0.125

INPUT AC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Unit

AC Input High (Logic 1 ) Voltage

(AC)

REF

+ 0.250

AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533

(AC)

REF

- 0.250

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DDR2 I

SPECIFICATIONS AND CONDITIONS

Includes DDR2 SDRAM components only

Symbol

Proposed Conditions

534

403

Units

DD0*

Operating one bank active-precharge current;
t

= t

), t

= t

), t

RAS

= t

RAS

min(I

); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

2284

DD1*

Operating one bank active-read-precharge current;
I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

= t

), t

RAS

= t

RAS

min(I

), t

RCD

= t

RCD

);

CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus input
are switching; Data pattern is same as I

2554

DD2P**

Precharge power-down current;
All banks idle; t

= t

); CKE is LOW; Other control and address bus inputs are STABLE; Data bus

inputs are FLOATING

988

DD2Q**

Precharge quiet standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

1780

DD2N**

Precharge standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

1960

DD3P**

Active power-down current;
All banks open; t

= t

); CKE is LOW; Other control and address

bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0mA

1780

Slow PDN Exit MRS(12) = 1mA

1132

DD3N**

Active standby current;
All banks open; t

= t

), t

= t

); t

RAS

= t

RAS

max(I

); CKE is HIGH, CS# is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

2500

DD4W*

Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data

bus inputs are SWITCHING

2824

2644

DD4R*

Operating burst read current;
All banks open, Continuous burst reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as I

2914

2734

DD5**

Burst auto refresh current;
t

= t

); Refresh command at every t

RFC

) interval; CKE is HIGH, CS# is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

5740

DD6**

Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING

Normal

288

DD7*

Operating bank interleave read current;
All bank interleaving reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = t

D(I

)-1*t

); t

= t

), t

RRD

= t

RRD

), t

RCD

= 1*t

); CKE is HIGH, CS# is HIGH between valid commands; Address

bus inputs are STABLE during DESELECTs; Data bus imputs are switching.

4804

Notes:
I

specifi cation is based on SAMSUNG components. Other DRAM manufacturers specifi cation may be different.

* Value calculated as one module rank in this operating condition, and all other module ranks in I

DD2P

( CKE LOW) mode.

** Value calculated refl ects all module ranks in this operating condition.

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AC TIMING PARAMETERS & SPECIFICATIONS

0°C T

+70°C; V

CCQ

= + 1.8V ± 0.1V, V

= +1.8V ± 0.1V

AC CHARACTERISTICS

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNIT

Clock

Clock cycle time

CL = 4

CK (4)

3,750

8,000

5,000

8,000

CL = 3

CK (3)

5,000

8,000

5,000

8,000

CK high-level width

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

Half clock period

MIN (t

, t

)

MIN (t

, t

)

Clock jitter

JIT

TBD

Data

DQ output access time from CK/CK#

-500

+500

-600

+600

Data-out high-impedance window from CK/CK#

MAX

Data-out low-impedance window from CK/CK#

MIN

MAX

MIN

MAX

DQ and DM input setup time relative to DQS

100

150

DQ and DM input hold time relative to DQS

225

275

A DQ and DM input pulse width (for each input)

0.35

Data hold skew factor

QHS

400

450

DQ...DQS hold, DQS to fi rst DQ to go nonvalid, per access

- t

QHS

- t

QHS

Data valid output window (DVW)

DVW

- t

DQSQ

- t

DQSQ

Data Strobe

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS output access time from CK/CK#

DQSCK

-450

+450

-500

+500

DQS falling edge to CK rising ... setup time

DSS

0.2

DQS falling edge from CK rising ... hold time

DSH

0.2

DQS...DQ skew, DQS to last DQ valid, per group,
per access

DQSQ

300

350

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

DQS write preamble setup time

WPRES

DQS write preamble

WPRE

0.35

DQS write postamble

WPST

0.4

0.6

0.4

0.6

Write command to fi rst DQS latching transition

DQSS

WL - 0.25

WL + 0.25

WL - 0.25

WL + 0.25

Notes:

AC specifi cation is based on SAMSUNG components. Other DRAM manufacturers specifi cation may be different.

Continued on next page

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AC TIMING PARAMETERS (cont'd)

0°C T

+70°C; V

CCQ

= + 1.8V ± 0.1V, V

= +1.8V ± 0.1V

AC CHARACTERISTICS

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNIT

Command and

Address

Address and control input pulse width for each input

IPW

0.6

Address and control input setup time

250

Address and control input hold time

375

475

CAS# to CAS# command delay

CCD

ACTIVE to ACTIVE (same bank) command

ACTIVE bank a to ACTIVE bank b command

RRD

7.5

ACTIVE to READ or WRITE delay

RCD

Four Bank Activate period

FAW

37.5

ACTIVE to PRECHARGE command

RAS

70,000

Internal READ to precharge command delay

RTP

7.5

Write recovery time

Auto precharge write recovery + precharge time

DAL

+ t

Internal WRITE to READ command delay

WTR

7.5

PRECHARGE command period

PRECHARGE all command period

RPA

+ t

LOAD MODE command cycle time

MRD

CKE low to CK,CK# uncertainty

DELAY

4.375

Self Refresh

REFRESH to REFRESH command interval

RFC

127.5

70,000

127.5

70,000

Average periodic refresh interval

REFI

7.8

µs

Exit self refresh to non-READ command

XSNR

RFC

(MIN)

+ 10

RFC (MIN)

+ 10

Exit self refresh to READ command

XSRD

200

Exit self refresh timing reference

ISXR

ODT

ODT turn-on delay

AOND

ODT turn-on

AON

(MIN)

(MAX) +

1000

(MIN)

(MAX) +

1000

ODT turn-off delay

AOFD

2.5

ODT turn-off

AOF

(MIN)

(MAX) +

600

(MIN)

(MAX) +

600

ODT turn-on (power-down mode)

AONPD

(MIN) +

2000

2 x t

(MAX) +

1000

(MIN) +

2000

2 x t

(MAX) +

1000

ODT turn-off (power-down mode)

AOFPD

(MIN) +

2000

2.5 x t

(MAX) +

1000

(MIN) +

2000

2.5 x t

(MAX) +

1000

ODT to power-down entry latency

ANPD

ODT power-down exit latency

AXPD

Power-Down

Exit active power-down to READ command, MR[bit12=0]

XARD

Exit active power-down to READ command, MR[bit12=1]

XARDS

6 - AL

A Exit precharge power-down to any non-READ command.

CKE minimum high/low time

CKE

Notes:
AC specifi cation is based on SAMSUNG components. Other DRAM manufacturers specifi cation may be different.

WV3HG2128M72AER-D6

ADVANCED*

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

September
2005 Rev. 0

133.35 (5.25)

133.20 (5.244)

Front View

Back View

3.00

(0.118)

(4x)

63.00 (2.48)

TYP

55.00 (2.165)

TYP

PIN 240

PIN 121

5.0 (0.197) TYP.

PIN 1

PIN 120

2.50

(0.098)

1.00

(0.039)

0.20

(0.008)

Detail B

5.00 (0.197) TYP.

Detail A

1.69 0 (0.063)
1.40 (0.055)

0.85 (0.034)
0.75 (0.030)

Detail C

Detail A

4.843 (123.0)

TYP.

Detail C

3.00

(0.118)

(4X)

4.00

(0.157)

(4X)

5.175 (0.204)

(2x)

30.50 (1.201)
29.85 (1.175)

17.80 (0.700)

TYP.

10.00 (0.394)

TYP.

3.80 (0.150)

4.00 (0.157)

MAX

1.37 (0.054)
1.17 (0.046)

2.70 (0.106

2.30 (0.091)

PACKAGE DIMENSIONS FOR D6

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR D6

Part Number

Speed

CAS Latency

RCD

Height*

WV3HG2128M72AER534D6xG

266MHz/533Mb/s

29.97mm (1.18")

WV3HG2128M72AER403D6xG

200MHz/400Mb/s

29.97mm (1.18")

NOTES:

· RoHS products. ("G" = RoHS Compliant)

· Vendor specifi c part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"

in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualifi ed sourcing options.
(M = Micron, S = Samsung & consult factory for others)

· Consult factory for availability of industrial temperature (-40°C to 85°C) option

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