WV3HG2128M72EEU-AD4

February 2006
Rev. 0

ADVANCED*

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

2GB 2x128Mx72 DDR2 SDRAM UNBUFFERED, ECC w/PLL

DESCRIPTION

The WV3HG2128M72EEU is a 2x128Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 128Mx8 bit stacked BGA with
8 banks DDR2 Synchronous DRAMs in FBGA packages,
mounted on a 200-pin SO-DIMM FR4 substrate.

* This product is under development, is not qualifi ed or characterized and is subject to

change or cancellation without notice.

NOTE: Consult factory for availability of:

· Vendor source control options
· Industrial temperature option

FEATURES

200-pin, dual in-line memory module (SO-DIMM)

Support ECC error detection and correction

Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200

= V

CCQ

= 1.8V ±0.1V

1.8V I/O (SSTL_18-compatible)

Differential data strobe (DQS, DQS#) option

Differential clock inputs (CK, CK#)

Multiple internal device banks for concurrent
operation

Programmable CAS# latency (CL): 3, 4, 5 and 6

Adjustable data-output drive strength

On-die

termination

(ODT)

Posted CAS# latency: 0, 1, 2, 3 and 4

Serial Presence Detect (SPD) with EEPROM

64ms: 8,192 cycle refresh

Gold edge contacts

Dual

Rank

RoHS

compliant

Package

option

· 200 Pin SO-DIMM

· PCB 30.00mm (1.181") Max

OPERATING FREQUENCIES

PC2-6400*

PC2-5300*

PC2-4200

PC2-3200

Clock Speed

400MHz

333MHz

266MHz

200MHz

CL-t

RCD

-t

6-6-6

5-5-5

4-4-4

3-3-3

WV3HG2128M72EEU-AD4

February 2006
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NOTES:
SA2 does NOT connect to memory connector and is shown ONLY on Block Diagram
SA2 is tied LOW on memory module for all memory confi gurations

PIN CONFIGURATION

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

REF

DQ18

101

151

102

152

DQ0

DQ19

103

153

DQS5#

DQ4

DQ28

104

154

DM5

105

155

DQS5

DQ5

DQ29

106

156

DQ1

DQ24

107

157

108

158

DQ46

DQS0#

DQ25

109

159

DQ42

DM0

DM3

110

160

DQ47

DQS0

111

A10/AP

161

DQ43

112

BA1

162

DQS3#

113

BA0

163

DQ6

DQ30

114

164

DQ52

DQ2

DQS3

115

RAS#

165

DQ48

DQ7

DQ31

116

WE#

166

DQ53

DQ3

117

167

DQ49

118

CS0#

168

DQ26

119

CAS#

169

DQ12

CB4

120

ODT0

170

DM6

DQ8

DQ27

121

CS1#

171

DQS6#

DQ13

CB5

122

A13

172

DQ9

123

173

DQS6

124

174

DQ54

CB0

125

ODT1

175

DM1

DM8

126

176

DQ55

DQS1#

CB1

127

NC/CS3#

177

DQ50

128

CK#

178

DQS1

129

DQ32

179

DQ51

DQ14

CB6

130

180

DQ60

DQS8#

131

181

DQ15

CB7

132

DQ36

182

DQ61

DQ10

DQS8

133

DQ33

183

DQ56

134

DQ37

184

DQ11

135

DQS4#

185

DQ57

DQ20

CB2

136

186

DM7

CKE0

137

DQS4

187

DQ21

CB3

138

DM4

188

DQ62

DQ16

CKE1

139

189

DQS7#

140

190

DQ17

NC/CS2#

141

DQ34

191

DQS7

BA2

142

DQ38

192

DQ63

143

DQ35

193

DQ58

DM2

144

DQ39

194

SDA

DQS2#

A12

145

195

A11

146

196

SCL

DQS2

147

DQ40

197

DQ59

DQ22

148

DQ44

198

SA1

149

DQ41

199

SPD

DQ23

100

150

DQ45

200

SA0

PIN NAMES

Pin Name

Function

A0-A13

Address Inputs

A10/AP

Address Input/Auto Precharge

BA0 - BA2

SDRAM Bank Address

DQ0-DQ63

Data Input/Output

CB0-CB7

Check Bits

DQS0-DQS8

Data strobes

DQS0#-DQS8#

Data strobes negative

ODT0, ODT1

On-die termination control

CK,CK#

Clock inputs, positive/negative

CKE0, CKE1

Clock enable input

CS0#, CS1#

Chip select input

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

Core Power (1.8V)

Ground

SA0-SA1

SPD address

SDA

Serial Data Input/Output

REF

Input/Output Reference

DM0-DM8

Data-in mask

CCSPD

Serial EEPROM power supply

SCL

Serial Presence Detect(SPD) Clock Input

No Connect

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FUNCTIONAL BLOCK DIAGRAM

Serial PD

SA0 SA1

SA2

SCL

SDA

CCSPD

REF

Serial PD

DDR2 SDRAMs

PLL

CK0

CK#

CK0#

120

DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

CS1#
CS0#

DQS0

DQS0#

DM0

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

DQS4

DQS4#

DM4

DQ8
DQ9

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

DQS1

DQS1#

DM1

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

DQS5

DQS5#

DM5

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

DQS2

DQS2#

DM2

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

DQS6

DQS6#

DM6

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

DQS3

DQS3#

DM3

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

DQS7

DQS7#

DM7

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DM#

CS#

DQS DQS#

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

CS#

DQS DQS#

DQS8

DQS8#

DM8

CS0#

CS1#

BA0 - BA2

A0 - A13

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

CS0# : DDR2 SDRAMs

CS1# : DDR2 SDRAMs

BA0 - BA2 : DDR2 SDRAMs

A0 - A13 : DDR2 SDRAMs

RAS# : DDR2 SDRAMs

CAS# : DDR2 SDRAMs

WE# : DDR2 SDRAMs

CKE0 : DDR2 SDRAMs

CKE1 : DDR2 SDRAMs

ODT0 : DDR2 SDRAMs

ODT1 : DDR2 SDRAMs

NOTE: All resistor values are 22 ohms unless otherwise specifi ed.

WV3HG2128M72EEU-AD4

February 2006
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ADVANCED

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DC OPERATING CONDITIONS

All voltages referenced to V

Parameter

Symbol

Rating

Units

Notes

Min.

Type

Max.

Supply Voltage

1.7

1.8

1.9

I/O Reference Voltage

REF

0.49 x V

0.50 x V

0.51 x V

I/O Termination Voltage

REF

-0.04

REF

+0.04

Notes:
1 V

REF

is expected to equal V

/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V

REF

may not exceed +/-1 percent of the DC

value. Peak-to-peak AC noise on V

REF

may not exceed +/-2 percent of V

REF

. This measurement is to be taken at the nearest V

REF

bypass capacitor.

2. V

in sot applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

Max

Units

Voltage on V

pin relative to V

-1.0

2.3

, V

OUT

Voltage on any pin relative to V

-0.5

2.3

STG

Storage Temperature

-55

100

°C

CASE

Device operating Temperature

°C

Input leakage current; Any input 0V<V

; V

REF

input

0V<V

<0.95V; Other pins not under test = 0V

Command/Address,

RAS#, CAS#, WE#

-90

µA

CKE, CS#, ODT

-45

µA

CK,CK#

-10

µA

-10

Output leakage current; 0V<V

CCQ

; DQs and ODT are

disable

DQ, DQS, DQS#

-10

µA

VREF

REF

leakage current; V

REF

= Valid V

REF

level

-36

µA

WV3HG2128M72EEU-AD4

February 2006
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OPERATING TEMPERATURE CONDITION

Parameter

Symbol

Rating

Units

Notes

Operating temperature

TOPER

to 85°

°C

1, 2

Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
2. At 0°C - 85°C, operation temperature range, all DRAM specifi cation will be supported.

INPUT DC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Units

Input High (Logic 1) Voltage

(DC)

REF

+ 0.125

+ 0.300

Input Low (Logic 0) Voltage

(DC)

-0.300

REF

- 0.125

INPUT AC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Units

Input High (Logic 1) Voltage DDR2-400 & DDR2-533

(AC)

REF

+ 0.250

Input Low (Logic 1) Voltage DDR2-667

(AC)

REF

+ 0.200

Input Low (Logic 0) Voltage DDR2-400 & DDR2-533

(AC)

REF

- 0.250

Input Low (Logic 0) Voltage DDR2-667

(AC)

REF

- 0.200

INPUT/OUTPUT CAPACITANCE

= 25°C, f = 100MHz

Parameter

Symbol

Min

Max

Units

Input Capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)

IN1

Input Capacitance (CKE0, CKE1), (ODT0, ODT1)

IN2

Input Capacitance (CS0# ~ CS1#)

IN3

Input Capacitance (CK, CK#)

IN4

Input Capacitance (DM0 ~ DM8), (DQS0 ~ DQS8)

IN5

(665)

IN5

(534, 403)

Input Capacitance (DQ0 ~ DQ63), (CB0 ~ CB7)

OUT1

(665)

OUT1

(534, 403)

WV3HG2128M72EEU-AD4

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DDR2 I

SPECIFICATIONS AND CONDITIONS

Includes DDR2 SDRAM components only

0°C T

CASE

< +70°C; V

CCQ

= + 1.8V ± 0.1V, V

= +1.8V ± 0.1V

Symbol

Proposed Conditions

806

665

534

403

Units

CC0*

Operating one bank active-precharge current;
t

= t

), t

= t

), t

RAS

= t

RAS

min(I

); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1,218

1,173

1,128

CC1*

Operating one bank active-read-precharge current;
I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

= t

), t

RAS

= t

RAS

min(I

), t

RCD

= t

RCD

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as I

TBD

1,308

1,263

1,218

CC2P**

Precharge power-down current;
All banks idle; t

= t

); CKE is LOW; Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

TBD

516

CC2Q**

Precharge quiet standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs

are STABLE; Data bus inputs are FLOATING

TBD

1,020

930

CC2N**

Precharge standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs

are SWITCHING; Data bus inputs are SWITCHING

TBD

1,110

1,020

CC3P**

Active power-down current;
All banks open; t

= t

); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

TBD

840

750

Slow PDN Exit MRS(12) = 1

TBD

516

CC3N**

Active standby current;
All banks open; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH

between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING

TBD

1,200

1,110

CC4W*

Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus

inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1,803

1,578

1,443

CC4R*

Operating burst read current;
All banks open, Continuous burst reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address

bus inputs are SWITCHING; Data pattern is same as I

TBD

1,803

1,578

1,443

CC5**

Burst auto refresh current;
t

= t

); Refresh command at every t

RFC

) interval; CKE is HIGH, CS# is HIGH between

valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING

TBD

4,260

4,170

4,080

CC6**

Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING

TBD

108

CC7*

Operating bank interleave read current;
All bank interleaving reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = t

D(I

)-1*t

); t

), t

= t

), t

RRD

= t

RRD

), t

RCD

= 1*t

); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as I

CC4R

;

Refer to the following page for detailed timing conditions

TBD

3,108

2,928

2,748

Note: I

specifi cation is based on SAMSUNG components. Other DRAM Manufacturers specifi cation may be different.

* Value calculated as one module rank in this operation condition, and all other module ranks in I

CC2P

(CKE LOW) mode.

** Value calculated refl ects all module ranks in the operating condition.

WV3HG2128M72EEU-AD4

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AC TIMING PARAMETERS & SPECIFICATIONS

AC CHARACTERISTICS

806

665

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Clock

Clock cycle time

CL = 6

CK (6)

TBD

CL = 5

CK (5)

TBD

3,000

8,000

CL = 4

CK (4)

TBD

3,750

8,000

3,750

8,000

5,000

8,000

CL = 3

CK (3)

TBD

5,000

8,000

5,000

8,000

5,000

8,000

CK high-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

Half clock period

TBD

MIN (t

)

MIN (t

)

MIN (t

)

Clock jitter

TBD

-125

125

-125

125

-125

125

Data

DQ output access time from CK/CK#

TBD

-450

+450

-500

+500

-600

+600

Data-out high-impedance window from
CK/CK#

TBD

MAX

Data-out low-impedance window from
CK/CK#

TBD

MIN

MAX

MIN

MAX

MIN

MAX

DQ and DM input setup time relative to
DQS

TBD

100

150

DQ and DM input hold time relative to DQS

TBD

175

225

275

DQ and DM input pulse width (for each
input)

TBD

0.35

Data hold skew factor

QHS

TBD

340

400

450

DQ...DQS hold, DQS to fi rst DQ to go
nonvalid, per access

TBD

- t

QHS

- t

QHS

- t

QHS

Data valid output window (DVW)

DVW

TBD

- t

DQSQ

- t

DQSQ

- t

DQSQ

Data Strobe

DQS input high pulse width

DQSH

TBD

0.35

DQS input low pulse width

DQSL

TBD

0.35

DQS output access time from CK/CK#

DQSCK

TBD

-400

+400

-450

+450

-500

+500

DQS falling edge to CK rising ... setup time

DSS

TBD

0.2

DQS falling edge from CK rising ... hold
time

DSH

TBD

0.2

DQS...DQ skew, DQS to last DQ valid, per
group,
per access

DQSQ

TBD

240

300

350

DQS read preamble

RPRE

TBD

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

DQS write preamble setup time

WPRES

TBD

p s

DQS write preamble

WPRE

TBD

0.25

DQS write postamble

WPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

Write command to fi rst DQS latching
transition

DQSS

TBD

- 0.25

WL +

0.25

- 0.25

WL +

0.25

- 0.25

WL +

0.25

Address and control input pulse width for

each input

IPW

TBD

0.6

Address and control input setup time

TBD

200

250

350

Address and control input hold time

TBD

275

375

475

Address and control input hold time

CCD

TBD

AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.
Continued on next page

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AC TIMING PARAMETERS (cont'd)

AC CHARACTERISTICS

806

665

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Command and

Address

ACTIVE to ACTIVE (same bank) command

TBD

ACTIVE bank a to ACTIVE bank b command

RRD

TBD

7.5

ACTIVE to READ or WRITE delay

RCD

TBD

Four Bank Activate period

FAW

TBD

37.5

ACTIVE to PRECHARGE command

RAS

TBD

70,000

Internal READ to precharge command delay

RTP

TBD

7.5

Write recovery time

TBD

Auto precharge write recovery + precharge

time

DAL

TBD

Internal WRITE to READ command delay

WTR

TBD

7.5

PRECHARGE command period

TBD

PRECHARGE ALL command period

RPA

TBD

RP+

LOAD MODE command cycle time

MRD

TBD

CKE low to CK,CK# uncertainty

DELAY

TBD

IS+

Self Refresh

REFRESH to Active of Refresh to Refresh

command interval

RFC

TBD

127.5

70,000

127.5

70,000

127.5

70,000

Average periodic refresh interval

REF

TBD

7.8

µs

Exit self refresh to non-READ command

XSNR

TBD

RFC

(MIN)

+ 10

RFC

(MIN)

+ 10

RFC

(MIN)

+ 10

Exit self refresh to READ command

XSRD

TBD

200

Exit self refresh timing reference

SXR

TBD

ODT

ODT turn-on delay

AOND

TBD

ODT turn-on

AON

TBD

(MIN)

(MAX) +

1000

(MIN)

(MAX) +

1000

(MIN)

(MAX) +

1000

ODT turn-off delay

AOFD

TBD

2.5

ODT turn-off

AOF

TBD

(MIN)

(MAX) +

600

(MIN)

(MAX) +

600

(MIN)

(MAX) +

600

ODT turn-on (power-down mode)

AONPD

TBD

(MIN) +

2000

2 x t

+ t

(MAX) +

1000

(MIN) +

2000

2 x t

+ t

(MAX) +

1000

(MIN) +

2000

2 x t

+ t

(MAX) +

1000

ODT turn-off (power-down mode)

AOFPD

TBD

(MIN) +

2000

2.5 x

+ t

(MAX) +

1000

(MIN) +

2000

2.5 x

+ t

(MAX) +

1000

(MIN) +

2000

2.5 x

+ t

(MAX) +

1000

ODT to power-down entry latency

ANPD

TBD

ODT power-down exit latency

AXPD

TBD

Power-Down

Exit active power-down to READ command,

MR[bit12=0]

XARD

TBD

Exit active power-down to READ command,

MR[bit12=1]

XARDS

TBD

6 - AL

A Exit precharge power-down to any non-

READ command.

TBD

CKE minimum high/low time

CKE

TBD

AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.

WV3HG2128M72EEU-AD4

February 2006
Rev. 0

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

6.35 (0.250)

MAX

1.10 (0.043)
0.90 (0.035)

PIN 1

67.75 (2.667)
67.45 (2.656)

20.00 (0.787)

TYP

1.80 (0.071)

(2X)

0.60 (0.024)

TYP

0.45 (0.018)

TYP

PIN 199

PIN 200

PIN 2

FRONT VIEW

2.15 (0.085)

6.00 (0.236)

2.504 (63.60)

2.55 (0.100)

1.00 (0.039)

TYP

BACK VIEW

30.15 (1.187)
29.85 (1.175)

47.40 (1.866)

TYP

11.40 (0.449)

TYP

4.2 (0.165)

TYP

4.10 (0.161) (2X)
3.90 (0.154)

PACKAGE DIMENSIONS FOR AD4

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

Tolerances: ±0.13 (0.005) unless otherwise specifi ed

ORDERING INFORMATION FOR D4

Part Number

Clock/Data Rate

Speed

CAS

Latency

RCD

Height*

WV3HG2128M72EEU806AD4-xG

400MHz/800Mb/s

30.00mm (1.181")

WV3HG2128M72EEU665AD4-xG

333MHz/667Mb/s

30.00mm (1.181")

WV3HG2128M72EEU534AD4-xG

266MHz/533Mb/s

30.00mm (1.181")

WV3HG2128M72EEU403AD4-xG

200MHz/400Mb/s

30.00mm (1.181")

NOTES:

· RoHS product. ("G" = RoHS Compliant)

· Vendor specifi c part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "-x"

in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualifi ed sourcing options.
(M = Micron, S = Samsung & consult factory for others)

· Consult factory for availability of industrial temperature (-40°C to 85°C) option

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