WV3HG264M64EEU-D4

February 2006
Rev. 2

ADVANCED*

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

1GB 2x64Mx64 DDR2 SDRAM UNBUFFERED

DESCRIPTION

The WV3HG264M64EEU is a 2x64Mx64 Double Data
Rate DDR2 SDRAM high density SO-DIMM. This memory
module consists of sixteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.

* This product is under development, is not qualifi ed or characterized and is subject to

change or cancellation without notice.

NOTE: Consult factory for availability of:

· Vendor source control options
· Industrial temperature option

FEATURES

200-pin, dual in-line memory module (SO-DIMM)

Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200

Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components

= 1.8V ±0.1V

CCSPD

= 1.7V to 3.6V

JEDEC standard 1.8V I/O (SSTL_18-compatible)

Differential data strobe (DQS, DQS#) option

Four-bit

prefetch

architecture

DLL to align DQ and DQS transitions with CK

Multiple internal device banks for concurrent
operation

Supports duplicate output strobe (RDQS/RDQS#)

Programmable CAS# latency (CL): 3, 4, 5 and 6

Adjustable data-output drive strength

On-die

termination

(ODT)

Posted CAS# latency: 0, 1, 2, 3 and 4

Serial Presence Detect (SPD) with EEPROM

64ms: 8,192 cycle refresh

Gold edge contacts

Dual

Rank

RoHS

compliant

JEDEC

Package

option

· 200 Pin (SO-DIMM)

· PCB 30.00mm (1.181") TYP.

OPERATING FREQUENCIES

PC2-3200

PC2-4200

PC2-5300*

PC2-6400*

Clock Speed

200MHz

266MHz

333MHz

400MHz

CL-t

RCD

-t

3-3-3

4-4-4

5-5-5

6-6-6

* Consult factory for availability

WV3HG264M64EEU-D4

February 2006
Rev. 2

ADVANCED

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White Electronic Designs

PIN CONFIGURATION

PIN#

SYMBOL

PIN#

SYMBOL

PIN#

SYMBOL

PIN#

SYMBOL

REF

DQS2

101

151

DQ42

DM2

102

152

DQ46

103

153

DQ43

DQ4

104

154

DQ47

DQ0

DQ18

105

A10/AP

155

DQ5

DQ22

106

BA1

156

DQ1

DQ19

107

BA0

157

DQ48

DQ23

108

RAS#

158

DQ52

109

WE#

159

DQ49

DM0

110

CS0#

160

DQ53

DQS0#

DQ24

111

161

DQ28

112

162

DQS0

DQ25

113

CAS#

163

DQ6

DQ29

114

ODT0

164

CK1

115

CS1#

165

DQ7

116

A13

166

CK1#

DQ2

DM3

117

167

DQS6#

DQS3#

118

168

DQ3

119

ODT1

169

DQS6

DQ12

DQS3

120

170

DM6

121

171

DQ13

122

172

DQ8

DQ26

123

DQ32

173

DQ50

DQ30

124

DQ36

174

DQ54

DQ9

DQ27

125

DQ33

175

DQ51

DM1

DQ31

126

DQ37

176

DQ55

127

177

128

178

DQS1#

CKE0

129

DQS4#

179

DQ56

CK0

CKE1

130

DM4

180

DQ60

DQS1

131

DQS4

181

DQ57

CK0#

132

182

DQ61

133

183

134

DQ38

184

DQ10

135

DQ34

185

DM7

DQ14

136

DQ39

186

DQS7#

DQ11

137

DQ35

187

DQ15

138

188

DQS7

A12

139

189

DQ58

A11

140

DQ44

190

141

DQ40

191

DQ59

142

DQ45

192

DQ62

DQ16

143

DQ41

193

DQ20

144

194

DQ63

DQ17

145

195

SDA

DQ21

146

DQS5#

196

147

DM5

197

SCL

148

DQS5

198

SA0

DQS2#

149

199

CCSPD

100

150

200

SA1

PIN NAMES

Pin Name

Function

CK0,CK1

Clock Inputs, positive line

CK0#, CK1#

Clock Inputs, negative line

CKE0, CKE1

Clock Enables

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

CS0#, CS1#

Chip Selects

A0-A9, A11-A13

Address Inputs

A10/AP

Address Input/Auto precharge

BA0,BA1

SDRAM Bank Address

ODT0,ODT1

On-die termination control

SCL

Serial Presence Detect (SPD) Clock Input

SDA

SPD Data Input/Output

SA1,SA0

SPD address

DQ0-DQ63

Data Input/Output

DM0-DM7

Data Masks

DQS0-DQS7

Data strobes

DQS0#-DQS7#

Data strobes complement

Core and I/O Power

Ground

REF

Input/Output Reference

SPD

SPD Power

Spare pins, No connect

WV3HG264M64EEU-D4

February 2006
Rev. 2

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

FUNCTIONAL BLOCK DIAGRAM

ODT0

CKE0

CS1#

ODT1

CKE1

SPD

SA0

SCL

SDA

DDR2 SDRAMs, SPD

REF

DDR2 SDRAMs

DDR2 SDRAMs, V

CC,

CCQ

and V

CCL

SPD

Serial PD

SA1

SCL
A0
A1

A0 - A13

RAS#

DDR2 SDRAMs

CAS#

DDR2 SDRAMs

WE#

DDR2 SDRAMs

BA0 - BA1

DDR2 SDRAMs

± 5%

3 ohm + 5%?

CS0#

DQS1
DQS1#
DM1

CS0#

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQS
DQS#
DM

DQS0
DQS0#
DM0

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15

DQS

DQS5
DQS5#
DM5

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQS
DQS#
DM

DQS4
DQS4#
DM4

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15

DQS

DQS3
DQS3#
DM3

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQS
DQS#
DM

DQS2
DQS2#
DM2

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15

DQS
DQS#
DM

DQS7
DQS7#
DM7

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQS
DQS#
DM

DQS6
DQS6#
DM6

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15

DQS
DQS#
DM

O
D
T
0

C
K
E
0

CS1#

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQS
DQS#
DM

I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15

DQS

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQS
DQS#
DM

I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15

DQS
DQS#
DM

O
D
T
1

C
K
E
1

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQS
DQS#
DM

I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15

DQS

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQS
DQS#
DM

I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15

DQS
DQS#
DM

O
D
T
0

C
K
E
0

O
D
T
1

C
K
E
1

O
D
T
0

C
K
E
0

O
D
T
1

C
K
E
1

O
D
T
0

C
K
E
0

O
D
T
1

C
K
E
1

O
D
T
0

C
K
E
0

O
D
T
1

C
K
E
1

O
D
T
0

C
K
E
0

O
D
T
1

C
K
E
1

O
D
T
0

C
K
E
0

O
D
T
1

C
K
E
1

O
D
T
0

C
K
E
0

O
D
T
1

C
K
E
1

Notes :
1. All resistor values are 22 ohms ± 5% unless otherwise specified
2. BAx, Ax, RAS#, CAS#, WE# resistors : 3.0 Ohms ±5%.

* Wire per Clock Loading

Table/Wiring Diagrams

* Clock Wiring

Clock Input

DDR2 SDRAMs

*CK0/CK0#
*CK1/CK1#

8 DDR2 SDRAMs
8 DDR2 SDRAMs

3 ohm

CS0#

CS1#

CS0#

DQS#

CS1#

DQS#

CS0#

CS1#

CS0#

CS1#

CS0#

CS1#

CS0#

CS1#

CS0#

CS1#

WV3HG264M64EEU-D4

February 2006
Rev. 2

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

DC OPERATING CONDITIONS

All voltages referenced to V

Parameter

Symbol

Rating

Units

Notes

Min.

Type

Max.

Supply Voltage

1.7

1.8

1.9

I/O Reference Voltage

REF

0.49 x V

0.50 x V

0.51 x V

I/O Termination Voltage

REF

-0.04

REF

+0.04

Notes:
1. V

REF

is expected to equal V

CC/2

of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V

REF

may not exceed +/-1percent of the DC

value. Peak-to-peak AC noise on V

REF

may not exceed +/-2 percent of V

REF

. This measurement is to be taken at the nearest V

REF

bypass capacitor.

2. V

in sot applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

Max

Units

Voltage on V

pin relative to V

-0.5

2.3

, V

OUT

Voltage on any pin relative to V

-0.5

2.3

STG

Storage Temperature

-55

100

°C

Input leakage current; Any input 0V<V

; V

REF

input

0V<V

<0.95V; Other pins not under test = 0V

Command/Address,

RAS#, CAS#, WE#

-80

µA

CS#, CKE

-40

µA

CK, CK#

-40

µA

-10

µA

Output leakage current; 0V<V

; DQs and ODT are

disable

DQ, DQS, DQS#

-10

µA

VREF

REF

leakage current; V

REF

= Valid V

REF

level

-32

µA

INPUT/OUTPUT CAPACITANCE

= 25°C, f = 100MHz

Parameter

Symbol

Min

Max

Units

Input Capacitance (A0~A13, BA0~BA1, RAS#, CAS#, WE#)

IN1

Input Capacitance (CKE0, CKE1), (ODT0, ODT1)

IN2

Input Capacitance (CS0#, CS1#)

IN3

Input Capacitance (CK0, CK0#, CK1, CK1#)

IN4

Input Capacitance (DM0 ~ DM7), (DQS0 ~ DQS7)

IN5

(667)

IN5

(534)

Input Capacitance (DQ0 ~ DQ63)

OUT1

(667)

OUT1

(534)

WV3HG264M64EEU-D4

February 2006
Rev. 2

ADVANCED

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OPERATING TEMPERATURE CONDITION

Parameter

Symbol

Rating

Units

Notes

Operating temperature

TOPER

to 85°

°C

1, 2

Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
2. At 0°C - 85°C, operation temperature range, all DRAM specifi cation will be supported.

INPUT DC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Units

Input High (Logic 1) Voltage

(DC)

REF

+ 0.125

+ 0.300

Input Low (Logic 0) Voltage

(DC)

-0.300

REF

- 0.125

INPUT AC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Units

Input High (Logic 1) Voltage DDR2-400 & DDR2-533

(DC)

REF

+ 0.250

Input Low (Logic 1) Voltage DDR2-667

(DC)

REF

+ 0.200

Input Low (Logic 0) Voltage DDR2-400 & DDR2-533

(DC)

REF

- 0.250

Input Low (Logic 0) Voltage DDR2-667, DDR2-800 TBD

(DC)

REF

- 0.200

WV3HG264M64EEU-D4

February 2006
Rev. 2

ADVANCED

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SPECIFICATION

Symbol

Proposed Conditions

806

665

534

403

Units

CC0*

Operating one bank active-precharge;
t

= t

), t

= t

), t

RAS

= t

RAS

min(I

); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

744

704

CC1*

Operating one bank active-read-precharge;
I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

= t

), t

RAS

= t

RAS

min(I

); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as I

TBD

864

824

CC2P**

Precharge power-down current;
All banks idle; t

= t

); CKE is LOW; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

TBD

128

CC2Q**

Precharge quiet standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

STABLE; Data bus inputs are FLOATING

TBD

560

480

CC2N**

Precharge standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

STABLE; Data bus inputs are SWITCHING

TBD

640

560

CC3P**

Active power-down current;
All banks open; t

= t

); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

TBD

480

Slow PDN Exit MRS(12) = 1

TBD

192

CC3N**

Active standby current;
All banks open; t

= t

), t

= t

CC,

RAS

= t

RAS

min(I

); CKE is HIGH, CS# is HIGH between

valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING

TBD

880

800

CC4W*

Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus

inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1184

1024

944

CC4R*

Operating burst read current;
All banks open, Continuous burst reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus

inputs are SWITCHING; Data pattern is same as I

TBD

1224

1064

944

CC5**

Burst auto refresh current;
t

= t

); Refresh command at every t

RFC

) interval; CKE is HIGH, CS# is HIGH between

valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING

TBD

2400

2240

CC6**

Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING

Normal

TBD

128

CC7*

Operating bank interleave read current;
All bank interleaving reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = t

D(I

)-1*t

); t

), t

= t

), t

RRD

= t

RRD

), t

RCD

= 1*t

); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.

TBD

1824

specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.

Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated refl ects all module ranks in this operating condition.

WV3HG264M64EEU-D4

February 2006
Rev. 2

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

AC TIMING PARAMETERS & SPECIFICATIONS

AC CHARACTERISTICS

806

665

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Clock

Clock cycle time

CL = 6

CK (6)

TBD

CL = 5

CK (5)

TBD

3,000

8,000

CL = 4

CK (4)

TBD

3,750

8,000

3,750

8,000

5,000

8,000

CL = 3

CK (3)

TBD

5,000

8,000

5,000

8,000

5,000

8,000

CK high-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

Half clock period

TBD

MIN (t

)

MIN (t

)

MIN (t

)

Clock jitter

TBD

-125

125

-125

125

-125

125

Data

DQ output access time from CK/CK#

TBD

-450

+450

-500

+500

-600

+600

Data-out high-impedance window from
CK/CK#

TBD

MAX

Data-out low-impedance window from
CK/CK#

TBD

MIN

MAX

MIN

MAX

MIN

MAX

DQ and DM input setup time relative to
DQS

TBD

100

150

DQ and DM input hold time relative to DQS

TBD

225

275

DQ and DM input pulse width (for each
input)

TBD

0.35

Data hold skew factor

QHS

TBD

340

400

450

DQ...DQS hold, DQS to fi rst DQ to go
nonvalid, per access

TBD

- t

QHS

- t

QHS

- t

QHS

Data valid output window (DVW)

DVW

TBD

- t

DQSQ

- t

DQSQ

- t

DQSQ

Data Strobe

DQS input high pulse width

DQSH

TBD

0.35

DQS input low pulse width

DQSL

TBD

0.35

DQS output access time from CK/CK#

DQSCK

TBD

-400

+400

-450

+450

-500

+500

DQS falling edge to CK rising ... setup time

DSS

TBD

0.2

DQS falling edge from CK rising ... hold
time

DSH

TBD

0.2

DQS...DQ skew, DQS to last DQ valid, per
group,
per access

DQSQ

TBD

240

300

350

DQS read preamble

RPRE

TBD

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

DQS write preamble setup time

WPRES

TBD

p s

DQS write preamble

WPRE

TBD

0.35

DQS write postamble

WPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

Write command to fi rst DQS latching
transition

DQSS

TBD

- 0.25

WL +

0.25

- 0.25

WL +

0.25

- 0.25

WL +

0.25

Address and control input pulse width for

each input

IPW

TBD

0.6

Address and control input setup time

TBD

200

250

350

Address and control input hold time

TBD

275

375

475

Address and control input hold time

CCD

TBD

AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.
Continued on next page

WV3HG264M64EEU-D4

February 2006
Rev. 2

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

AC TIMING PARAMETERS (cont'd)

AC CHARACTERISTICS

800

665

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Command and

Address

ACTIVE to ACTIVE (same bank) command

TBD

ACTIVE bank a to ACTIVE bank b command

RRD

TBD

7.5

ACTIVE to READ or WRITE delay

RCD

TBD

Four Bank Activate period

FAW

TBD

37.5

ACTIVE to PRECHARGE command

RAS

TBD

70,000

Internal READ to precharge command delay

RTP

TBD

7.5

Write recovery time

TBD

Auto precharge write recovery + precharge

time

DAL

TBD

Internal WRITE to READ command delay

WTR

TBD

7.5

PRECHARGE command period

TBD

PRECHARGE ALL command period

RPA

TBD

RP+

LOAD MODE command cycle time

MRD

TBD

CKE low to CK,CK# uncertainty

DELAY

TBD

+ t

Self Refresh

REFRESH to Active of Refresh to Refresh

command internal

RFC

TBD

127.5

70,000

127.5

70,000

127.5

70,000

Average periodic refresh interval

REF

TBD

7.8

µs

Exit self refresh to non-READ command

XSNR

TBD

RFC

(MIN)

+ 10

RFC

(MIN)

+ 10

RFC

(MIN)

+ 10

Exit self refresh to READ command

XSRD

TBD

200

Exit self refresh timing reference

SXR

TBD

ODT

ODT turn-on delay

AOND

TBD

ODT turn-on

AON

TBD

(MIN)

(MAX) +

1000

(MIN)

(MAX) +

1000

(MIN)

(MAX) +

1000

ODT turn-off delay

AOFD

TBD

2.5

ODT turn-off

AOF

TBD

(MIN)

(MAX) +

600

(MIN)

(MAX) +

600

(MIN)

(MAX) +

600

ODT turn-on (power-down mode)

AONPD

TBD

(MIN) +

2000

2 x t

+ t

(MAX) +

1000

(MIN) +

2000

2 x t

+ t

(MAX) +

1000

(MIN) +

2000

2 x t

+ t

(MAX) +

1000

ODT turn-off (power-down mode)

AOFPD

TBD

(MIN) +

2000

2.5 x

+ t

(MAX) +

1000

(MIN) +

2000

2.5 x

+ t

(MAX) +

1000

(MIN) +

2000

2.5 x

+ t

(MAX) +

1000

ODT to power-down entry latency

ANPD

TBD

ODT power-down exit latency

AXPD

TBD

Power-Down

Exit active power-down to READ command,

MR[bit12=0]

XARD

TBD

Exit active power-down to READ command,

MR[bit12=1]

XARDS

TBD

7 - AL

6 - AL

A Exit precharge power-down to any non-

READ command.

TBD

CKE minimum high/low time

CKE

TBD

AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.

WV3HG264M64EEU-D4

February 2006
Rev. 2

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

3.80 (0.150)

MAX

1.10 (0.043)
0.90 (0.035)

PIN 1

67.75 (2.667)
67.45 (2.656)

20.00 (0.787)

TYP

1.80 (0.071)

(2X)

0.60 (0.024)

TYP

0.45 (0.018)

TYP

PIN 199

PIN 200

PIN 2

2.15 (0.085)

6.00 (0.236)

63.60 (2.504)

2.55 (0.100)

1.00 (0.039)

TYP

BACK VIEW

FRONT VIEW

30.15 (1.187)
29.85 (1.175)

47.40 (1.866)

TYP

11.40 (0.449)

TYP

4.2 (0.165)

TYP

4.10(0.161) (2X)
3.90(0.154)

PACKAGE DIMENSIONS FOR D4

** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR D4

Part Number

Clock/Data Rate

Speed

CAS Latency

RCD

Height**

WV3HG264M64EEU806D4xG*

400MHz/800Mb/s

30.00mm (1.181") TYP

WV3HG264M64EEU665D4xG*

333MHz/667Mb/s

30.00mm (1.181") TYP

WV3HG264M64EEU534D4xG

266MHz/533Mb/s

30.00mm (1.181") TYP

WV3HG264M64EEU403D4xG

200MHz/400Mb/s

30.00mm (1.181") TYP

* Consult factory for availability
NOTES:

· RoHS product. ("G" = RoHS Compliant)

· Vendor specifi c part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"

in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualifi ed sourcing options.
(M = Micron, S = Samsung & consult factory for others)

· Consult factory for availability of industrial temperature (-40°C to 85°C) option

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