WV3HG264M64EEU-D6
December 2005
Rev. 0
ADVANCED*
1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
1GB 2x64Mx64 DDR2 SDRAM UNBUFFERED
DESCRIPTION
The WV3HG264M64EEU is a 2x64Mx64 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of sixteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
* This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
Vendor source control options
Industrial temperature option
FEATURES
240-pin, dual in-line memory module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
Utilizes 800*, 667*, 533 and 400 MT/s DDR2
SDRAM components
V
CC
= V
CCQ
= 1.8V 0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, 5 and 6
On-die
termination
(ODT)
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
Dual
Rank
RoHS
compliant
Package
option
240 Pin DIMM
PCB 30.00mm (1.181") TYP
OPERATING FREQUENCIES
PC2-3200
PC2-4200
PC2-5300*
PC2-6400*
Clock Speed
200MHz
266MHz
333MHz
400MHz
CL-t
RCD
-t
RP
3-3-3
4-4-4
5-5-5
6-6-6
* Consult factory for availability
WV3HG264M64EEU-D6
December 2005
Rev. 0
ADVANCED
2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PIN CONFIGURATION
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
1
V
REF
61
A4
121
V
SS
181
V
CCQ
2
V
SS
62
V
CCQ
122
DQ4
182
A3
3
DQ0
63
A2
123
DQ5
183
A1
4
DQ1
64
V
CC
124
V
SS
184
V
CC
5
V
SS
65
V
SS
125
DM0
185
CK0
6
DQS0#
66
V
SS
126
NC
186
CK0#
7
DQS0
67
V
CC
127
V
SS
187
V
CC
8
V
SS
68
NC
128
DQ6
188
A0
9
DQ2
69
V
CC
129
DQ7
189
V
CC
10
DQ3
70
A10/AP
130
V
SS
190
BA1
11
V
SS
71
BA0
131
DQ12
191
V
CCQ
12
DQ8
72
V
CCQ
132
DQ13
192
RAS#
13
DQ9
73
WE#
133
V
SS
193
CS0#
14
V
SS
74
CAS#
134
DM1
194
V
CCQ
15
DQS1#
75
V
CCQ
135
NC
195
ODT0
16
DQS1
76
CS1#
136
V
SS
196
A13
17
V
SS
77
ODT1
137
CK1
197
V
CC
18
NC
78
V
CCQ
138
CK1#
198
V
SS
19
NC
79
V
SS
139
V
SS
199
DQ36
20
V
SS
80
DQ32
140
DQ14
200
DQ37
21
DQ10
81
DQ33
141
DQ15
201
V
SS
22
DQ11
82
V
SS
142
V
SS
202
DM4
23
V
SS
83
DQS4#
143
DQ20
203
NC
24
DQ16
84
DQS4
144
DQ21
204
V
SS
25
DQ17
85
V
SS
145
V
SS
205
DQ38
26
V
SS
86
DQ34
146
DM2
206
DQ39
27
DQS2#
87
DQ35
147
NC
207
V
SS
28
DQS2
88
V
SS
148
V
SS
208
DQ44
29
V
SS
89
DQ40
149
DQ22
209
DQ45
30
DQ18
90
DQ41
150
DQ23
210
V
SS
31
DQ19
91
V
SS
151
V
SS
211
DM5
32
V
SS
92
DQS5#
152
DQ28
212
NC
33
DQ24
93
DQS5
153
DQ29
213
V
SS
34
DQ25
94
V
SS
154
V
SS
214
DQ46
35
V
SS
95
DQ42
155
DM3
215
DQ47
36
DQS3#
96
DQ43
156
NC
216
V
SS
37
DQS3
97
V
SS
157
V
SS
217
DQ52
38
V
SS
98
DQ48
158
DQ30
218
DQ53
39
DQ26
99
DQ49
159
DQ31
219
V
SS
40
DQ27
100
V
SS
160
V
SS
220
CK2
41
V
SS
101
SA2
161
NC
221
CK2#
42
NC
102
NC
162
NC
222
V
SS
43
NC
103
V
SS
163
V
SS
223
DM6
44
V
SS
104
DQS6#
164
NC
224
NC
45
NC
105
DQS6
165
NC
225
V
SS
46
DQS8
106
V
SS
166
V
SS
226
DQ54
47
V
SS
107
DQ50
167
NC
227
DQ55
48
NC
108
DQ51
168
NC
228
V
SS
49
NC
109
V
SS
169
V
SS
229
DQ60
50
V
SS
110
DQ56
170
V
CCQ
230
DQ61
51
V
CCQ
111
DQ57
171
CKE1
231
V
SS
52
CKE0
112
V
SS
172
V
CC
232
DM7
53
V
CC
113
DQS7#
173
NC
233
NC
54
NC
114
DQS7
174
NC
234
V
SS
55
NC
115
V
SS
175
V
CCQ
235
DQ62
56
V
CCQ
116
DQ58
176
A12
236
DQ63
57
A11
117
DQ59
177
A9
237
V
SS
58
A7
118
V
SS
178
V
CC
238
V
CCSPD
59
V
CC
119
SDA
179
A8
239
SA0
60
A5
120
SCL
180
A6
240
SA1
PIN NAMES
Pin Name
Function
A0-A13
Address Input
BA0, BA1
Bank Address
DQ0 ~ DQ63
Data Input/output
DQS0 ~ DQS7
Data Strobe
DQS0# ~ DQS7#
Data Strobe negative
ODT0, ODT1
On Die Termination
CK0,CK0# - CK2,
CK2#
Clock Input
CKE0, CKE1
Clock enable input
CS0#, CS1#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
V
CC
Voltage Supply (1.8V0.1V)
V
CCQ
I/O Power (1.8V)
V
SS
Ground
SA0 ~ SA2
SPD Address
SDA
Serial Data I/O
SCL
Serial clock
DM(0-7)
Data Masks
A10/AP
Address input/Auto precharge
V
REF
I/O reference supply
V
CCSPD
Serial EEPROM
NC
No Connect
WV3HG264M64EEU-D6
December 2005
Rev. 0
ADVANCED
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
SA0
SA1
SA2
SCL
SDA
WP
V
CCSPD
V
CC
/V
CCQ
V
REF
V
SS
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
RDQS
CS#
DQS
DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS1#
CS0#
DQS0
DQS0#
DM0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DQS4#
DM4
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS1#
DM1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DQS5#
DM5
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS2#
DM2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS6
DQS6#
DM6
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DQS3#
DM3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS7
DQS7#
DM7
CS0#
CS1#
BA0 - BA1
A0 - A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
S0# : DDR2 SDRAMs
S1# : DDR2 SDRAMs
BA0 - RBA1 : DDR2 SDRAMs
A0 - A13 : DDR2 SDRAMs
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE : DDR2 SDRAMs
CKE : DDR2 SDRAMs
ODT : DDR2 SDRAMs
ODT : DDR2 SDRAMs
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
A0
WP
A1
A2
Serial PD
*Clock Wiring
*Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ, DM, DQS, DQS# resistors: 5.1 Ohms +/- 5%
2. BAx, Ax, RAS#, CAS#, WE# resistors: 5.1 Ohms +/- 5%
Clock
Input
DDR2 SDRAMs
*CK0/CK0#
*CK1/CK1#
*CK2/CK2#
4 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
NOTE: All resistor values are 22 ohms unless otherwise specifi ed.
WV3HG264M64EEU-D6
December 2005
Rev. 0
ADVANCED
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DC OPERATING CONDITIONS
All Voltages Referenced to V
SS
Parameter
Symbol
Rating
Units
Notes
Min.
Type
Max.
Supply Voltage
V
CC
1.7
1.8
1.9
V
1
I/O Supply Voltage
V
CCQ
1.7
1.8
1.9
V
4
VCCL Supply Voltage
V
CCL
1.7
1.8
1.9
V
4
I/O Reference Voltage
V
REF
0.49*V
CCQ
0.50*V
CCQ
0.51*V
CCQ
V
2
I/O Termination Voltage
V
TT
V
REF
-0.04
V
REF
V
REF
+0.04
V
3
Notes:
1. V
CC
and V
CCQ
must track each other. V
CCQ
must be less than or equal to V
CC
.
2. V
REF
is expected to equal V
CCQ/2
of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V
REF
may not exceed +/- percent of the DC
value. Peak-to-peak AC noise on V
REF
may not exceed +/-2 percent of V
REF
. This measurement is to be taken at the nearest V
REF
bypass capacitor.
3. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
4. V
CCQ
tracks with V
CC
; V
CCL
track with V
CC
.
ABSOLUTE MAXIMUM RATINGS
SSTL_1.8V
Symbol
Parameter
Min
Max
Unit
V
CC
Voltage on V
CC
pin relative to V
SS
- 1.0
2.3
V
V
CCQ
Voltage on V
CCQ
pin relative to V
SS
- 0.5
2.3
V
V
CCL
Voltage on V
CCL
pin relative to V
SS
- 0.5
2.3
V
V
IN
, V
OUT
Voltage on any pin relative to V
SS
- 0.5
2.3
V
T
STG
Storage Temperature
-55
100
C
T
CASE
Device operating Temperature
0
85
C
I
L
Input leakage current; Any input 0V<V
IN
<V
CC
;
V
REF
input 0V<V
IN
<<0.95; Other pins not
under test = 0V
Command/Address, RAS#,
CAS#, WE#
-80
80
uA
CS#, CKE
-40
40
uA
CK, CK#
-30
30
uA
DM
-10
10
uA
I
OZ
Output leakage current; 0V<V
OUT
<V
CCQ
; DQs
and ODT are disable
DQ, DQS, DQS#
-10
10
uA
I
VREF
V
REF
leakage current; V
REF
= Valid V
REF
level
-32
32
uA
WV3HG264M64EEU-D6
December 2005
Rev. 0
ADVANCED
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating Temperature
TOPER
0C to 85C
C
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2.
2. At 0 - 85
C, operation temperature range, all DRAM specifi cation will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Symbol
Min
Max
Units
Input High (Logic 1) Voltage
V
IH(DC)
VREF + 0.125
VREF + 0.300
V
Input Low (Logic 0) Voltage
V
IL(DC)
-0.300
VREF - 0.125
V
INPUT AC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Symbol
Min
Max
Units
AC Input High (Logic 1) Voltage
V
IH(AC)
VREF+ 0.250
V
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
V
IL(AC)
VREF - 0.250
V
AC Input Low (Logic 0) Voltage DDR2-667, DDR2-800 (TBD)
V
IL(AC)
VREF - 0.200
V
CAPACITANCE
T
A
= 25C, f = 1MHz, V
CC
= V
CCQ
= 1.8V
Parameter
Symbol
Min
Max
Units
Input Capacitance: (A0 ~ A13 , BA0 ~ BA1, RAS#, CAS#, WE#)
C
IN1
20
36
pF
Input Capacitance: (CKE0, CKE1), (ODT0, ODT1)
C
IN2
12
20
pF
Input Capacitance: (CS0#, CS1#)
C
IN3
12
20
pF
Input Capacitance: (CK0, CK0# ~ CK2, CK2#)
C
IN4
10
16
pF
Input Capacitance: (DM0 ~ DM7)
C
IN6 (E6)
9
11
pF
C
IN6 (D5)
9
12
pF
Input Capacitance: (DQ0 ~ DQ63)
C
OUT1 (E6)
9
11
pF
C
OUT1 (D5)
9
12
pF
WV3HG264M64EEU-D6
December 2005
Rev. 0
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DDR2 I
CC
SPECIFICATIONS AND CONDITIONS
Symbol
Proposed Conditions
806
665
534
403
Units
I
CC0*
Operating one bank active-precharge current;
t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS
min(I
CC
); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
744
704
704
mA
I
CC1*
Operating one bank active-read-precharge current;
I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS MIN
(I
CC
),
t
RCD
= t
RCD
(I
CC
); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as I
CC4W
TBD
864
824
824
mA
I
CC2P**
Precharge power-down current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
TBD
128
128
128
mA
I
CC2Q**
Precharge quiet standby current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
TBD
560
480
480
mA
I
CC2N**
Precharge standby current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
640
560
560
mA
I
CC3P**
Active power-down current;
All banks open; t
CK
= t
CK
(I
CC
); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit MRS(12) = 0
TBD
480
480
480
mA
Slow PDN Exit MRS(12) = 1
TBD
192
192
192
mA
I
CC3N**
Active standby current;
All banks open; t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS MIN
(I
CC
); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
TBD
880
800
800
mA
I
CC4W**
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RAS
=
t
RAS MAX
(I
CC
), t
RP
= t
RP
(I
CC
); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
1184
1024
944
mA
I
CC4R*
Operating burst read current;
All banks open, Continuous burst reads, I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RAS
= t
RAS MAX
(I
CC
), t
RP
= t
RP
(I
CC
); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as I
CC4W
TBD
1224
1064
944
mA
I
CC5B**
Burst auto refresh current;
t
CK
= t
CK
(I
CC
); Refresh command at every t
RFC
(I
CC
) interval; CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
TBD
2400
2240
2240
mA
I
CC6*
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
FLOATING
Normal
TBD
128
128
128
mA
I
CC7*
Operating bank interleave read current;
All bank interleaving reads, I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = t
RC
D(I
CC
)-1*t
CK
(I
CC
); t
CK
=
t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RRD
= t
RRD
(I
CC
), t
RCD
= 1*t
CK
(I
CC
); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
switching.
TBD
1824
1824
1824
mA
* Value calculated as one module rank in thes operating condition, and all other module ranks in I
CC2P
(CKE LOW) mode.
** Value calculated refl ects all module ranks in this operating condition
NOTES:
I
CC
specifi cations were calculated using SAMSUNG components. Other manufactures DRAMs may have different values.
WV3HG264M64EEU-D6
December 2005
Rev. 0
ADVANCED
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS
0C T
CASE
< +85C; V
CCQ
= + 1.8V 0.1V, V
CC
= +1.8V 0.1V
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Clock
Clock cycle time
CL = 6
t
CK (6)
TBD
TBD
ps
CL = 5
t
CK (5)
TBD
TBD
3000
8000
ps
CL = 4
t
CK (4)
TBD
TBD
3750
8000
3,750
8,000
5,000
8,000
ps
CL = 3
t
CK (3)
TBD
TBD
5680
8000
5,000
8,000
5,000
8,000
ps
CK high-level width
t
CH
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
CK low-level width
t
CL
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
Half clock period
t
HP
TBD
TBD
MIN (t
CH
,
t
CL
)
MIN (t
CH
,
t
CL
)
MIN (t
CH
,
t
CL
)
ps
Data
DQ output access time from CK/CK#
t
AC
TBD
TBD
-450
+450
-500
+500
-600
+600
ps
Data-out high-impedance window from
CK/CK#
t
HZ
TBD
TBD
t
AC
(MAX)
t
AC
(MAX)
t
AC
(MAX)
ps
Data-out low-impedance window from
CK/CK#
t
LZ
TBD
TBD
t
AC
(MIN)
t
AC
(MAX)
t
AC
(MIN)
t
AC
(MAX)
t
AC
(MIN)
t
AC
(MAX)
ps
DQ and DM input setup time relative to DQS
t
DS
TBD
TBD
100
100
150
ps
DQ and DM input hold time relative to DQS
t
DH
TBD
TBD
225
225
275
ps
A DQ and DM input pulse width (for each
input)
t
DIPW
TBD
TBD
0.35
0.35
0.35
t
CK
Data hold skew factor
t
QHS
TBD
TBD
340
400
450
ps
DQ...DQS hold, DQS to fi rst DQ to go
nonvalid, per access
t
QH
TBD
TBD
t
HP
- t
QHS
t
HP
- t
QHS
t
HP
- t
QHS
ps
Data valid output window (DVW)
t
DVW
TBD
TBD
t
QH
- t
DQSQ
t
QH
- t
DQSQ
t
QH
- t
DQSQ
ns
Data Strobe
DQS input high pulse width
t
DQSH
TBD
TBD
0.35
0.35
0.35
t
CK
DQS input low pulse width
t
DQSL
TBD
TBD
0.35
0.35
0.35
t
CK
DQS output access time from CK/CK#
t
DQSCK
TBD
TBD
-400
+400
-450
+450
-500
+500
ps
DQS falling edge to CK rising ... setup time
t
DSS
TBD
TBD
0.2
0.2
0.2
t
CK
DQS falling edge from CK rising ... hold time
t
DSH
TBD
TBD
0.2
0.2
0.2
t
CK
DQS...DQ skew, DQS to last DQ valid, per
group,
per access
t
DQSQ
TBD
TBD
240
300
350
ps
DQS read preamble
t
RPRE
TBD
TBD
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
DQS read postamble
t
RPST
TBD
TBD
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
DQS write preamble setup time
t
WPRES
TBD
TBD
0
0
0
ps
DQS write preamble
t
WPRE
TBD
TBD
0.35
0.35
0.35
t
CK
DQS write postamble
t
WPST
TBD
TBD
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
Write command to fi rst DQS latching
transition
t
DQSS
TBD
TBD
WL
- 0.25
WL +
0.25
WL
- 0.25
WL +
0.25
WL
- 0.25
WL +
0.25
t
CK
Address and control input pulse width for
each input
t
IPW
TBD
TBD
0.6
0.6
0.6
t
CK
NOTE:
AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.
Continued on next page
WV3HG264M64EEU-D6
December 2005
Rev. 0
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS (cont'd)
0C T
CASE
< +85C; V
CCQ
= + 1.8V 0.1V, V
CC
= +1.8V 0.1V
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Command and
Address
Address and control input setup time
t
IS
TBD
TBD
200 250
250
ps
Address and control input hold time
t
IH
TBD
TBD
275
375
475
ps
CAS# to CAS# command delay
t
CCD
TBD
TBD
2
2
2
t
CK
ACTIVE to ACTIVE (same bank) command
t
RC
TBD
TBD
55
55
55
ns
ACTIVE bank a to ACTIVE bank b command
t
RRD
TBD
TBD
7.5
7.5
7.5
ns
ACTIVE to READ or WRITE delay
t
RCD
TBD
TBD
15
15
15
ns
Four Bank Activate period
t
FAW
TBD
TBD
37.5
37.5
37.5
37.5
37.5
37.5
ACTIVE to PRECHARGE command
t
RAS
TBD
TBD
45
70,000
45
70,000
45
70,000
ns
Internal READ to precharge command delay
t
RTP
TBD
TBD
7.5
7.5
7.5
ns
Write recovery time
t
WR
TBD
TBD
15
15
15
ns
Auto precharge write recovery + precharge time
t
DAL
TBD
TBD
t
WR
+ t
RP
t
WR
+ t
RP
t
WR
+ t
RP
ns
Internal WRITE to READ command delay
t
WTR
TBD
TBD
10
7.5
10
ns
PRECHARGE command period
t
RP
TBD
TBD
15
15
15
PRECHARGE ALL command period
t
RPA
TBD
TBD
t
WR
+ t
CK
t
WR
+ t
CK
t
WR
+ t
CK
ns
LOAD MODE command cycle time
t
MRD
TBD
TBD
2
2
2
t
CK
CKE low to CK,CK# uncertainty
t
DELAY
TBD
TBD
t
IS
+ t
CK +
t
IH
t
IS
+ t
CK +
t
IH
t
IS
+ t
CK +
t
IH
ns
Refresh
REFRESH to REFRESH command interval
t
RFC
TBD
TBD
127.5
127.5
127.5
70,000
127.5
70,000
ns
Average periodic refresh interval
t
REFI
TBD
TBD
7.8
7.8
7.8
s
Self Refresh
Exit self refresh to non-READ command
t
XSNR
TBD
TBD
t
RFC
(MIN)
+ 10
t
RFC
(MIN)
+ 10
t
RFC
(MIN)
+ 10
ns
Exit self refresh to READ command
t
XSRD
TBD
TBD
200
200
200
t
CK
Exit self refresh timing reference
t
ISXR
TBD
TBD
t
IS
t
IS
t
IS
ps
ODT
ODT turn-on delay
t
AOND
TBD
TBD
2
2
2
2
2
2
t
CK
ODT turn-on
t
AON
TBD
TBD
t
AC
(MIN)
t
AC
(MAX)
+ 1000
t
AC
(MIN)
t
AC
(MAX)
+ 1000
t
AC
(MIN)
t
AC
(MAX)
+ 1000
ps
ODT turn-off delay
t
AOFD
TBD
TBD
2.5
2.5
2.5
2.5
2.5
2.5
t
CK
ODT turn-off
t
AOF
TBD
TBD
t
AC
(MIN)
t
AC
(MAX)
+ 600
t
AC
(MIN)
t
AC
(MAX)
+ 600
t
AC
(MIN)
t
AC
(MAX)
+ 600
ps
ODT turn-on (power-down mode)
t
AONPD
TBD
TBD
t
AC
(MIN) +
2000
2 x t
CK
+
t
AC
(MAX)
+ 1000
t
AC
(MIN) +
2000
2 x t
CK
+
t
AC
(MAX)
+ 1000
t
AC
(MIN) +
2000
2 x t
CK
+
t
AC
(MAX)
+ 1000
ps
ODT turn-off (power-down mode)
t
AOFPD
TBD
TBD
t
AC
(MIN) +
2000
2.5 x t
CK
+
t
AC
(MAX)
+ 1000
t
AC
(MIN) +
2000
2.5 x t
CK
+
t
AC
(MAX)
+ 1000
t
AC
(MIN) +
2000
2.5 x t
CK
+
t
AC
(MAX)
+ 1000
ps
ODT to power-down entry latency
t
ANPD
TBD
TBD
2
3
3
t
CK
ODT power-down exit latency
t
AXPD
TBD
TBD
8
8
8
t
CK
Power-Down
Exit active power-down to READ command,
MR[bit12=0]
t
XARD
TBD
TBD
2
2
2
t
CK
Exit active power-down to READ command,
MR[bit12=1]
t
XARDS
TBD
TBD
7-AL
6 - AL
6 - AL
t
CK
A Exit precharge power-down to any non-READ
command.
t
XP
TBD
TBD
2
2
2
t
CK
CKE minimum high/low time
t
CKE
TBD
TBD
3
3
3
t
CK
NOTE:
AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.
WV3HG264M64EEU-D6
December 2005
Rev. 0
ADVANCED
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
133.35 (5.25)
133.20 (5.244)
10.00 (0.394)
TYP
17.80 (0.700)
TYP
30.50 (1.201)
29.85 (1.175)
63.00 (2.48) TYP
55.00 (2.165) TYP
3.00
(0.118)
(4x)
4.00
(0.158)
(4x)
2.50 0.20
(0.098 0.007)
1.50 0.10
(0.059 0.004)
4.00 (0.158)
5.00
(0.196)
1.00 (0.039) TYP
0.80 0.05
(0.032 0.002) TYP
PIN 20
PIN 1
0.054 (1.37)
0.046 (1.17)
0.158 (4.00)
MAX
FRONT VIEW
BACK VIEW
+
+
PIN 1
PIN 121
PACKAGE DIMENSIONS FOR D6
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
ORDERING INFORMATION FOR D6
Part Number
Speed/Data Rate
CAS Latency
t
RCD
t
RP
Height*
WV3HG264M64EEU806D6xG**
400MHz/800Mb/s
6
6
6
30.00mm (1.181") TYP
WV3HG264M64EEU665D6xG**
333MHz/667Mb/s
5
5
5
30.00mm (1.181") TYP
WV3HG264M64EEU534D6xG
266MHz/533Mb/s
4
4
4
30.00mm (1.181") TYP
WV3HG264M64EEU403D6xG
200MHz/400Mb/s
3
3
3
30.00mm (1.181") TYP
** Consult factory for availability
NOTES:
RoHS compliant product. (G = RoHS Compliant)
Vendor specifi c part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualifi ed sourcing options.
(G = Infi neon, M = Micron, S = Samsung & consult factory for others)
Consult factory for availability of industrial temperature (-40C to 85C) option
WV3HG264M64EEU-D6
December 2005
Rev. 0
ADVANCED
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
PART NUMBERING GUIDE
WV 3 H G 2 64M 64 E E U xxx D6 x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DUAL RANK
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
UNBUFFERED
SPEED (Mb/s)
PACKAGE 240 PIN
COMPONENT VENDOR
NAME
(G = Infi neon)
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
WV3HG264M64EEU-D6
December 2005
Rev. 0
ADVANCED
11
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
Document Title
1GB 2x64Mx64 DDR2 SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
December 2005
Advanced
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