WV3HG264M72EER-D7

August 2006
Rev. 3

ADVANCED*

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

1GB 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM

DESCRIPTION

The WV3HG264M72EER is a 2x64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
244-pin DIMM FR4 substrate.

* This product is under development, is not qualifi ed or characterized and is subject to

change without notice.

NOTE: Consult factory for availability of:

· Vendor source control options
· Industrial temperature option

FEATURES

244-pin, dual in-line memory module (Mini-DIMM)
Fast data transfer rates: PC2-6400*, PCS-5300*,

PC2-4200 and PC2-3200

Utilizes 800, 667, 533 and 400 Mb/s DDR2 SDRAM

components

= V

CCQ

= 1.8V ±0.1V

CCSPD

= 1.7V to 3.6V

Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, 5 and 6
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
JEDEC Standard 1.8V I/O (SSTL_18 Compatible)
Gold (Au) edge contacts
Dual

Rank

RoHS

compliant

Package

option

· 244 Pin Mini-DIMM
· PCB 30.00mm (1.181") TYP

OPERATING FREQUENCIES

PC2-3200

PC2-4200

PC2-5300*

PC2-6400*

Clock Speed

200MHz

266MHz

333MHz

400MHz

CL-t

RCD

-t

3-3-3

4-4-4

5-5-5

6-6-6

*Consult factory for availability.

WV3HG264M72EER-D7

August 2006
Rev. 3

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

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PIN NAMES

Pin Name

Function

A0-A13

Address Inputs

BA0,BA1

SDRAM Bank Address

DQ0-DQ63

Data Input/Output

CB0-CB7

Check Bits

DQS0-DQS8

Data strobes

DQS0#-DQS8#

Data strobes complement

ODT0, ODT1

On-die termination control

CK0,CK0#

Clock Inputs

CKE0, CKE1

Clock Enables

CS0#, CS1#

Chip Selects

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

RESET#

DM (0-8)

Data Masks

CCSPD

SPD Power

Voltage Supply (1.8V±0.1V)

CCQ

I/O Power (1.8V)

Ground

SA0-SA2

SPD address

SDA

SPD Data Input/Output

SCL

Serial Presence Detect(SPD) Clock Input

Spare pins, No connect

REF

Input/Output Reference

PIN CONFIGURATION

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

REF

123

184

CCQ

124

DQ4

185

DQ0

125

DQ5

186

DQ1

126

187

127

DM0

188

CK0

DQS0#

128

189

CK0#

DQS0

129

190

130

DQ6

191

DQ2

A10/AP

131

DQ7

192

BA1

DQ3

BA0

132

193

133

DQ12

194

RAS#

DQ8

WE#

134

DQ13

195

CCQ

DQ9

CCQ

135

196

CS0#

CAS#

136

DM1

197

CCQ

DQS1#

CCQ

137

198

ODT0

DQS1

CS1#

138

199

A13

ODT1

139

200

RESET#

CCQ

140

201

141

202

142

DQ14

203

DQ36

DQ10

DQ32

143

DQ15

204

DQ37

DQ11

DQ33

144

205

145

DQ20

206

DM4

DQ16

DQS4#

146

DQ21

207

DQ17

DQS4

147

208

148

DM2

209

DQ38

DQS2#

DQ34

149

210

DQ39

DQS2

DQ35

150

211

151

DQ22

212

DQ44

DQ18

DQ40

152

DQ23

213

DQ45

DQ19

DQ41

153

214

154

DQ28

215

DM5

DQ24

DQS5#

155

DQ29

216

DQ25

DQS5

156

217

157

DM3

218

DQ46

DQS3#

DQ42

158

219

DQ47

DQS3

DQ43

159

220

160

DQ30

221

DQ52

DQ26

100

DQ48

161

DQ31

222

DQ53

DQ27

101

DQ49

162

223

102

163

CB4

224

CB0

103

SA2

164

CB5

225

CB1

104

165

226

105

166

DM8

227

DM6

DQS8#

106

DQS6#

167

228

DQS8

107

DQS6

168

229

108

169

CB6

230

DQ54

CB2

109

DQ50

170

CB7

231

DQ55

CB3

110

DQ51

171

232

111

172

233

DQ60

112

DQ56

173

CCQ

234

DQ61

CCQ

113

DQ57

174

CKE1

235

CKE0

114

175

236

DM7

115

DQS7#

176

237

116

DQS7

177

238

117

178

CCQ

239

DQ62

CCQ

118

DQ58

179

A12

240

DQ63

A11

119

DQ59

180

241

120

181

242

SDA

121

SA0

182

243

SCL

122

SA1

183

244

CCSPD

RESET (pin 18) is connected to both OE of the PLL and Reset# of the register .

WV3HG264M72EER-D7

August 2006
Rev. 3

ADVANCED

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FUNCTIONAL BLOCK DIAGRAM

CS#

DM/
RDQS

RCS1#
RCS0#
DQS0
DQS0#
DM0

DQS1
DQS1#
DM1

DQS2
DQS2#
DM2

DQS3
DQS3#
DM3

DQS7
DQS7#
DM7

DQS6
DQS6#
DM6

DQS5
DQS5#
DM5

DQS4
DQS4#
DM4

DQS8
DQS8#
DM8

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

CS#

DM/
RDQS

DQS

DQS#

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

1:2

CS0#
CS1#

BA0-BA1

A0-A13

RAS#

CAS#

WE#

CKE0
CKE1
ODT0
ODT1

RESET#**

CK#**

CK**

RST#

** RESET#, CK AND CK# connects to both Registers. Other signals connct to one of two Registers.

RCS0# -> CS# : DDR2 SDRAMs
RCS1 -> CS# : DDR2 SDRAMs
RBA0 - RBA1 -> BA0-BA1 : DDR2 SDRAMs
RA0-RA13 -> A0-A13 : DDR2 SDRAMs
RRAS# -> RAS# DDR2 SDRAMs
RCAS# -> CAS# DDR2 SDRAMs
RWE# -> WE# : DDR2 SDRAMs
RCKE0 -> CKE : DDR2 SDRAMs
RCKE1 -> CKE : DDR2 SDRAMs
RODT0 -> ODT : DDR2 SDRAMs
RODT1 -> ODT : DDR2 SDRAMs

CK0

CK0#

RESET#

Serial PD

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs

PCK0# -> PCK6#, PCK8#, PCK9# -> CK# : DDR2 SDRAMs

PCK7 -> CK : Register

PCK7 -> CK# : Register

SA0 SA1 SA2

SDA

SCL

CCSPD

CC/

CCQ

VREF

Serial PD

DDR2 SDRAMs

NOTE: All resistor values are 22 ohms ±5% unless otherwise specifi ed.

WV3HG264M72EER-D7

August 2006
Rev. 3

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

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DC OPERATING CONDITIONS

All voltages referenced to V

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Supply voltage

1 .7

1 .8

1 .9

I/O Supply voltage

CCQ

1 .7

1 .8

1 .9

CCL

Supply voltage

CCL

1 .7

1 .8

1 .9

I/O Reference voltage

REF

0.49 x V

CCQ

0.50 x V

CCQ

0.51 x V

CCQ

I/O Termination voltage

REF

-0.04

REF

+ 0.04

Notes:
1. V

CCQ

must track each other. V

CCQ

must be less than or equal to V

2. V

REF

is expected to equal V

CCQ

/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V

REF

may not exceed ±1 percent of the DC

value. Peak-to-peak AC noise on V

REF

may not exceed ±2 percent of V

REF

. This measurement is to be taken at the nearest V

REF

bypass capacitor.

3. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

4. V

CCQ

tracks with V

; V

CCL

track with V

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

MIN

MAX

Unit

Voltage on V

pin relative to V

-0.5

2.3

CCQ

Voltage on V

CCQ

pin relative to V

-0.5

2.3

CCL

Voltage on V

CCL

pin relative to V

-0.5

2.3

, V

OUT

Voltage on any pin relative to V

-0.5

2.3

STG

Storage temperature

-55

100

°C

CASE

Device operating temperature

°C

Input leakage current; Any input 0V<V

; V

REF

input

0V<V

<0.95V; Other pins not under test = 0V

Command/Address,
RAS#, CAS#, WE#,
CS#, CKE

-5

µA

CK, CK#

-10

µA

-10

µA

Output leakage current;
0V<V

OUT

CCQ

; DQs and ODT are disable

DQ, DQS, DQS#

-10

µA

VREF

REF

leakage current; V

REF

= Valid V

REF

level

-36

µA

INPUT/OUTPUT CAPACITANCE

TA=25 0 C, f=1 00MHz

Parameter

Symbol

Min

Max

Unit

Input capacitance (A0 - A13, BA0 - BA1 ,RAS#,CAS#,WE#)

IN1

Input capacitance ( CKE0, CKE1), (ODT0, ODT1)

IN2

Input capacitance (CS0#, CS1#)

IN3

Input capacitance (CK0, CK0#)

IN4

Input capacitance (DM0 - DM8), (DQS0 - DQS8)

IN5 (E6)

IN5 (E5)

Input capacitance (DQ0 - DQ63), (CB0 - CB7)

OUT1 (E6)

OUT1 (E5)

WV3HG264M72EER-D7

August 2006
Rev. 3

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

OPERATING TEMPERATURE CONDITION

Parameter

Symbol

Rating

Units

Notes

Operating temperature

OPER

0°C to 85°C

°C

1, 2

Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51 .2
2. At 0 - 85°C, operation temperature range, all DRAM specifi cation will be supported.

INPUT DC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Unit

Input High (Logic 1 ) Voltage

(DC)

REF

+ 0.125

CCQ

+ 0.300

Input Low (Logic 0) Voltage

(DC)

-0.300

REF

- 0.125

INPUT AC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Unit

AC Input High (Logic 1 ) Voltage DDR2-400 & DDR2-533

(AC)

REF

+ 0.250

AC Input High (Logic 1 ) Voltage DDR2-667

(AC)

REF

+ 0.200

AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533

(AC)

REF

- 0.250

AC Input Low (Logic 1 ) Voltage DDR2-667, DDR2-800(TBD)

(AC)

REF

- 0.200

WV3HG264M72EER-D7

August 2006
Rev. 3

ADVANCED

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DDR2 I

SPECIFICATIONS AND CONDITIONS

Includes DDR2 SDRAM components only; T

= 0°C, V

= 1.9V

Symbol Parameter Condition

806

665

534

403

Unit

CC0*

Operating
one bank
active-
precharge;

= t

CK(ICC)

; t

= t

RC(ICC)

; t

RAS

= t

RAS MIN(ICC)

; CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1337

1292

CC1*

Operating
one bank
active-
read-
precharge;

OUT

= 0mA; BL = 4; CL = CL(I

); t

= t

CK(ICC)

; t

= t

RC(ICC)

; t

RAS

= t

RAS MIN(ICC)

; CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING; Data pattern is same as I

CC4W

TBD

1472

1427

CC2P**

Precharge
power-
down
current;

All banks idle; t

= t

CK(ICC)

; CKE is LOW; Other control and address bus inputs are

STABLE; Data bus inputs are FLOATING

TBD

644

CC2Q**

Precharge
quite
standby
current;

All banks idle; t

= t

CK(ICC)

; CKE is HIGH; CS# is HIGH; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING

TBD

1130

1040

CC2N**

Precharge
standby
current;

All banks idle; t

= t

CK(ICC)

; CKE is HIGH; CS# is HIGH; Other control and address bus

inputs are STABLE; Data bus inputs are SWITCHING

TBD

1220

1130

CC3P**

Active
power-
down
current;

All banks open; t

= t

CK(ICC)

, CKE is LOW; Other control

and address bus inputs are STABLE; Data bus inputs are
FLOATING

Fast PDN Exit
MRS(12) = 0

TBD

1040

Slow PDN Exit
MRS(12) = 1

TBD

716

CC3N**

Active
standby
current;

All banks open; t

= t

CK(ICC)

; t

= t

RC(ICC)

; t

RAS

= t

RAS MIN(ICC)

; CKE is HIGH, CS#

is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING

TBD

1490

1400

CC4W*

Operating
burst write
current;

All banks open; Continuous burst writes; BL = 4; CL = CL(I

); AL = 0; t

= t

CK(ICC)

;

= t

RC(ICC)

; t

RAS

= t

RAS MIN(ICC)

; CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1832

1652

1562

CC4R*

Operating
burst read
current;

All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(I

); AL = 0;

= t

CK(ICC)

; t

= t

RC(ICC)

; t

RAS

= t

RAS MIN(ICC)

; CKE is HIGH, CS# is HIGH between

valid commands; Address bus inputs are SWITCHING; Data pattern is same as I

CC4W

TBD

1877

1697

1562

CC5**

Burst auto
refresh
current;

= t

CK(ICC)

; Refresh command at every t

RC(ICC)

interval; CKE is HIGH; CS# is HIGH

between valid commands; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING

TBD

3200

3020

CC6**

Self
refresh
current;

CK and CK# at 0V; CKE < 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING

Normal

TBD

144

CC7*

Operating
bank
interleave
read
current;

All bank interleaving reads; I

OUT

= 0mA; BL = 4; CL = CL(I

); AL = t

RCD(ICC)

- 1*t

CK(ICC)

;

= t

CK(ICC)

; t

= t

RC(ICC)

; t

RRD

= t

RRD MIN(ICC)

= 1*t

CK(ICC)

; CKE is HIGH; CS# is HIGH

between valid commands; Address bus inputs are STABLE during DESELECTs; Data
bus inputs are SWITCHING

TBD

2552

Notes:
I

specifi cation is based on

SAMSUNG components. Other DRAM manufacturers specifi cation may be different.

* Value calculated as one module rank in this operating condition, and all other module ranks in I

CC2P

( CKE LOW) mode.

** Value calculated refl ects all module ranks in this operating condition.

WV3HG264M72EER-D7

August 2006
Rev. 3

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

AC TIMING PARAMETERS

0°C T

CASE

< +85°C; V

CCQ

= + 1.8V ± 0.1V, V

= +1.8V ± 0.1V

Parameter

Symbol

806

665

534

403

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Clock

Clock cycle time

CL=6

(6)

TBD

CL=5

(5)

TBD

3000

8000

CL=4

(4)

TBD

3750

8000

3,750

8,000

5,000

8,000

CL=3

(3)

TBD

5000

8000

5,000

8,000

5,000

8,000

CK high-level width

TBD

0.45 0.55

0.45

0.55

0.45

0.55

CK low-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

Half clock period

TBD

MIN(t

CL)

MIN (t

)

MIN (t

)

Clock jitter

JIT

TBD

-125

125

-125

125

-125

125

Data

DQ output access time from CK/CK#

TBD

-450

+450

-500

+500

-600

+600

Data-out high impedance window from CK/CK#

TBD

AC(MAX)

Data-out low-impedance window from CK/CK#

TBD

AC(MIN)

AC(MAX)

AC(MIN)

AC(MAX)

AC(MIN)

AC(MAX)

DQ and DM input setup time relative to DQS

TBD

100

150

DQ and DM input hold time relative to DQS

TBD

175

225

275

DQ and DM input pulse width (for each input)

DIPW

TBD

0.35

Data hold skew factor

QHS

TBD

340

400

450

DQ-DQS hold, DQS to fi rst DQ to go nonvalid, per
access

TBD

- t

QHS

- t

QHS

- t

QHS

Data valid output window (DVW)

DVW

TBD

- t

DQSQ

- t

DQSQ

- t

DQSQ

Data Strobe

DQS input high pulse width

DQSH

TBD

0.35

DQS input low pulse width

DQSL

TBD

0.35

DQS output access time from CK/CK#

DQSCK

TBD

-400

+400

-450

+450

-500

+500

DQS falling edge to CK rising - setup time

DSS

TBD

0.2

DQS falling edge from CK rising - hold time

DSH

TBD

0.2

DQS-DQ skew, DOS to last DQ valid, per group, per
access

DQSQ

TBD

240

300

350

DQS read preamble

RPRE

TBD

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

DQS write preamble setup time

WPRES

TBD

DQS write preamble

WPRE

TBD

0.35

DQS write postamble

WPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

Write command to fi rst DQS latching transition

DQSS

TBD

WL-0.25 WL+0.25 WL-0.25 WL+0.25 WL-0.25 WL+0.25

AC specifi cation is based on

SAMSUNG components. Other DRAM manufacturers specifi cation may be different.

WV3HG264M72EER-D7

August 2006
Rev. 3

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

AC TIMING PARAMETERS (continued)

0°C T

CASE

< +85°C; V

CCQ

= + 1.8V ± 0.1V, V

= +1.8V ± 0.1V

Parameter

Symbol

806

665

534

403

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Command and

Address

Address and control input pulse width for each input

IPW

TBD

0.6

Address and control input setup time

TBD

200

250

350

Address and control input hold time

TBD

275

375

475

CAS# to CAS# command delay

CCD

TBD

ACTIVE to ACTIVE (same bank) command

TBD

ACTIVE bank a to ACTIVE bank b command

RRD

TBD

7.5

ACTIVE to READ or WRITE delay

RCD

TBD

Four Bank Activate period

FAW

TBD

37.5

ACTIVE to PRECHARGE command

RAS

TBD

70,000

Internal READ to precharge command delay

RTP

TBD

7.5

Write recovery time

TBD

Auto precharge write recovery + precharge time

DAL

TBD

+ t

Internal WRITE to READ command delay

WTR

TBD

7.5

PRECHARGE command period

TBD

PRECHARGE ALL command period

RPA

TBD

+ t

LOAD MODE command cycle time

MRD

TBD

CKE low to CK, CK# uncertainty

DELAY

TBD

IS+

CK+

IS+

CK+

IS+

CK+

Self Refresh

REFRESH to Active or Refresh to Refresh command interval

RFC

TBD

105

70,000

105

70,000

105

70,000

Average periodic refresh interval

REFI

TBD

7.8

Exit self refresh to non-READ command

XSNR

TBD

RFC(MIN)

+ 10

RFC(MIN)

+ 10

RFC(MIN)

+ 10

Exit self refresh to READ

XSRD

TBD

200

Exit self refresh timing reference

lSXR

TBD

ODT

ODT turn-on delay

AOND

TBD

ODT turn-on

ACN

TBD

AC(MIN)

AC(MAX)

+ 1000

AC(MIN)

AC(MAX)

+ 1000

AC(MIN)

AC(MAX)

+ 1000

ODT turn-off delay

AOFD

TBD

2.5

ODT turn-off

AOF

TBD

AC(MIN)

AC(MAX)

600

AC(MIN)

AC(MAX)

600

AC(MIN)

AC(MAX)

600

ODT turn-on (power-down mode)

AONPD

TBD

AC(MIN)

2000

2 x t

AC(MAX)

+ 1000

AC(MIN)

2000

2 x t

AC(MAX)

+ 1000

AC(MIN)

2000

2 x t

AC(MAX)

+ 1000

ODT turn-off (power-down mode)

AOFPD

TBD

AC(MIN)

2000

2.5 x

AC(MAX)

+1000

AC(MIN)

2000

2.5 x

AC(MAX)

+1000

AC(MIN)

2000

2.5 x

AC(MAX)

+ 1000

ODT to power-down entry latency

ANPD

TBD

ODT power-down exit latency

AXPD

TBD

Power-Down

Exit active power-down to READ command, MR[bit12=0]

XARD

TBD

Exit active power-down to READ command, MR[bit12=1]

XARDS

TBD

7-AL

6-AL

Exit precharge power-down to any non-READ command

TBD

CKE minimum high/low time

CKE

TBD

AC specifi cation is based on

SAMSUNG components. Other DRAM manufacturers specifi cation may be different.

WV3HG264M72EER-D7

August 2006
Rev. 3

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

82.15 (3.234)

FRONT VIEW

30.00 (1.181)

20.0 (0.787)

TYP

10.0 (0.394)

TYP

1.0 (0.039)

TYP

0.50 (0.020) R

1.80 (0.071) D

6.0 (0.236)

TYP

2.0 (0.079)

TYP

78.0 (3.071)

TYP

0.60 (0.024)

TYP

PIN 1

PIN 122

42.90 (1.689)

TYP

BACK VIEW

TYP

3.6 (0.142) TYP

3.3 (0.130)

TYP

33.6 (1.323)

TYP

38.4 (1.512)

TYP

3.2 (0.126)

Detail A

Detail B

TYP

3.80 (0.150)

MAX

1.10 (0.043)

PIN 244

PIN 123

3.6 (0.142) TYP

3.80±0.10

(0.150±0.004)

0.25 MAX

(0.010)

0.45±0.03 MAX

(0.018±0.001)

0.60 TYP

0.024 TYP

(1.30)

0.051

1.00±0.05

(0.039±0.002)

81.15 (3.222)

0.90 (0.035 )

4.10 (0.161) (2X)
3.90 (0.154)

2.10 (0.083) (2X)
1.90 (0.075)

PACKAGE DIMENSIONS FOR D7

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR D7

Part Number

Clock Speed/

Data Rate

CAS Latency

RCD

Height*

WV3HG264M72EER806D7xG** 400MHz/800Mb/s

30.00mm (1.181") TYP

WV3HG264M72EER665D7xG** 333MHz/667Mb/s

30.00mm (1.181") TYP

WV3HG264M72EER534D7xG

266MHz/533Mb/s

30.00mm (1.181") TYP

WV3HG264M72EER403D7xG

200MHz/400Mb/s

30.00mm (1.181") TYP

** Contact factory for availability.
NOTES:

· RoHS product. ("G" = RoHS Compliant)

Vendor

specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case"x" in

the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron,
S = Samsung & consult factory for others)

· Consult factory for availability of industrial temperature (-40°C to 85°C) option

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