WV3HG64M72EER-D6

August 2006
Rev. 1

ADVANCED*

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

512MB 64Mx72 DDR2 SDRAM REGISTERED DIMM, w/PLL

DESCRIPTION

The WV3HG64M72EER is a 64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of nine 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.

* This product is under development, is not qualifi ed or characterized and is subject to

change or cancellation without notice.

NOTE: Consult factory for availability of:

· Vendor source control options
· Industrial temperature option

FEATURES

Registered 240-pin, dual in-line memory module
Fast data transfer rates: PC2-6400*, PC2-5300*,

PC2-4200 and PC2-3200

Utilizes 800*, 667*, 533 and 400 MT/s DDR2

SDRAM components

= V

CCQ

= 1.8V ± 0.1V

CCSPD

= 1.7V to 3.6V

JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Multiple internal device banks for concurrent

operation

Supports duplicate output strobe (RDQS/RDQS#)
Write Latency = Read Latency 1

tck

Programmable CAS# latency (CL): 3, 4, 5* and 6*
Adjustable data-output drive strength
On-die termination (ODT)
7.8µs average periodic refresh interval
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
Auto & Self Refresh (8k/64ms refresh)
Gold edge contacts
RoHS

compliant

Package

option

· 240 Pin DIMM
· PCB 30.00mm (1.181") TYP

OPERATING FREQUENCIES

PC2-3200

PC2-4200

PC2-5300*

PC2-6400*

Clock Speed

200MHz

266MHz

333MHz

400MHz

CL-t

RCD

-t

3-3-3

4-4-4

5-5-5

6-6-6

* Consult factory for availability

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White Electronic Designs

August 2006
Rev. 1

PIN CONFIGURATION

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

REF

121

181

122

DQ4

182

DQ0

123

DQ5

183

DQ1

124

184

125

DM0/DQS9

185

CK0

DQS0#

126

NC/DQS9#

186

CK0#

DQS0

127

187

128

DQ6

188

DQ2

129

DQ7

189

DQ3

A10/AP

130

190

BA1

BA0

131

DQ12

191

DQ8

132

DQ13

192

RAS#

DQ9

WE#

133

193

CS0#

CAS#

134

DM1/DQS10

194

DQS1#

135

NC/DQS10#

195

ODT0

DQS1

136

196

A13

137

197

RESET#

138

198

139

199

DQ36

DQ32

140

DQ14

200

DQ37

DQ10

DQ33

141

DQ15

201

DQ11

142

202

DM4/DQS13

DQS4#

143

DQ20

203

NC/DQS13#

DQ16

DQS4

144

DQ21

204

DQ17

145

205

DQ38

DQ34

146

DM2/DQS11

206

DQ39

DQS2#

DQ35

147

NC/DQS11#

207

DQS2

148

208

DQ44

DQ40

149

DQ22

209

DQ45

DQ18

DQ41

150

DQ23

210

DQ19

151

211

DM5/DQS14

DQS5#

152

DQ28

212

NC/DQS14#

DQ24

DQS5

153

DQ29

213

DQ25

154

214

DQ46

DQ42

155

DM3/DQS12

215

DQ47

DQS3#

DQ43

156

NC/DQS12#

216

DQS3

157

217

DQ52

DQ48

158

DQ30

218

DQ53

DQ26

DQ49

159

DQ31

219

DQ27

100

160

220

101

SA2

161

CB4

221

CB0

102

162

CB5

222

CB1

103

163

223

DM6/DQS15

104

DQS6#

164

DM8/DQS17

224

NC/DQS15#

DQS8#

105

DQS6

165

NC/DQS17#

225

DQS8

106

166

226

DQ54

107

DQ50

167

CB6

227

DQ55

CB2

108

DQ51

168

CB7

228

CB3

109

169

229

DQ60

110

DQ56

170

230

DQ61

111

DQ57

171

231

CKE0

112

172

232

DM7/DQS16

113

DQS7#

173

233

NC/DQS16#

114

DQS7

174

234

115

175

235

DQ62

116

DQ58

176

A12

236

DQ63

A11

117

DQ59

177

237

118

178

238

SPD

119

SDA

179

239

SA0

120

SCL

180

240

SA1

PIN NAMES

Pin Name

Function

A0-A13

Address Inputs

BA0,BA1

SDRAM Bank Addresses

DQ0-DQ63

Data Input/Output

CB0-CB7

Check Bits

DQS0-DQS17

Data strobes

DQS0#-DQS17#

Data strobes complement

DM0 - DM8

Data Masks

ODT0

On-die termination control

CK0,CK0#

Clock Inputs

CKE0

Clock Enable

CS0#

Chip Select

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

RESET#

Core and I/O Power (1.8V)

Ground

SA0-SA2

SPD address

SDA

SPD Data Input/Output

SCL

Serial Presence Detect(SPD) Clock Input

REF

Input/Output Reference Voltage

SPD

SPD Power

Spare pins, No connect

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Rev. 1

FUNCTIONAL BLOCK DIAGRAM

Serial PD

A1 A2

SA0 SA1 SA2

SCL

SDA

CCSPD

CCQ

REF

Serial PD

DDR2 SDRAMs

1:2

RST#

CS0#

BA0 - BA1

A0 - A13

RAS#
CAS#

WE#

CKE0
ODT0

RESET#**

PCK7**

PCK7#**

CK0

CK0#

RESET#

PCK0-PCK6, PCK8, PCK9 CK : DDR2 SDRAMs

PCK0#-PCK6#, PCK8#, PCK9# CK# : DDR2 SDRAMs
PCK7 CK : Register
PCK7# CK# : Register

RCS0# : DDR2 SDRAMs
RBA0 - RBA1 : DDR2 SDRAMs
RA0 - RA13 : DDR2 SDRAMs
RRAS# : DDR2 SDRAMs
RCAS# : DDR2 SDRAMs
RWE# : DDR2 SDRAMs
RCKE0 : DDR2 SDRAMs
RODT0 : DDR2 SDRAMs

RCS0#

DQS0

DQS0#

DM0/DQS9

NC/DQS9#

DM/

RDQS

NU/

RDQS#

CS# DQS DQS#

DQ1

DQ0

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS1

DQS1#

NC/DQS10#

DM1/DQS10

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DQS2#

DM2/DQS11

NC/DSS11#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DQS3#

DM3/DQS12

NC/DSS12#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS8

DQS8#

DM8/DQS17

NC/DSS17#

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DQS4

DQS4#

DM4/DQS13

NC/DQS13#

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DQS5#

DM5/DQS14

NC/DQS14#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DQS6#

DM6/DQS15

NC/DQS15#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DQS7#

DM7/DQS16

NC/DQS16#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM/

RDQS

NU/

RDQS#

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

NU/

RDQS#

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

NU/

RDQS#

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

NU/

RDQS#

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

NU/

RDQS#

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

NU/

RDQS#

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

NU/

RDQS#

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

NU/

RDQS#

CS# DQS DQS#

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

NOTE: All resistor values are 22 ohms unless otherwise specifi ed.
**RESET#, PCK7 and RCK7# connects both registers. Other signals connect to one of two registers.

WV3HG64M72EER-D6

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White Electronic Designs

August 2006
Rev. 1

DC OPERATING CONDITIONS

All voltages referenced to V

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Supply Voltage

1.7

1.8

1.9

I/O Reference Voltage

REF

0.49 x V

0.50 x V

0.51 x V

I/O Termination Voltage

REF

-0.04

REF

+0.04

SPD Supply Voltage

CCSPD

1.7

3.6

Notes:
1

REF

is expected to equal V

CC/2

of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on

REF

may not exceed +/-1 percent of the

DC value. Peak-to-peak AC noise on V

REF

may not exceed +/-2 percent of V

REF

. This measurement is to be taken at the nearest V

REF

bypass capacitor.

2. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

3. V

CCQ

of all IC's are tied to V

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

Max

Units

Voltage on V

pin relative to V

-0.5

2.3

, V

OUT

Voltage on any pin relative to V

- 0.5

2.3

STG

Storage Temperature

-55

100

°C

Input leakage current: Any input
0V<VIN<V

; V

REF

input

0V<VIN<0.95V; Other pins not under test = 0V

Command/Address,
RAS#, CAS#, WE#,
CS#, CKE

-5

µA

CK, CK#

-10

-5

Output leakage current;
0V<VOUT<V

; DQs and ODT are disable

DQ, DQS, DQS#

-5

µA

VREF

REF

leakage current; V

REF

= Valid V

REF

level

-18

µA

CAPACITANCE

= 25°C, f = 100MHz

Parameter

Symbol

Min

Max

Units

Input Capacitance: (A0~A13, BA0~BA1, RAS#, CAS#, WE#)

CIN

Input Capacitance: (CKE0), (ODT0)

CIN

Input Capacitance: (CS0#)

CIN

Input Capacitance: (CK0, CK0#)

CIN

Input Capacitance: (DM0~DM8), DQS0~DQS17)

CIN

6.5

Input/Output Capacitance: (DQ0 ~ DQ63), (CB0 ~CB7)

COUT

6.5

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White Electronic Designs

August 2006
Rev. 1

OPERATING TEMPERATURE CONDITION

Parameter

Symbol

Rating

Units

Notes

Operating Case Temperature (Commercial)

TOPER

0 to +85°C

°C

1, 2

NOTE:
1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2
2. At 0 to +85

°C, operation temperature range, all DRAM specifi cation will be supported.

INPUT DC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Unit

Input High (Logic 1) Voltage

(DC)

REF

+ 0.125

+ 0.300

Input Low (Logic 0) Voltage

(DC)

- 0.300

VREF - 0.125

INPUT AC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Unit

AC Input High (Logic 1) Voltage
DDR2-400 & DDR2-533

(AC)

REF

+ 0.250

AC Input High (Logic 1) Voltage
DDR2-667

(AC)

REF

+ 0.200

AC Input High (Logic 0) Voltage
DDR2-400 & DDR2-533

(AC)

REF

- 0.250

AC Input High (Logic 0) Voltage
DDR2-667

(AC)

REF

- 0.200

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Rev. 1

DDR2 I

SPECIFICATIONS AND CONDITIONS

Includes DDR2 SDRAM components only

Symbol Proposed Conditions

806

665

534

403

Units

CC0*

Operating one bank active-precharge current;
t

= t

), t

= t

), t

RAS

= t

RAS

min(I

); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1,120

CC1*

Operating one bank active-read-precharge current;
I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

= t

), t

RAS

= t

RAS

min(I

), t

RCD

= t

RCD

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as I

TBD

1,255

CC2P*

Precharge power-down current;
All banks idle; t

= t

); CKE is LOW; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

TBD

472

CC2Q**

Precharge quiet standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

STABLE; Data bus inputs are FLOATING

TBD

670

CC2N**

Precharge standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

TBD

715

CC3P**

Active power-down current;
All banks open; t

= t

); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

TBD

670

Slow PDN Exit MRS(12) = 1

TBD

508

CC3N**

Active standby current;
All banks open; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between

valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING

TBD

850

CC4W*

Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus

inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1,480

1,390

CC4R*

Operating burst read current;
All banks open, Continuous burst reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus

inputs are SWITCHING; Data pattern is same as I

TBD

1,525

1,390

CC5B**

Burst auto refresh current;
t

= t

); Refresh command at every t

RFC

) interval; CKE is HIGH, CS# is HIGH between

valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING

TBD

1,160

1,660

CC6**

Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs
are FLOATING; Data bus inputs are FLOATING

Normal

TBD

CC7*

Operating bank interleave read current;
All bank interleaving reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = t

D(I

)-1*t

); t

), t

= t

), t

RRD

= t

RRD

), t

RCD

= 1*t

); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.

TBD

2,380

Note: I

specifi cation is based on

SAMSUNG components. Other DRAM Manufacturers specifi cation may be different.

*: Value calculated as one module rank in this operating condition, and all other module ranks in I

CC2P

(CKE LOW) mode.

**: Value calculated refl ects all module ranks in this operating condition.

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AC TIMING PARAMETERS & SPECIFICATIONS

AC CHARACTERISTICS

806

665

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Clock

Clock cycle time

CL = 6

CK (6)

TBD

CL = 5

CK (5)

TBD

3,000

8,000

CL = 4

CK (4)

TBD

3,750

8,000

3,750

8,000

5,000

8,000

CL = 3

CK (3)

TBD

5,000

8,000

5,000

8,000

5,000

8,000

CK high-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

Half clock period

TBD

MIN

CH,

)

MIN

CH,

)

MIN

CH,

)

Clock jitter

TBD

-125

125

-125

125

-125

125

Data

DQ output access time from CK/CK#

TBD

-450

+450

-500

+500

-600

+600

Data-out high-impedance window from
CK/CK#

TBD

AC(MAX)

Data-out low-impedance window from
CK/CK#

TBD

AC(MIN)

AC(MAX)

AC(MIN)

AC(MAX)

AC(MIN)

AC(MAX)

DQ and DM input setup time relative to
DQS

TBD

100

150

DQ and DM input hold time relative to DQS

TBD

225

275

DQ and DM input pulse width (for each
input)

TBD

0.35

Data hold skew factor

QHS

TBD

340

400

450

DQ...DQS hold, DQS to fi rst DQ to go
nonvalid, per access

TBD

HP -

QHS

HP -

QHS

HP -

QHS

Data valid output window (DVW)

DVW

TBD

QH -

DQSQ

QH -

DQSQ

QH -

DQSQ

Data Strobe

DQS input high pulse width

DQSH

TBD

0.35

DQS input low pulse width

DQSL

TBD

0.35

DQS output access time from CK/CK#

DQSCK

TBD

-400

+400

-450

+450

-500

+500

DQS falling edge to CK rising ... setup time

DSS

TBD

0.2

DQS falling edge from CK rising ... hold
time

DSH

TBD

0.2

DQS...DQ skew, DQS to last DQ valid, per

group,

per access

DQSQ

TBD

240

300

350

DQS read preamble

RPRE

TBD

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

DQS write preamble setup time

WPRES

TBD

DQS write preamble

WPRE

TBD

0.35

DQS write postamble

WPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

Write command to fi rst DQS latching
transition

DQSS

TBD

WL-

0.25

WL+

0.25

WL-

0.25

WL+

0.25

WL-

0.25

WL+

0.25

Address and control input pulse width for

each input

IPW

TBD

0.6

Address and control input setup time

TBD

200

250

Address and control input hold time

TBD

275

375

475

Address and control input hold time

CCD

TBD

* AC specifi cation is based on

SAMSUNG components. Other DRAM manufactures specifi cation may be different.

Continued on next page

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Rev. 1

AC TIMING PARAMETERS (cont'd)

AC CHARACTERISTICS

806

665

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Command and

Address

ACTIVE to ACTIVE (same bank) command

TBD

ACTIVE bank a to ACTIVE bank b command

RRD

TBD

7.5

ACTIVE to READ or WRITE delay

RCD

TBD

Four Bank Activate period

FAW

TBD

37.5

ACTIVE to PRECHARGE command

RAS

TBD

70,000

Internal READ to precharge command delay

RTP

TBD

7.5

Write recovery time

TBD

Auto precharge write recovery + precharge

time

DAL

TBD

Internal WRITE to READ command delay

WTR

TBD

7.5

PRECHARGE command period

TBD

PRECHARGE ALL command period

RPA

TBD

LOAD MODE command cycle time

MRD

TBD

CKE low to CK,CK# uncertainty

DELAY

TBD

Self Refresh

REFRESH to Active of Refresh to Refresh

command interfal

RFC

TBD

127.5

70,000

127.5

70,000

127.5

70,000

Average periodic refresh interval

REF

TBD

7.8

µs

Exit self refresh to non-READ command

XSNR

TBD

RFC(MIN)

+10

RFC(MIN)

+10

RFC(MIN)

+10

Exit self refresh to READ command

XSRD

TBD

200

Exit self refresh timing reference

SXR

TBD

ODT

ODT turn-on delay

AOND

TBD

ODT turn-on

AON

TBD

AC(MIN)

AC(MAX)

+1000

AC(MIN)

AC(MAX)

+1000

AC(MIN)

AC(MAX)

+1000

ODT turn-off delay

AOFD

TBD

2.5

ODT turn-off

AOF

TBD

AC(MIN)

AC(MAX)

+600

AC(MIN)

AC(MAX)

+600

AC(MIN)

AC(MAX)

+600

ODT turn-on (power-down mode)

AONPD

TBD

AC(MIN)

+2000

2 x t

AC(MAX)

+1000

AC(MIN)

+2000

2 x t

AC(MAX)

+1000

AC(MIN)

+2000

2 x t

AC(MAX)

+1000

ODT turn-off (power-down mode)

AOFPD

TBD

AC(MIN)

+2000

2.5 x

AC(MAX)

+1000

AC(MIN)

+2000

2.5 x

AC(MAX)

+1000

AC(MIN)

+2000

2.5 x

AC(MAX)

+1000

ODT to power-down entry latency

ANPD

TBD

ODT power-down exit latency

AXPD

TBD

Power-Down

Exit active power-down to READ command,

MR[bit12=0]

XARD

TBD

Exit active power-down to READ command,

MR[bit12=1]

XARDS

TBD

7-AL

6-AL

A Exit precharge power-down to any non-

READ command.

TBD

CKE minimum high/low time

CKE

TBD

* AC specifi cation is based on

SAMSUNG components. Other DRAM manufactures specifi cation may be different.

WV3HG64M72EER-D6

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

August 2006
Rev. 1

30.50 (1.201)
29.85 (1.175)

PIN 1

17.80 (0.700)

TYP.

5.0 (0.197) TYP.

123.0 (4.843)

TYP.

1.0 (0.039)

TYP.

0.80 (0.032)

TYP.

4.00 (0.158)

(4X)

PIN 120

FRONT VIEW

133.50 (5.256)
133.20 (5.244)

63.0 (2.480)

TYP.

55.0 (2.165)

TYP.

10.00(0.394 )

TYP.

BACK VIEW

PIN 240

PIN 121

1.37 (0.054)
1.17 (0.046)

4.0 (0.158)

MAX

1.50 (0.059)

3.00 (0.118)

(4X)

5.175 (0.204)

(2X)

PACKAGE DIMENSIONS FOR D6

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

ORDERING INFORMATION FOR D6

Part Number

Speed

CAS Latency

RCD

Height*

WV3HG64M72EER806D6

400MHz/800Mb/s

30.00mm (1.181") TYP

WV3HG64M72EER665D6

333MHz/667Mb/s

30.00mm (1.181") TYP

WV3HG64M72EER534D6

266MHz/533Mb/s

30.00mm (1.181") TYP

WV3HG64M72EER403D6

200MHz/400Mb/s

30.00mm (1.181") TYP

NOTES:

· RoHS products. ("G" = RoHS Compliant)

Vendor

specifi c part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"

in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualifi ed sourcing options.
(M = Micron, S = Samsung & consult factory for others)

· Consult factory for availability of industrial temperature (-40°C to 85°C) option

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