WV3HG64M72EEU-PD4

May 2006
Rev. 2

ADVANCED*

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

512MB 64Mx72 DDR2 SDRAM, UNBUFFERED SO-DIMM, w/

PLL

DESCRIPTION

The WV3HG64M72EEU is a 64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of nine 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.

* This product is under development, is not qualifi ed or characterized and is subject to

change or cancellation without notice.

NOTE: Consult factory for availability of:

· Vendor source control options
· Industrial temperature option

FEATURES

Unbuffered 200-pin (SO-DIMM), Small-Outline dual

in-line memory module

Fast data transfer rates: PC2-6400*, PC2-5300*,

PC2-4200 and PC2-3200

= V

CCQ

1.8V ±0.1V

CCSPD

1.7V to 3.6V

JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Multiple internal device banks for concurrent

operation

Differential clock inputs (CK, CK#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Posted CAS# additive latency: 0, 1, 2, 3 and 4
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms: 8,192 cycle refresh)
Gold edge contacts
Single

Rank

RoHS

compliant

JEDEC proposed pin-out
Package

· 200 Pin SO-DIMM: 30.00mm (1.181") TYP.

OPERATING FREQUENCIES

PC2-3200

PC2-4200

PC2-5300*

PC2-6400*

Clock Speed

200MHz

266MHz

333MHz

400MHz

CL-t

RCD

-t

3-3-3

4-4-4

5-5-5

6-6-6

* Consult factory for availability

WV3HG64M72EEU-PD4

May 2006
Rev. 2

ADVANCED

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PIN NAMES

Pin Name

Function

A0-A13

Address Inputs

BA0, BA1

SDRAM Bank Address

DQ0-DQ63

Data Input/Output

CB0-CB7

Check Bits

DM0-DM8

Data-in mask

DQS0-DQS8

Data strobes

DQS0#-DQS8#

Data strobes negative

ODT0

On-die termination control

CK, CK#

Clock Input

CKE0

Clock enable input

CS0#

Chip select input

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

Core Power

RESET#

PLL Output enable

Ground

SA0-SA1

SPD address

SDA

Serial Data Input/Output

REF

Input/Output Reference

CCSPD

Serial EEPROM power supply

SCL

SPD Clock Input

Spare pins, No connect

PIN CONFIGURATION

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

Pin No.

Symbol

REF

DQ18

101

151

102

152

DQ0

DQ19

103

153

DQS5#

DQ4

DQ28

104

154

DM5

105

155

DQS5

DQ5

DQ29

106

156

DQ1

DQ24

107

157

108

158

DQ46

DQS0#

DQ25

109

159

DQ42

DM0

DM3

110

160

DQ47

DQS0

111

A10/AP

161

DQ43

112

BA1

162

DQS3#

113

BA0

163

DQ6

DQ30

114

164

DQ52

DQ2

DQS3

115

RAS#

165

DQ48

DQ7

DQ31

116

WE#

166

DQ53

DQ3

117

167

DQ49

118

CS0#

168

DQ26

119

CAS#

169

DQ12

CB4

120

ODT0

170

DM6

DQ8

DQ27

121

171

DQS6#

DQ13

CB5

122

A13

172

DQ9

123

173

DQS6

124

174

DQ54

CB0

125

175

DM1

DM8

126

176

DQ55

DQS1#

CB1

127

177

DQ50

128

CK#

178

DQS1

129

DQ32

179

DQ51

DQ14

CB6

130

180

DQ60

DQS8#

131

181

DQ15

CB7

132

DQ36

182

DQ61

DQ10

DQS8

133

DQ33

183

DQ56

134

DQ37

184

DQ11

135

DQS4#

185

DQ57

DQ20

CB2

136

186

DM7

CKE0

137

DQS4

187

DQ21

CB3

138

DM4

188

DQ62

DQ16

139

189

DQS7#

140

190

DQ17

141

DQ34

191

DQS7

RESET#

142

DQ38

192

DQ63

143

DQ35

193

DQ58

DM2

144

DQ39

194

SDA

DQS2#

A12

145

195

A11

146

196

SCL

DQS2

147

DQ40

197

DQ59

DQ22

148

DQ44

198

SA1

149

DQ41

199

SPD

DQ23

100

150

DQ45

200

SA0

WV3HG64M72EEU-PD4

May 2006
Rev. 2

ADVANCED

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FUNCTIONAL BLOCK DIAGRAM

Serial PD

A1 A2

SA0 SA1

SA2

SCL

SDA

CCSPD

REF

Serial PD

DDR2 SDRAMs

BA0 - BA1

A0 - A13

RAS#
CAS#

WE#

CKE0
ODT0

BA0 - BA1 : DDR2 SDRAMs
A0 - A13 : DDR2 SDRAMs
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE : DDR2 SDRAMs
ODT : DDR2 SDRAMs

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/RDQS CS# DQS DQS#

CS0#

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DQS4

DQS4#

DM4

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DQS1

DQS1#

DM1

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DQS5

DQS5#

DM5

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DQS2

DQS2#

DM2

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DQS6

DQS6#

DM6

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DQS3

DQS3#

DM3

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DQS7

DQS7#

DM7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS# DQS DQS#

DQS8

DQS8#

DM8

CK0

CK0#

RESET#

CK: SDRAMs

CK#: SDRAMs

DM/RDQS

120

DQS0

DQS0#

DM0

NOTE: All resistor values are 22 ohms ±5% unless otherwise specifi ed.

WV3HG64M72EEU-PD4

May 2006
Rev. 2

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

Max

Units

Voltage on V

pin relative to V

-1.0

2.3

, V

OUT

Voltage on any pin relative to V

-0.5

2.3

STG

Storage Temperature

-55

100

°C

Input leakage current; Any input 0V<V

; V

REF

input

0V,V

,0.95V; Other pins not under test = 0V

Command/Address,
RAS#, CAS#, WE#,

-45

µA

CS#, CKE

-45

µA

CK, CK#

-10

µA

-5

µA

Output leakage current; 0V<V

; DQs and ODT are disable

DQ, DQS, DQS#

-5

µA

VREF

REF

leakage current; V

REF

= Valid V

REF

level

-18

µA

DC OPERATING CONDITIONS

All voltages referenced to V

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Supply Voltage

1.7

1.8

1.9

I/O Reference Voltage

REF

0.49 x V

0.50 x V

0.51 x V

I/O Termination Voltage

REF

-0.04

REF

+0.04

SPD Supply Voltage

CCSPD

1.7

3.6

Notes:
1

REF

is expected to equal V

CC/2

of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on

REF

may not exceed +/-1 percent of the

DC value. Peak-to-peak AC noise on V

REF

may not exceed +/-2 percent of V

REF

. This measurement is to be taken at the nearest V

REF

bypass capacitor.

2. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

3. V

CCQ

of all IC's are tied to V

OPERATING TEMPERATURE CONDITION

Parameter

Symbol

Rating

Units

Notes

Operating Case Temperature (Commercial)

TOPER

0 to +85°C

°C

1, 2

NOTE:
1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2
2. At 0 - 85

°C, operation temperature range, all DRAM specifi cation will be supported.

WV3HG64M72EEU-PD4

May 2006
Rev. 2

ADVANCED

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INPUT DC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Unit

Input High (Logic 1) Voltage

(DC)

REF

+ 0.125

+ 0.300

Input High (Logic 0) Voltage

(DC)

-0.300

REF

- 0.125

INPUT AC LOGIC LEVEL

All voltages referenced to V

Parameter

Symbol

Min

Max

Unit

AC Input High (Logic 1) Voltage
DDR2-400 & DDR2-533

(AC)

REF

+ 0.250

AC Input High (Logic 1) Voltage
DDR2-667

(AC)

REF

+ 0.200

AC Input High (Logic 0) Voltage
DDR2-400 & DDR2-533

(AC)

REF

- 0.250

AC Input High (Logic 0) Voltage
DDR2-667

(AC)

REF

- 0.200

INPUT/OUTPUT CAPACITANCE

TA=25°C, f=100MHz

Parameter

Symbol

Min

Max

Unit

Input capacitance (A0~A13, BA0~BA1,
RAS#, CAS#, WE#)

Input capacitance (CKE0), (ODT0)

Input capacitance (CS0#)

Input capacitance (CK, CK#)

Input capacitance (DM0~DM8),
(DQS0~DQS8)

5 (665)

6.5

7.5

5 (534, 403)

6.5

Input capacitance (DQ0~DQ63),
(CB0~CB7)

OUT

1 (665)

6.5

7.5

OUT

1 (534, 403)

6.5

WV3HG64M72EEU-PD4

May 2006
Rev. 2

ADVANCED

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DDR2 I

SPECIFICATIONS AND CONDITIONS

Includes DDR2 SDRAM components only

= +1.8V ± 0.1V

Symbol Proposed Conditions

806

665

534

403

Units

CC0*

Operating one bank active-precharge current;
t

= t

), t

= t

), t

RAS

= t

RAS

min(I

); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1,065

1, 020

1,020

CC1*

Operating one bank active-read-precharge current;
I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

= t

), t

RAS

= t

RAS

min(I

), t

RCD

= t

RCD

); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as I

TBD

1,200

1,115

1,155

CC2P*

Precharge power-down current;
All banks idle; t

= t

); CKE is LOW; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

TBD

372

CC2Q**

Precharge quiet standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

STABLE; Data bus inputs are FLOATING

TBD

615

570

CC2N**

Precharge standby current;
All banks idle; t

= t

); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

TBD

660

615

CC3P**

Active power-down current;
All banks open; t

= t

); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

TBD

570

Slow PDN Exit MRS(12) = 1

TBD

408

CC3N**

Active standby current;
All banks open; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between

valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING

TBD

795

750

CC4W*

Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus

inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1,560

1,380

1,290

CC4R*

Operating burst read current;
All banks open, Continuous burst reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = 0; t

= t

), t

RAS

= t

RAS

max(I

), t

= t

); CKE is HIGH, CS# is HIGH between valid commands; Address bus

inputs are SWITCHING; Data pattern is same as I

TBD

1,605

1,425

1,290

CC5B**

Burst auto refresh current;
t

= t

); Refresh command at every t

RFC

) interval; CKE is HIGH, CS# is HIGH between

valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING

TBD

1,650

1,560

CC6**

Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING

Normal

TBD

CC7*

Operating bank interleave read current;
All bank interleaving reads, I

OUT

= 0mA; BL = 4, CL = CL(I

), AL = t

D(I

)-1*t

); t

), t

= t

), t

RRD

= t

RRD

), t

RCD

= 1*t

); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.

TBD

2,280

Note: I

specifi cation is based on

SAMSUNG components. Other DRAM Manufacturers specifi cation may be different.

*: Value calculated as one module rank in this operating condition, and all other module ranks in I

CC2P

(CKE LOW) mode.

**: Value calculated refl ects all module ranks in this operating condition.

WV3HG64M72EEU-PD4

May 2006
Rev. 2

ADVANCED

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AC TIMING PARAMETERS & SPECIFICATIONS

AC CHARACTERISTICS

806

665

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Clock

Clock cycle time

CL = 6

CK (6)

TBD

CL = 5

CK (5)

TBD

3,000

8,000

CL = 4

CK (4)

TBD

3,750

8,000

3,750

8,000

5,000

8,000

CL = 3

CK (3)

TBD

5,000

8,000

5,000

8,000

5,000

8,000

CK high-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

TBD

0.45

0.55

0.45

0.55

0.45

0.55

Half clock period

TBD

MIN

CH,

CL)

MIN

CH,

CL)

MIN

CH,

CL)

Clock jitter

JIT

TBD

-125

125

-125

125

-125

125

Data

DQ output access time from CK/CK#

TBD

-450

+450

-500

+500

-600

+600

Data-out high-impedance window from
CK/CK#

TBD

AC(MAX)

Data-out low-impedance window from
CK/CK#

TBD

AC(MIN)

AC(MAX)

AC(MIN)

AC(MAX)

AC(MIN)

AC(MAX)

DQ and DM input setup time relative to
DQS

TBD

100

150

DQ and DM input hold time relative to DQS

TBD

225

275

DQ and DM input pulse width (for each
input)

TBD

0.35

Data hold skew factor

QHS

TBD

340

400

450

DQ...DQS hold, DQS to fi rst DQ to go
nonvalid, per access

TBD

HP -

QHS

HP -

QHS

HP -

QHS

Data valid output window (DVW)

DVW

TBD

QH -

DQSQ

QH -

DQSQ

QH -

DQSQ

Data Strobe

DQS input high pulse width

DQSH

TBD

0.35

DQS input low pulse width

DQSL

TBD

0.35

DQS output access time from CK/CK#

DQSCK

TBD

-400

+400

-450

+450

-500

+500

DQS falling edge to CK rising ... setup time

DSS

TBD

0.2

DQS falling edge from CK rising ... hold
time

DSH

TBD

0.2

DQS...DQ skew, DQS to last DQ valid, per

group,

per access

DQSQ

TBD

240

300

350

DQS read preamble

RPRE

TBD

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

DQS write preamble setup time

WPRES

TBD

p s

DQS write preamble

WPRE

TBD

0.35

DQS write postamble

WPST

TBD

0.4

0.6

0.4

0.6

0.4

0.6

Write command to fi rst DQS latching
transition

DQSS

TBD

WL-

0.25

WL+

0.25

WL-

0.25

WL+

0.25

WL-

0.25

WL+

0.25

Address and control input pulse width for

each input

IPW

TBD

0.6

Address and control input setup time

TBD

200

250

Address and control input hold time

TBD

275

375

475

Address and control input hold time

CCD

TBD

* AC specifi cation is based on

SAMSUNG components. Other DRAM manufactures specifi cation may be different.

Continued on next page

WV3HG64M72EEU-PD4

May 2006
Rev. 2

ADVANCED

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AC TIMING PARAMETERS (cont'd)

AC CHARACTERISTICS

806

665

534

403

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Command and

Address

ACTIVE to ACTIVE (same bank) command

TBD

ACTIVE bank a to ACTIVE bank b command

RRD

TBD

7.5

ACTIVE to READ or WRITE delay

RCD

TBD

Four Bank Activate period

FAW

TBD

37.5

ACTIVE to PRECHARGE command

RAS

TBD

70,000

Internal READ to precharge command delay

RTP

TBD

7.5

Write recovery time

TBD

Auto precharge write recovery + precharge

time

DAL

TBD

Internal WRITE to READ command delay

WTR

TBD

7.5

PRECHARGE command period

TBD

PRECHARGE ALL command period

RPA

TBD

LOAD MODE command cycle time

MRD

TBD

CKE low to CK,CK# uncertainty

DELAY

TBD

4.375

Self Refresh

REFRESH to Active of Refresh to Refresh

command interfal

RFC

TBD

105

70,000

105

70,000

105

70,000

Average periodic refresh interval

REF

TBD

7.8

µs

Exit self refresh to non-READ command

XSNR

TBD

RFC(MIN)

+10

RFC(MIN)

+10

RFC(MIN)

+10

Exit self refresh to READ command

XSRD

TBD

200

Exit self refresh timing reference

SXR

TBD

ODT

ODT turn-on delay

AOND

TBD

ODT turn-on

AON

TBD

AC(MIN)

AC(MAX)

+1000

AC(MIN)

AC(MAX)

+1000

AC(MIN)

AC(MAX)

+1000

ODT turn-off delay

AOFD

TBD

2.5

ODT turn-off

AOF

TBD

AC(MIN)

AC(MAX)

+600

AC(MIN)

AC(MAX)

+600

AC(MIN)

AC(MAX)

+600

ODT turn-on (power-down mode)

AONPD

TBD

AC(MIN)

+2000

2 x t

AC(MIN)

+1000

AC(MIN)

+2000

2 x t

AC(MIN)

+1000

AC(MIN)

+2000

2 x t

AC(MIN)

+1000

ODT turn-off (power-down mode)

AOFPD

TBD

AC(MIN)

+2000

2.5 x

AC(MIN)

+1000

AC(MIN)

+2000

2.5 x

AC(MIN)

+1000

AC(MIN)

+2000

2.5 x

AC(MIN)

+1000

ODT to power-down entry latency

ANPD

TBD

ODT power-down exit latency

AXPD

TBD

Power-Down

Exit active power-down to READ command,

MR[bit12=0]

XARD

TBD

Exit active power-down to READ command,

MR[bit12=1]

XARDS

TBD

7-AL

6-AL

A Exit precharge power-down to any non-

READ command.

TBD

CKE minimum high/low time

CKE

TBD

* AC specifi cation is based on

SAMSUNG components. Other DRAM manufactures specifi cation may be different.

WV3HG64M72EEU-PD4

May 2006
Rev. 2

ADVANCED

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

3.302 (0.130)

MAX

1.10 (0.043)

0.90 (0.035)

PIN 1

67.75 (2.667)

67.45 (2.656)

20.00 (0.787)

TYP

1.80 (0.071)

(2X)

0.60 (0.024)

TYP

0.45 (0.018)

TYP

PIN 199

PIN 200

PIN 2

FRONT VIEW

2.15 (0.085)

6.00 (0.236)

63.60 (2.504)

2.55 (0.100)

1.00 (0.039)

TYP

BACK VIEW

30.15 (1.187)

29.85 (1.175)

47.40 (1.866)

TYP

11.40 (0.449)

TYP

4.2 (0.165)

TYP

4.10(0.161) (2X)

3.90(0.154)

PACKAGE DIMENSIONS FOR PD4

* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)

Tolerances: ±0.13 (0.005) unless otherwise specifi ed

ORDERING INFORMATION FOR PD4

Part Number

Speed/Data Rate

Frequency

CAS

Latency

RCD

Height*

WV3HG64M72EEU806PD4xxG**

400MHz/800Mb/s

30.00mm (1.181") TYP

WV3HG64M72EEU665PD4xxG**

333MHz/667Mb/s

30.00mm (1.181") TYP

WV3HG64M72EEU534PD4xxG

266MHz/533Mb/s

30.00mm (1.181") TYP

WV3HG64M72EEU403PD4xxG

200MHz/400Mb/s

30.00mm (1.181") TYP

** Consult factory for availability
NOTES:

· RoHS compliant product (G = RoHS Compliant)

Vendor

specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be

replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)

· Consult factory for availability of industrial temperature (-40°C to 85°C) option

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