128K x 8 Static RAM
WCFS1008C3E
WCFS1008C9E
Revised April 12, 2002
S1008C3E
1008C9E
Features
High speed
-- t
AA
= 15 ns
2.0V Data Retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE options
Functional Description
The WCF1008C3E and WCFS1008C9E are high-perfor-
mance CMOS static RAM organized as 131,072 words by 8
bits. Easy memory expansion is provided by an active LOW
Chip Enable (CE
1
), an active HIGH Chip Enable (CE
2
), an
active LOW Output Enable (OE), and three-state drivers. Writ-
ing to the device is accomplished by taking Chip Enable One
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable
Two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The WCFS1008C3E is available in standard 300-mil-wide
SOJ. The WCFS1008C9E is available in standard 400-mil-
wide SOJ. The WCFS1008C3E and WCFS1008C9E are func-
tionally equivalent in all other respects.
.
14
15
Logic Block Diagram
Pin
Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
S
E
NS
E AM
PS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
A
10
CE
1
A
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15
17
18
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
WE
V
CC
A
15
A
13
A
8
A
9
I/O
7
I/O
6
I/O
5
I/O
4
A
2
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
I/O
3
A
1
A
0
A
11
CE
2
Selection Guide
WCFS1008C3E WCFS1008C9E 15ns
Maximum Access Time (ns)
15
Maximum Operating Current (mA)
80
Maximum CMOS Standby Current (mA)
10
WCFS1008C3E
WCFS1008C9E
Page 2 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage on V
CC
to Relative GND
[1]
.... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial
0
C to +70
C
5V
10%
Electrical Characteristics
Over the Operating Range
Test Conditions
WCFS1008C3E
WCFS1008C9E 15ns
Parameter
Description
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.,
I
OH
= 4.0 mA
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min.,
I
OL
= 8.0 mA
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
A
I
OZ
Output Leakage
Current
GND < V
I
< V
CC
,
Output Disabled
5
+5
A
I
OS
Output Short
Circuit Current
[3]
V
CC
= Max.,
V
OUT
= GND
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
80
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE
1
> V
IH
or CE
2
< V
IL
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
40
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE
1
> V
CC
0.3V,
or CE
2
< 0.3V,
V
IN
> V
CC
0.3V,
or V
IN
< 0.3V, f = 0
10
mA
Capacitance
[ 4]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
9
pF
C
OUT
Output Capacitance
8
pF
Note:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
T
A
is the case temperature.
3.
Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4.
Tested initially and after any design or process changes that may affect these parameters.
WCFS1008C3E
WCFS1008C9E
Page 3 of 8
AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
3 ns
3 ns
OUTPUT
R1 480
R1 480
R2
255
R2
255
167
Equivalent to:
VENIN EQUIVALENT
1.73V
TH
Switching Characteristics
[5]
Over the Operating Range
WCFS1008C3E
WCFS1008C9E-15
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
15
ns
t
AA
Address to Data Valid
15
ns
t
OHA
Data Hold from Address Change
3
ns
t
ACE
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
15
ns
t
DOE
OE LOW to Data Valid
7
ns
t
LZOE
OE LOW to Low Z
0
ns
t
HZOE
OE HIGH to High Z
[6, 7]
7
ns
t
LZCE
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[7]
3
ns
t
HZCE
CE
1
HIGH to High Z, CE
2
LOW to High Z
[6, 7]
7
ns
t
PU
CE
1
LOW to Power-Up, CE
2
HIGH to Power-Up
0
ns
t
PD
CE
1
HIGH to Power-Down, CE
2
LOW to Power-Down
15
ns
WRITE CYCLE
[8]
t
WC
Write Cycle Time
[9]
15
ns
t
SCE
CE
1
LOW to Write End, CE
2
HIGH to Write End
12
ns
t
AW
Address Set-Up to Write End
12
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Set-Up to Write Start
0
ns
t
PWE
WE Pulse Width
12
ns
t
SD
Data Set-Up to Write End
8
ns
t
HD
Data Hold from Write End
0
ns
t
LZWE
WE HIGH to Low Z
[7]
3
ns
t
HZWE
WE LOW to High Z
[6, 7]
7
ns
Note:
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8.
The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9.
The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
WCFS1008C3E
WCFS1008C9E
Page 4 of 8
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min.
Max
Unit
V
DR
V
CC
for Data Retention
No input may exceed V
CC
+ 0.5V
V
CC
= V
DR
= 2.0V,
CE
1
> V
CC
0.3V or CE
2
< 0.3V,
V
IN
> V
CC
0.3V or V
IN
< 0.3V
2.0
V
t
CDR
Chip Deselect to Data Retention Time
0
ns
t
R
Operation Recovery Time
200
s
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1
[10, 11]
Read Cycle No. 2 (OE Controlled)
[11, 12]
Note:
10. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE
1
transition LOW and CE
2
transition HIGH.
4.5V
4.5V
CE
V
CC
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
1
I
CC
I
SB
IMPEDANCE
ADDRESS
CE
2
DATA OUT
V
CC
SUPPLY
CURRENT
WCFS1008C3E
WCFS1008C9E
Page 5 of 8
Write Cycle No. 1 (CE
1
or CE
2
Controlled)
[10, 14]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[10, 14]
Notes:
13. Data I/O is high impedance if OE = V
IH
.
14. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms
(continued)
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
1
ADDRESS
CE
2
WE
DATA I/O
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
1
ADDRESS
CE
2
WE
DATA I/O
OE
NOTE
15
WCFS1008C3E
WCFS1008C9E
Page 6 of 8
Write Cycle No. 3 (WE Controlled, OE LOW)
[14]
Switching Waveforms
(continued)
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
SCE
t
WC
t
HZWE
CE
1
ADDRESS
CE
2
WE
DATA I/O
NOTE
15
Truth Table
CE
1
CE
2
OE
WE
I/O
0
I/O
7
Mode
Power
H
X
X
X
High Z
Power-Down
Standby (I
SB
)
X
L
X
X
High Z
Power-Down
Standby (I
SB
)
L
H
L
H
Data Out
Read
Active (I
CC
)
L
H
X
L
Data In
Write
Active (I
CC
)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (I
CC
)
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
15
WCFS1008C3E-JC15
J
32-Lead (300-Mil) Molded SOJ
Commercial
WCFS1008C9E-JC15
J
32-Lead (400-Mil) Molded SOJ
WCFS1008C3E
WCFS1008C9E
Page 7 of 8
Package Diagrams
32-Lead (300-Mil) Molded SOJ J
32-Lead (400-Mil) Molded SOJ J
WCFS1008C3E
WCFS1008C9E
Page 8 of 8
Document Title: WCFS1008C3E WCFS1008C9E 128K x 8 SRAM
REV.
Issue Date
Orig. of Change
Description of Change
**
4/12/02
XFL
NEW DATASHEET
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