256K x 16 Static RAM
WCFS4016V1C
April 12, 2002
S4016V1C
Features
High speed
-- t
AA
= 12ns
2.0V Data Retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
The WCFS4016V1C is high-performance CMOS Static RAMs
organized as 262K words by 16 bits.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the devices is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The WCFS4016V1C is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground pinout.
14
15
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
O
W
DECODER
SE
N
S
E A
M
P
S
INPUT BUFFER
256K x 16
ARRAY
A
0
A
11
A
13
A
12
A
A
A
16
A
17
A
9
A
10
1024 x 4096
I/O
0
I/O
7
OE
I/O
8
I/O
15
CE
WE
BLE
BHE
Top View
SOJ
TSOP II
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
V
CC
A
5
A
6
A
7
A
8
A
0
A
1
OE
V
SS
A
17
I/O
15
A
2
CE
I/O
2
I/O
0
I/O
1
BHE
A
3
A
4
18
17
20
19
I/O
3
27
28
25
26
22
21
23
24
V
SS
I/O
6
I/O
4
I/O
5
I/O
7
A
16
A
15
BLE
V
CC
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
I/O
8
A
14
A
13
A
12
A
11
A
9
A
10
NC
Selection Guide
WCFS4016V1C 12ns
Maximum Access Time (ns)
12
Maximum Operating Current (mA)
Comm'l
85
Maximum CMOS Standby Current (mA)
Comm'l
10
WCFS4016V1C
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage on V
CC
to Relative GND
[1]
.... 0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................ 0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +70
C
3.3V
0.3V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
12ns
Unit
Min.
Max.
V
OH
Output HIGH Voltage
V
CC
= Min.,
I
OH
= 4.0 mA
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min.,
I
OL
= 8.0 mA
0.4
V
V
IH
Input HIGH Voltage
2.0
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
A
I
OZ
Output Leakage Current
GND < V
OUT
< V
CC
, Output Disabled
1
+1
A
I
CC
V
CC
Operating
Supply Current
V
CC
= Max., f = f
MAX
=
1/t
RC
Comm'l
85
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
40
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V,
or V
IN
< 0.3V, f = 0
Comm'l
10
mA
Capacitance
[2]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz, V
CC
= 3.3V
8
pF
C
OUT
I/O Capacitance
8
pF
Note:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
Tested initially and after any design or process changes that may affect these parameters.
WCFS4016V1C
3
AC Test Loads and Waveforms
1041CV334
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
R1 317
R2
351
Rise time > 2V/ns
Fall time:
> 2V/ns
(c)
OUTPUT
50
Z
0
=50
V
TH
= 1.5V
30pF
INCLUDING
ALL COMPONENTS OF
TEST EQUIPMENT
(b)
WCFS4016V1C
4
AC Switching Characteristics
[3]
Over the Operating Range
WCFS4016V1C 12ns
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
power
[4]
V
CC
(typical) to the first access
1
s
t
RC
Read Cycle Time
12
ns
t
AA
Address to Data Valid
12
ns
t
OHA
Data Hold from Address Change
3
ns
t
ACE
CE LOW to Data Valid
12
ns
t
DOE
OE LOW to Data Valid
6
ns
t
LZOE
OE LOW to Low Z
0
ns
t
HZOE
OE HIGH to High Z
[5, 6]
6
ns
t
LZCE
CE LOW to Low Z
[6]
3
ns
t
HZCE
CE HIGH to High Z
[5, 6]
6
ns
t
PU
CE LOW to Power-Up
0
ns
t
PD
CE HIGH to Power-Down
12
ns
t
DBE
Byte Enable to Data Valid
6
ns
t
LZBE
Byte Enable to Low Z
0
ns
t
HZBE
Byte Disable to High Z
6
ns
WRITE CYCLE
[7, 8]
t
WC
Write Cycle Time
12
ns
t
SCE
CE LOW to Write End
8
ns
t
AW
Address Set-Up to Write End
8
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Set-Up to Write Start
0
ns
t
PWE
WE Pulse Width
8
ns
t
SD
Data Set-Up to Write End
6
ns
t
HD
Data Hold from Write End
0
ns
t
LZWE
WE HIGH to Low Z
[6]
3
ns
t
HZWE
WE LOW to High Z
[5, 6]
6
ns
t
BW
Byte Enable to End of Write
8
ns
Notes:
3.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
4.
t
POWER
gives the minimum amount of time that the power supply should be at typical Vcc values until the first memory access can be performed.
5.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5pF as in part (a) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
6.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7.
The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8.
The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
WCFS4016V1C
5
Switching Waveforms
Notes:
9.
Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Read Cycle No. 1
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
[9, 10]
Read Cycle No. 2 (OE Controlled)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZBE
t
PD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
t
DBE
t
LZBE
t
HZCE
BHE, BLE
[10, 11]
CURRENT
I
CC
I
SB
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