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Электронный компонент: WCMA1016U4X

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64K x 16 Static RAM
WCMA1016U4X
1
Features
High Speed
-- 55ns and 70ns availability
Low voltage range
-- 2.7V
-3.6V
Ultra-low active power
Low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The WCMA1016U4X is a high-performance CMOS static
RAM organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This device s ideal for portable applications such as cellular
telephones. The device also has an automatic power-down
feature that significantly reduces power consumption by 99%
when addresses are not toggling. The device can also be put
into standby mode when deselected (CE HIGH or both BLE
and BHE are HIGH). The input/output pins (I/O
0
through I/O
15
)
are placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), both Byte High En-
able and Byte Low Enable are disabled (BHE, BLE HIGH), or
during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
8
to I/O
15
. See the
Truth Table at the back of this data sheet for a complete de-
scription of read and write modes.
The WCMA1016U4X is available in a 48-ball FBGA package.
Logic Block Diagram
64K x 16
RAM Array
I/O
0
I/O
7
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
2048 X 512
SENSE AMPS
DATA IN DRIVERS
OE
I/O
8
I/O
15
CE
WE
BLE
BHE
ROW DECODER
A
7
A
6
A
3
A
0
A
2
A
1
A
5
A
4
A
8
Power - Down
Circuit
BHE
BLE
CE
A
9
A
10
2
WCMA1016U4X
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... -65C to +150C
Ambient Temperature with
Power Applied
.................................................. -55C to +125C
Supply Voltage to Ground Potential
.................-0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[2]
........................................ -0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
.................................... -0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Notes:
1.
NC pins are not connected to the die.
2.
V
IL
(min) =
-2.0V for pulse durations less than 20 ns.
3.
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25C.
Pin Configuration
[1]
WE
V
cc
A
11
A
10
NC
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
V
ss
A
7
I/O
0
BHE
NC
NC
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
NC
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
FBGA
NC
Top View
Operating Range
Device
Range
Ambient Temperature
V
CC
WCMA1016U4X
Industrial
-40C to +85C
2.7V to 3.6V
Product Portfolio
Product
V
CC
Range
Speed
Power Dissipation (Industrial)
Operating, I
CC
(f=f
max
)
Standby (I
SB2
)
V
CC(min.)
V
CC(typ.)
[3]
V
CC(max.)
Max.
Max.
WCMA1016U4X
2.7V
3.0V
3.6V
70 ns
15 mA
15 A
55 ns
20 mA
3
WCMA1016U4X
Electrical Characteristics
Over the Operating Range
Test Conditions
WCMA1016U4X-70/55
Param-
eter
Description
Min.
Typ.
[3]
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
=
-0.1 mA
V
CC
= 2.7V
2.2
V
V
OL
Output LOW Voltage
I
OL
= 2.1 mA
V
CC
= 2.7V
0.4
V
V
IH
Input HIGH Voltage
2.0
V
CC
+ 0.3V
V
V
IL
Input LOW Voltage
-0.3
0.4
V
I
IX
Input Leakage Current GND < V
I
< V
CC
-1
+1
A
I
OZ
Output Leakage Cur-
rent
GND < V
O
< V
CC
, Output Disabled
-1
+1
A
I
CC
V
CC
Operating Supply
Current
f = f
MAX
= 1/t
RC
V
CC
= 3.6V
I
OUT
= 0 mA
CMOS levels
70ns
15
mA
55ns
20
I
SB1
Automatic CE
Power-Down Current--
TTL Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
<V
IL
, f = f
MAX
2
A
I
SB2
Automatic CE
Power-Down Cur-
rent-- CMOS Inputs
Max. V
CC
, CE > V
CC
-0.3V
V
IN
> V
CC
-0.3V or V
IN
< 0.3V, f = 0
0.5
15
Capacitance
[4]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz,
V
CC
= V
CC(typ)
6
pF
C
OUT
Output Capacitance
8
pF
Thermal Resistance
Description
Test Conditions
Symbol
BGA
Units
Thermal Resistance (Junction
to Ambient)
[4]
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board
JA
55
C/W
Thermal Resistance (Junction
to Case)
[4]
JC
16
C/W
Note:
4.
Tested initially and after any design or process changes that may affect these parameters.
4
WCMA1016U4X
Notes:
5.
Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
>
100
s or stable at V
CC(min)
>
100
s.
6.
BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
AC Test Loads and Waveforms
V
CC
Typ
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Rise Time:
1 V/ns
Fall Time:
1 V/ns
Parameters
3.3V
UNIT
R1
1213
Ohms
R2
1378
Ohms
R
TH
645
Ohms
V
TH
1.75
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.
[3]
Max.
Unit
V
DR
V
CC
for Data Retention
2.0
3.6
V
I
CCDR
Data Retention Current
V
CC
= 2.0V
CE > V
CC
- 0.3V,
V
IN
> V
CC
- 0.3V or V
IN
< 0.3V
0.5
15
A
t
CDR
[4]
Chip Deselect to Data
Retention Time
0
ns
t
R
[5]
Operation Recovery Time
t
RC
ns
Data Retention Waveform
[6]
V
CC(min.)
V
CC(min.)
t
CDR
V
DR
> 2.0 V
DATA RETENTION MODE
t
R
CE or
V
CC
BHE.BLE
5
WCMA1016U4X
Switching Characteristics
Over the Operating Range
[7]
WCMA1016U4X-55 WCMA1016U4X-70
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
55
70
ns
t
AA
Address to Data Valid
55
70
ns
t
OHA
Data Hold from Address Change
10
10
ns
t
ACE
CE LOW to Data Valid
55
70
ns
t
DOE
OE LOW to Data Valid
25
35
ns
t
LZOE
OE LOW to Low Z
[8]
5
5
ns
t
HZOE
OE HIGH to High Z
[8, 9]
20
25
ns
t
LZCE
CE LOW to Low Z
[8]
10
10
ns
t
HZCE
CE HIGH to High Z
[8, 9]
20
25
ns
t
PU
CE LOW to Power-Up
0
0
ns
t
PD
CE HIGH to Power-Down
55
70
ns
t
DBE
BLE / BHE LOW to Data Valid
55
70
ns
t
LZBE
BLE / BHE LOW to Low Z
[8]
5
5
ns
t
HZBE
BLE / BHE HIGH to High Z
[8, 9]
20
25
ns
WRITE CYCLE
[10]
t
WC
Write Cycle Time
55
70
ns
t
SCE
CE LOW to Write End
45
60
ns
t
AW
Address Set-Up to Write End
45
60
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
ns
t
PWE
WE Pulse Width
40
50
ns
t
BW
BLE / BHE LOW to Write End
45
60
ns
t
SD
Data Set-Up to Write End
25
30
ns
t
HD
Data Hold from Write End
0
0
ns
t
HZWE
WE LOW to High Z
[8, 9]
25
25
ns
t
LZWE
WE HIGH to Low Z
[8]
5
5
ns
Note:
7.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ)
/2, input pulse levels of 0 to V
CC(typ)
, and output
loading of the specified I
OL
/I
OH
and 30 pF load capacitance.
8.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9.
t
HZOE
, t
HZCE
, t
HZBE
and t
HZWE
transitions are measured when the outputs enter a high impedence state.
10. The internal write time of the memory is defined by the overlap of WE, CE
= V
IL
, BHE and/or BLE =V
IL
. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the
edge of the signal that terminates the write.