256K x 8 Static RAM
WCMA2008U1B
W C M A 2 0 0 8 U 1 B
Features
High Speed
-- 70ns availability
Voltage range
-- 2.7V3.3V
Ultra low active power
-- Typical active current: 1 mA @ f = 1MHz
-- Typical active current: 7 mA @ f = f
max
(70ns speed)
Low standby power
Easy memory expansion with CE
1
,CE
2
,and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The WCMA2008U1B is a high-performance CMOS static
RAM organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is device is ideal for portable applications. The device
also has an automatic power-down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
1
HIGH or CE
2
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
2
) HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is
then written into the location specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip En-
able (CE
1
) and Output Enable (OE) LOW while forcing Write
Enable (WE) and Chip Enable 2 (CE
2
) HIGH. Under these
conditions, the contents of the memory location specified by
the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW).
The WCMA2008U1B is available in a 36-ball FBGA package.
Logic Block Diagram
1
5
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
O
W
D
E
C
O
D
E
R
S
E
N
S
E
A
M
P
S
Data in Drivers
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
128K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
2
A
1
4
A
1
3
CE
1
A
1
6
A
9
A
1 0
A
11
A A
1
7
CE
2
WCMA2008U1B
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................65C to +150C
Ambient Temperature with
Power Applied...............................................55C to +125C
Supply Voltage to Ground Potential..... ..........0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
........................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
..................................0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................20 mA
Static Discharge Voltage ..........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ......................................................>200 mA
Notes:
1.
V
IL(min.)
= 2.0V for pulse durations less than 20 ns.
2.
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25C.
Pin Configurations
A
15
V
CC
A
13
A
12
A
5
CE
2
WE
A
7
I/O
4
I/O
5
A
4
I/O
6
I/O
7
A
11
A
10
A
1
V
SS
I/O
0
A
2
A
8
A
6
A
3
A
0
V
CC
I/O
1
I/O
2
I/O
3
A
17
NC
A
16
CE
1
OE
A
9
A
14
3
2
6
5
4
1
D
E
B
A
C
F
G
H
FBGA (Top View)
DNU
V
SS
Operating Range
Product
Range
Ambient Temperature
V
CC
WCMA2008U1B
Industrial
40C to +85C
2.7V to 3.3V
Product Portfolio
Product
V
CC
Range
Speed
Power Dissipation (Industrial)
Operating, I
CC
Standby (I
SB2
)
f = 1 MHz
f = f
max
Min.
Typ.
[2]
Max.
Typ.
[2]
Max.
Typ.
[2]
Max.
Typ.
[2]
Max.
WCMA2008U1B
2.7V
3.0V
3.3V
70 ns
1.5 mA
3 mA
7 mA
15 mA
2
A
10
A
WCMA2008U1B
3
Electrical Characteristics Over the Operating Range
Test Conditions
WCMA2008U1B-70
Param-
eter
Description
Min.
Typ.
[2]
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= 1.0 mA
V
CC
= 2.7V
2.4
V
V
OL
Output LOW Voltage
I
OL
= 2.1 mA
V
CC
= 2.7V
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3V
V
V
IL
Input LOW Voltage
0.3
0.8
V
I
IX
Input Leakage Current
GND < V
I
< V
CC
1
+1
A
I
OZ
Output Leakage Current GND < V
O
< V
CC
, Output Disabled
1
+1
A
I
CC
V
CC
Operating Supply
Current
f =f
MAX
= 1/t
RC
V
CC
= 3.3V
I
OUT
= 0 mA
CMOS Levels
7
15
mA
f = 1 MHz
1.5
3
I
SB1
Automatic CE
Power-Down Current --
CMOS Inputs
CE
1
> V
CC
0.2V or CE
2
< 0.2V
V
IN
> V
CC
0.2V or V
IN
< 0.2V,
f = f
max
(Address and Data Only),
f = 0 (OE,WE)
2
10
A
I
SB2
Automatic CE
Power-Down Current--
CMOS Inputs
CE
1
> V
CC
0.2V or CE
2
< 0.2V
V
IN
> V
CC
-
0.2V or V
IN
< 0.2V,
f = 0, V
CC
=3.3V
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz,V
CC
= Vcc
(typ)
6
pF
C
OUT
Output Capacitance
8
pF
Thermal Resistance
Description
Test Conditions
Symbol
BGA
Unit
Thermal Resistance
[3]
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer print-
ed circuit board
JA
55
C/W
Thermal Resistance
[3]
(Junction to Case)
JC
16
C/W
Note:
3.
Tested initially and after any design or process changes that may affect these parameters.
WCMA2008U1B
4
AC Test Loads and Waveforms
Parameters
3.3V
Unit
R1
1105
Ohms
R2
1550
Ohms
R
TH
645
Ohms
V
TH
1.75
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.
[2]
Max.
Unit
V
DR
V
CC
for Data Retention
1.5
V
ccmax
V
I
CCDR
Data Retention Current
V
CC
= 1.5V
CE
1
> V
CC
0.2V or CE
2
< 0.2V
V
IN
> V
CC
-
0.2V or V
IN
< 0.2V
1
6
A
t
CDR
[3]
Chip Deselect to Data
Retention Time
0
ns
t
R
[4]
Operation Recovery
Time
t
RC
ns
Data Retention Waveform
Note:
4.
Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
s or stable at V
CC(min.)
>
100
s.
V
CC
Typ
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Fall time: 1 V/ns
Rise Time: 1 V/ns
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
t
R
CE
1
V
CC
CE
2
or
WCMA2008U1B
5
Switching Characteristics
Over the Operating Range
[5]
Parameter
Description
WCMA2008U1B-70
Unit
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
70
ns
t
AA
Address to Data Valid
70
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid
70
ns
t
DOE
OE LOW to Data Valid
35
ns
t
LZOE
OE LOW to Low Z
[6]
5
ns
t
HZOE
OE HIGH to High Z
[6, 7]
25
ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low Z
[6]
10
ns
t
HZCE
CE
1
HIGH or CE
2
LOW to High Z
[6, 7]
25
ns
t
PU
CE
1
LOW and CE
2
HIGH to Power-Up
0
ns
t
PD
CE
1
HIGH or CE
2
LOW to Power-Down
70
ns
WRITE CYCLE
[8,]
t
WC
Write Cycle Time
70
ns
t
SCE
CE
1
LOW and CE
2
HIGH to Write End
60
ns
t
AW
Address Set-Up to Write End
60
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Set-Up to Write Start
0
ns
t
PWE
WE Pulse Width
50
ns
t
SD
Data Set-Up to Write End
30
ns
t
HD
Data Hold from Write End
0
ns
t
HZWE
WE LOW to High Z
[6, 7]
25
ns
t
LZWE
WE HIGH to Low Z
[6]
10
ns
Notes:
5.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading
of the specified I
OL
/I
OH
and 30 pF load capacitance.
6.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7.
t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
8.
The internal write time of the memory is defined by the overlap of WE, CE
1
= V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the write.
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