128K x 16 Static RAM
WCMA2016U4B
1 * W C M A 2 0 1 6 U 4 B
Features
High Speed
-- 55ns and 70ns speed availability
Low Voltage range:
-- 2.7V-3.3V
Ultra-low active power
-- Typical active current: 1.5 mA @ f = 1MHz
-- Typical active current: 7 mA @ f = f
max
Low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The WCMA2016U4B is a high-performance CMOS static
RAMs organized as 128K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active cur-
rent. This device is ideal for portable applications such as cel-
lular telephones. The devices also have an automatic pow-
er-down feature that significantly reduces power consumption
by 80% when addresses are not toggling. The device can also
be put into standby mode reducing power consumption by
more than 99% when deselected (CE HIGH or both BLE and
BHE are HIGH). The input/output pins (I/O
0
through I/O
15
) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), both Byte High En-
able and Byte Low Enable are disabled (BHE, BLE HIGH), or
during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE ) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE ) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE ) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The WCMA2016U4B is available in a 48-ball FBGA package.
Logic Block Diagram
128K x 16
RAM Array
I/O
0
I/O
7
R
O
W
D
E
C
O
D
E
R
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
1
1
A
1
2
A
1
3
A
1
4
A
1
5
2048 x 1024
S
E
N
S
E
A
M
P
S
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
I/O
15
CE
WE
BLE
BHE
A
1
6
A
0
A
1
A
9
Power
-
Down
Circuit
BHE
BLE
CE
A
10
1 0
WCMA2016U4B
2
Pin Configuration
[1, 2]
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65C to +150C
Ambient Temperature with
Power Applied ............................................. 55C to +125C
Supply Voltage to Ground Potential ... 0.5V to V
ccmax
+ 0.5V
DC Voltage Applied to Outputs
in High Z State
[3]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[3]
.................................-0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Notes:
1.
NC pins are not connected to the die.
2.
E3 (DNU) can be left as NC or Vss to ensure proper application.
3.
V
IL(min.)
= 2.0V for pulse durations less than 20 ns.
4.
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25C.
WE
A
11
A
10
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
V
SS
A
7
I/O
0
BHE
NC
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
NC
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
FBGA (Top View)
A
16
DNU
V
CC
NC
Operating Range
Device
Range
Ambient
Temperature
V
CC
WCMA2016U4B
Industrial 40C to +85C 2.7V to 3.3V
Product Portfolio
Product
V
CC
Range(V)
Speed
(ns)
Power Dissipation (Industrial)
Operating, I
CC
(mA)
Standby, I
SB2
(
A)
f = 1 MHz
f = f
max
V
CC(min.)
V
CC(typ.)
[4]
V
CC(max.)
Typ.
[4]
Max.
Typ.
[4]
Max. Typ.
[4]
Max.
WCMA2016U4B
2.7
3.0
3.3
70
1.5
2
7
15
2
10
55
WCMA2016U4B
3
WCMA2016U4B-55
WCMA2016U4B-70
Param-
eter
Description
Test Conditions
Min.
Typ.
[4]
Max.
Min.
Typ.
[4]
Max.
Unit
V
OH
Output HIGH Voltage I
OH
= 1.0 mA
V
CC
= 2.7V
2.4
2.4
V
V
OL
Output LOW Voltage
I
OL
= 2.1mA
V
CC
= 2.7V
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+
0.5V
2.2
V
CC
+
0.5V
V
V
IL
Input LOW Voltage
0.3
0.8
0.3
0.8
V
I
IX
Input Leakage Cur-
rent
GND < V
I
< V
CC
1
+1
1
+1
A
I
OZ
Output Leakage Cur-
rent
GND < V
O
< V
CC
, Output Dis-
abled
1
+1
1
+1
A
I
CC
V
CC
Operating Supply
Current
f = f
MAX
= 1/t
RC
V
CC
= 3.3V
I
OUT
= 0 mA
CMOS Lev-
els
7
15
7
15
mA
f = 1 MHz
1.5
3
1.5
3
I
SB1
Automatic CE
Power-Down Cur-
rent-- CMOS Inputs
CE > V
CC
0.2V
V
IN
> V
CC
0.2V or V
IN
< 0.2V,
f = f
max
(Address and Data Only),
f=0 (OE,WE,BHE and BLE)
2
10
2
10
A
I
SB2
Automatic CE
Power-Down Cur-
rent-- CMOS Inputs
CE > V
CC
0.2V
V
IN
> V
CC
0.2V or V
IN
< 0.2V,
f = 0, Vcc=3.3V
Capacitance
[5]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz,
V
CC
= V
CC(typ.)
6
pF
C
OUT
Output Capacitance
8
pF
Electrical Characteristics
Over the Operating Range
Thermal Resistance
Description
Test Conditions
Symbol
BGA
Units
Thermal Resistance
(Junction to Ambient)
[5]
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer
printed circuit board
JA
55
C/W
Thermal Resistance
(Junction to Case)
[5]
JC
16
C/W
Note:
5.
Tested initially and after any design or process changes that may affect these parameters.
WCMA2016U4B
4
AC Test Loads and Waveforms
V
CC
Typ
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
R
T H
R1
Rise TIme: 1 V/ns
Fall Time: 1 V/ns
Parameters
3.0V
Unit
R1
1.105
KOhms
R2
1.550
KOhms
R
TH
0.645
KOhms
V
TH
1.75
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.
[4]
Max.
Unit
V
DR
V
CC
for Data Retention
1.5
V
ccmax
V
I
CCDR
Data Retention Current
V
CC
= 1.5V
CE > V
CC
0.2V,
V
IN
> V
CC
0.2V or V
IN
< 0.2V
0.5
7.5
A
t
CDR
[5]
Chip Deselect to Data
Retention Time
0
ns
t
R
[6]
Operation Recovery Time
70
ns
Data Retention Waveform
[7]
Note:
6.
Full Device AC operation requires linear V
C C
ramp from V
DR
to V
CC(min.)
> 100
s or stable at V
CC(min.)
> 100
s.
7.
BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
t
R
CE or
V
CC
BHE.BLE
WCMA2016U4B
5
Switching Characteristics
Over the Operating Range
[8]
Parameter
Description
55ns
70 ns
Min
Max
Min
Max
Unit
READ CYCLE
t
RC
Read Cycle Time
55
70
ns
t
AA
Address to Data Valid
55
70
ns
t
OHA
Data Hold from Address Change
10
10
ns
t
ACE
CE LOW to Data Valid
55
70
ns
t
DOE
OE LOW to Data Valid
25
35
ns
t
LZOE
OE LOW to Low Z
[9]
5
5
ns
t
HZOE
OE HIGH to High Z
[9, 11]
25
25
ns
t
LZCE
CE LOW to Low Z
[9]
10
10
ns
t
HZCE
CE HIGH to High Z
[9, 11]
25
25
ns
t
PU
CE LOW to Power-Up
0
0
ns
t
PD
CE HIGH to Power-Down
55
70
ns
t
DBE
BHE / BLE LOW to Data Valid
55
70
ns
t
LZBE
[10]
BHE / BLE LOW to Low Z
[9]
5
5
ns
t
HZBE
BHE / BLE HIGH to High Z
[9, 11]
25
25
ns
WRITE CYCLE
[12]
t
WC
Write Cycle Time
55
70
ns
t
SCE
CE LOW to Write End
45
60
ns
t
AW
Address Set-Up to Write End
45
60
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
ns
t
PWE
WE Pulse Width
40
50
ns
t
BW
BHE / BLE Pulse Width
50
60
ns
t
SD
Data Set-Up to Write End
25
30
ns
t
HD
Data Hold from Write End
0
0
ns
t
HZWE
WE LOW to High Z
[9, 11]
20
25
ns
t
LZWE
WE HIGH to Low Z
[9]
5
10
ns
Notes:
8.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of
the specified I
OL
/I
OH
and 30 pF load capacitance.
9.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for
any given device.
10. If both byte enables are toggled together this value is 10ns
11. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured
when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE
= V
IL
, BHE and/or BLE = V
IL
. All signals must be ACTIVE to initiate a write and
any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the write..
WCMA2016U4B
6
Switching Waveforms
Notes:
13. Device is continuously selected.
OE, CE
= V
IL
,
BHE, BLE
= V
IL
.
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE,
BHE, BLE
transition LOW.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
Read Cycle No. 1 (Address Transistion Controlled)
[13, 14]
Read Cycle No. 2 (OE Controlled)
[14, 15]
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE
t
LZOE
ADDRESS
t
DOE
t
LZOE
t
DBE
WCMA2016U4B
7
Notes:
16. Data I/O is high-impedance if OE = V
IH
.
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
18. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
W E
DATA I/O
OE
NOTE 18
Write Cycle No. 1(WE Controlled)
BHE/BLE
t
BW
[12, 16, 17]
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
W E
DATA I/O
OE
NOTE 18
Write Cycle No. 2 (CE
Controlled)
BHE/BLE
t
BW
[12, 16, 17]
t
SA
WCMA2016U4B
8
Switching Waveforms
(continued)
DATA
IN
VALID
t
H D
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATA I/O
NOTE 18
Write Cycle No. 3 (WE Controlled, OE LOW)
t
BW
BHE /BLE
[17]
DATA I/O
ADDRESS
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
CE
WE
DATA
IN
VALID
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[17]
NOTE 18
t
BW
BHE/BLE
t
SCE
t
PWE
WCMA2016U4B
9
Typical DC and AC Parameters
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
High Z
Deselect/Power-Down
Standby (I
SB
)
X
X
X
H
H
High Z
Deselect/Power-Down
Standby (I
SB
)
L
H
L
L
L
Data Out (I/O
O
I/O
15
)
Read
Active (I
CC
)
L
H
L
H
L
Data Out (I/O
O
I/O
7
);
I/O
8
I/O
15
in High Z
Read
Active (I
CC
)
L
H
L
L
H
Data Out (I/O
8
I/O
15
);
I/O
0
I/O
7
in High Z
Read
Active (I
CC
)
L
H
H
L
L
High Z
Output Disabled
Active (I
CC
)
L
H
H
H
L
High Z
Output Disabled
Active (I
CC
)
L
H
H
L
H
High Z
Output Disabled
Active (I
CC
)
L
L
X
L
L
Data In (I/O
O
I/O
15
)
Write
Active (I
CC
)
L
L
X
H
L
Data In (I/O
O
I/O
7
);
I/O
8
I/O
15
in High Z
Write
Active (I
CC
)
L
L
X
L
H
Data In (I/O
8
I/O
15
);
I/O
0
I/O
7
in High Z
Write
Active (I
CC
)
12.0
10.0
6.0
4.0
2.0
2.7
3.3
0.0
8.0
I
C
C
(
m
A
)
SUPPLY VOLTAGE (V)
(f = 1 MHz)
(f = f
max
)
14.0
3.0
12.0
10.0
6.0
4.0
3.0
0
8.0
I
S
B
(
A
)
Standby Current vs. Supply Voltage
SUPPLY VOLTAGE (V)
2.0
2.7
3.3
50
30
20
10
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
0
40
T
A
A
(
n
s
)
60
3.0
2.7
3.3
Operating Current vs. Supply Voltage
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC (typ.)
, T
A
= 25C)
WCMA2016U4B
10
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
70
WCMA2016U4B-FF70
FB48A
48-Ball Fine Pitch BGA
Industrial
55
WCMA2016U4B-FF55
.
WCMA2016U4B
11
Package Diagrams
48-Ball (6.0 mm x 8.0 mm x 1.0 mm) Fine Pitch BGA, FB48A
Top View
Bottom View
WCMA2016U4B
12
Document Title: WCMA2016U4B, 128K x 16 STATIC RAM
REV.
Spec #
ECN #
Issue Date
Orig. of Change
Description of Change
**
38-05320
117494
7/19/02
CBD
New Datasheet
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