512K x 8 Static RAM
WCMA4008C1X
Features
Voltage Range
-- 4.5V5.5V
Low active power
-- Typical active current: 2.5 mA @ f = 1 MHz
-- Typical active current: 12.5 mA @ f = f
max
Low standby current
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
and OE features
CMOS for optimum speed/power
Functional Description
The WCMA4008C1X is a high-performance CMOS static
RAM organized as 512K words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that reduces power
consumption by more than 99% when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location speci-
fied on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the con-
tents of the memory location specified by the address pins will
appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The WCMA4008C1X is available in a standard 32-pin
450-mil-wide body width SOIC.
18
13
Logic Block Diagram
Pin Configuration
A
1
A
4
A
5
A
6
A
7
A
12
A
14
A
16
COLUMN
DECODER
ROW DECODER
SE
N
S
E A
M
P
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
2
A
15
A
3
A
CE
A A
8
A
17
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
12
13
29
32
31
30
16
15
17
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
WE
V
CC
A
15
A
13
A
8
A
9
I/O
7
I/O
6
I/O
5
I/O
4
A
2
I/O
0
I/O
1
I/O
2
CE
OE
A
10
I/O
A
1
A
0
A
11
A
9
A
11
A
18
A
10
Top View
SOIC
GND
I/O
3
A
17
WCMA4008C1X
Page 2 of 10
Notes:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
Typical values are measured at V
CC
= 5V, T
A
= 25C, and are included for reference only and are not tested or guaranteed.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. 65C to +150C
Ambient Temperature with
Power Applied............................................. 55C to +125C
Supply Voltage on V
CC
to Relative GND ....... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
.....................................0.5V to V
CC
+0.5V
DC Input Voltage
[1]
..................................0.5V to V
CC
+0.5V
Current into Outputs (LOW) .........................................20 mA
Static Discharge Voltage...............................................2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .....................................................>200 mA
Product Portfolio
Product
V
CC
Range
Speed
Temp.
Power Dissipation
Operating, Icc
Standby (I
SB2
)
f = f
max
Typ.
[2]
Max.
Min.
Typ.
Max.
Typ.
[3]
Max.
WCMA4008C1X
4.5 V
5.0V
5.5V
70 ns
Ind'l
12.5 mA
20 mA
4
A
20
A
Operating Range
Range
Ambient
Temperature
V
CC
Industrial
40C to +85C
4.5V5.5V
WCMA4008C1X
Page 3 of 10
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
WCMA4008C1X
Unit
Min.
Typ.
[2]
Max.
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 1 mA
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 2.1 mA
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+0.3
V
V
IL
Input LOW Voltage
0.3
0.8
V
I
IX
Input Leakage Current
GND
V
I
V
CC
1
+1
A
I
OZ
Output Leakage
Current
GND
V
I
V
CC
, Output Disabled
1
+1
A
I
CC
V
CC
Operating
Supply Current
f = f
MAX
= 1/t
RC
I
OUT
=0 mA
V
CC
= Max.,
12.5
20
mA
f = 1 MHz
2.5
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
,CE
V
IH
V
IN
V
IH
or V
IN
V
IL
, f = f
MAX
1.5
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
, CE
V
CC
0.3V,
V
IN
V
CC
0.3V, or V
IN
0.3V, f =0
4
20
A
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz,
V
CC
= 5.0V
6
pF
C
OUT
Output Capacitance
8
pF
AC Test Loads and Waveforms
Note:
3.
Tested initially and after any design or process changes that may affect these parameters.
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
990
(a)
90%
10%
3.0V
GND
90%
10%
3 ns
3 ns
OUTPUT
639
Equivalent to:
THEVENIN EQUIVALENT
1.77V
R1 1800
ALL INPUT PULSES
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
R2
990
R1 1800
100 pF
WCMA4008C1X
Page 4 of 10
Switching Characteristics
[4]
Over the Operating Range
WCMA4008C1X
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
70
ns
t
AA
Address to Data Valid
70
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE LOW to Data Valid
70
ns
t
DOE
OE LOW to Data Valid
35
ns
t
LZOE
OE LOW to Low Z
[5]
5
ns
t
HZOE
OE HIGH to High Z
[5, 6]
25
ns
t
LZCE
CE LOW to Low Z
[5]
10
ns
t
HZCE
CE HIGH to High Z
[5, 6]
25
ns
t
PU
CE LOW to Power-Up
0
ns
t
PD
CE HIGH to Power-Down
70
ns
WRITE CYCLE
[7]
t
WC
Write Cycle Time
70
ns
t
SCE
CE LOW to Write End
60
ns
t
AW
Address Set-Up to Write End
60
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Set-Up to Write Start
0
ns
t
PWE
WE Pulse Width
55
ns
t
SD
Data Set-Up to Write End
30
ns
t
HD
Data Hold from Write End
0
ns
t
LZWE
WE HIGH to Low Z
[5]
5
ns
t
HZWE
WE LOW to High Z
[5, 6]
25
ns
Notes:
4.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
5.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
6.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
7.
The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
WCMA4008C1X
Page 5 of 10
Data Retention Characteristics
(Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.
[2]
Max.
Unit
V
DR
V
CC
for Data Retention
2.0
V
I
CCDR
Data Retention Current
No input may exceed
V
CC
+ 0.3V
V
CC
= V
DR
= 3.0V
CE > V
CC
0.3V
V
IN
> V
CC
0.3V or
V
IN
< 0.3V
20
A
t
CDR
[3]
Chip Deselect to Data
Retention Time
0
ns
t
R
[8]
Operation Recovery
Time
t
RC
ns
Data Retention Waveform
3.0V
3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
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