256K x 16 Static RAM
WCMA4016U1X
Weida Semiconductor, Inc.
Y62147BV
LTM
Features
Low voltage range: 2.7V3.6V
Ultra-low active, standby power
Easy memory expansion with CE
1
and CE
2
and OE fea-
tures
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
[1]
The WCMA4016U1X is a high-performance CMOS static
RAM organized as 262,144 words by 16 bits. This device
features advanced circuit design to provide ultra-low active
current and standby current. This is ideal for providing more
battery life in portable applications such as cellular telephones.
The device also has an automatic power-down feature that
significantly reduces power consumption by 99% when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE
1
HIGH or CE
2
LOW or
both BHE and BLE are HIGH). The input/output pins (I/O
0
through I/O
15
) are placed in a high-impedance state when:
deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE
1
LOW, CE
2
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
18
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O
8
to I/O
15
. See the truth table at the back of this
datasheet for a complete description of read and write modes.
.
Logic Block Diagram
Pin Configurations
I/O
0
I/O
7
RO
W
DE
C
O
D
E
R
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
S
E
N
S
E AM
PS
DATA IN DRIVERS
A
4
A
3
I/O
8
I/O
15
A
10
A
16
A
0
A
1
A
17
A
9
Power
-
Down
Circuit
BHE
BLE
WE
V
CC
A
11
A
10
NC
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
V
SS
A
7
I/O
0
BHE
CE
2
A
17
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
NC
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
FBGA (Top View)
256K 16
RAM Array
2048 2048
WE
BLE
BHE
CE
2
CE
1
OE
CE
2
CE
1
Preliminary
WCMA4016U1X
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65C to +150C
Ambient Temperature with
Power Applied............................................. 55C to +125C
Supply Voltage to Ground Potential ............... 0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................... -
0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2100V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Device
Range
Ambient
Temperature
V
CC
WCMA4016U1X
Industrial
40C to +85C
2.7V to
3.6V
Product Portfolio
Product
V
CC
Range
Power
Speed
(ns)
Power Dissipation (Industrial)
Operating (I
CC
)
Standby (I
SB2
)
V
CC(min.)
V
CC(typ.)
[2]
V
CC(max.)
Typ.
[2]
Maximum
Typ.
[2]
Maximum
WCMA4016U1X
2.7V
3.0V
3.6V
LL
70
7 mA
15 mA
2
A
20
A
Electrical Characteristics
Over the Operating Range
WCMA4016U1X
Parameter
Description
Test Conditions
Min.
Typ.
[2]
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= 1.0 mA
V
CC
= 2.7V
2.4
V
V
OL
Output LOW Voltage
I
OL
= 2.1 mA
V
CC
= 2.7V
0.4
V
V
IH
Input HIGH Voltage
V
CC
= 3.6V
2.2
V
CC
+ 0.5V
V
V
IL
Input LOW Voltage
V
CC
= 2.7V
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
1
+1
A
I
OZ
Output Leakage Current
GND < V
O
< V
CC
, Output Disabled
1
+1
+1
A
I
CC
V
CC
Operating Supply
Current
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
,
CMOS Levels
V
CC
= 3.6V
7
15
mA
I
OUT
= 0 mA, f = 1 MHz,
CMOS Levels
1
2
mA
I
SB1
Automatic CE
Power-Down Current--
CMOS Inputs
CE
1
> V
CC
-
0.3V, CE
2
< 0.3V
V
IN
>V
CC
0.3V, V
IN
<0.3V)
f = f
MAX
(Address and Data
Only),
f = 0 (OE, WE, BHE and BLE),
V
CC
=3.60V
LL
2
20
A
I
SB2
Automatic CE
Power-Down Current--
CMOS Inputs
CE
1
> V
CC
0.3V or CE
2
<
0.3V,
V
IN
> V
CC
0.3V or V
IN
<
0.3V,
f = 0, V
CC
= 3.60V
LL
2
20
A
Notes:
1.
V
IL(min.)
= 2.0V for pulse durations less than 20 ns.
2.
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25C.
WCMA4016U1X
3
.
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz,
V
CC
= V
CC(typ.)
6
pF
C
OUT
Output Capacitance
8
pF
Thermal Resistance
Description
Test Conditions
Symbol
BGA
Units
Thermal Resistance
(Junction to Ambient)
[3]
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board
JA
55
C/W
Thermal Resistance
(Junction to Case)
[3]
JC
16
C/W
AC Test Loads and Waveforms
V
CC
Typ
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
V
CC
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R1
R2
(a)
Rise TIme: 1 V/ns
Fall Time: 1 V/ns
(c)
Parameters
3.0V
Unit
R1
1103
R2
1554
R
TH
645
V
TH
1.75V
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.
[2]
Max.
Unit
V
DR
V
CC
for Data Retention
1.0
3.6
V
I
CCDR
Data Retention Current
V
CC
= 1.0V
CE
1
> V
CC
0.3V, CE
2
< 0.2V,
V
IN
> V
CC
0.3V or V
IN
< 0.3V
L
1
10
A
LL
t
CDR
[3]
Chip Deselect to Data
Retention Time
0
ns
t
R
[4]
Operation Recovery Time
70
ns
Note:
3.
Tested initially and after any design or process changes that may affect these parameters.
4.
Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 10
s or stable at V
CC(min.)
>10
s.
WCMA4016U1X
4
Data Retention Waveform
[5]
Switching Characteristics
Over the Operating Range
[6]
70 ns
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
70
ns
t
AA
Address to Data Valid
70
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid
70
ns
t
DOE
OE LOW to Data Valid
35
ns
t
LZOE
OE LOW to Low Z
[7, 9]
5
ns
t
HZOE
OE HIGH to High Z
[9]
25
ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low Z
[7]
10
ns
t
HZCE
CE
1
HIGH and CE
2
LOW to High Z
[7, 9]
25
ns
t
PU
CE
1
LOW and CE
2
HIGH to Power-Up
0
ns
t
PD
CE
1
HIGH and CE
2
LOW to Power-Down
70
ns
t
DBE
BHE / BLE LOW to Data Valid
70
ns
t
LZBE
[8]
BHE / BLE LOW to Low Z
5
ns
t
HZBE
BHE / BLE HIGH to High Z
25
ns
WRITE CYCLE
[10, 11]
t
WC
Write Cycle Time
70
ns
t
SCE
CE
1
LOW and CE
2
HIGH
to Write End
60
ns
t
AW
Address Set-Up to Write End
60
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Set-Up to Write Start
0
ns
t
PWE
WE Pulse Width
50
ns
Notes:
5.
BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
6.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
OL
/I
OH
and 30 pF load capacitance.
7.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8.
If both byte enables are toggled together this value is 10ns
9.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11.
The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
V
CC
, min.
V
CC
, min.
t
CDR
V
DR
> 1.0 V
DATA RETENTION MODE
t
R
CE1 or
V
CC
BHE.BLE
CE2
or
WCMA4016U1X
5
t
BW
BHE / BLE Pulse Width
60
ns
t
SD
Data Set-Up to Write End
30
ns
t
HD
Data Hold from Write End
0
ns
t
HZWE
WE LOW to High Z
[7, 9]
25
ns
t
LZWE
WE HIGH to Low Z
[7]
10
ns
Switching Waveforms
Notes:
12. The device is continuously selected. OE, CE
1
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE
1
, BHE, BLE transition LOW and CE
2
transition HIGH.
Switching Characteristics
Over the Operating Range
[6]
(continued)
70 ns
Parameter
Description
Min.
Max.
Unit
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
tAA
tOHA
Read Cycle 1 (Address Transition Controlled)
[12, 13]
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tPD
HIGH
OE
CE
1
I
CC
I
SB
IMPEDANCE
ADDRESS
CE2
VCC
SUPPLY
CURRENT
Read Cycle 2 (
OE
Controlled)
[13, 14]
tHZBE
BHE
/
BLE
tLZBE
tHZCE
DATA OUT
tDBE
WCMA4016U1X
6
Notes:
15. Data I/O is high impedance if OE = V
IH
.
16. If CE
1
goes HIGH and CE
2
goes LOW simultaneously with WE = V
IH
, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
VALID DATA
CE
1
ADDRESS
CE2
WE
DATA I/O
OE
Write Cycle 1 (WE Controlled)
BHE
/
BLE
tBW
[10, 15, 16, 17]
See Note 17
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
VALID DATA
CE1
ADDRESS
CE2
WE
DATA I/O
OE
See Note 17
Write Cycle 2 (CE
1
or CE
2
Controlled)
BHE/BLE
tBW
[10, 15, 16, 17]
tSA
WCMA4016U1X
7
Typical DC and AC Characteristics
Truth Table
CE
1
CE
2
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
X
High Z
Deselect/Power-Down
Standby (I
SB
)
X
L
X
X
X
X
High Z
Deselect/Power-Down
Standby (I
SB
)
X
X
X
X
H
H
High Z
Deselect/Power-Down
Standby (I
SB
)
L
H
H
L
L
L
Data Out (I/O0 I/O15)
Read
Active (I
CC
)
L
H
H
L
H
L
Data Out (I/O0 I/O7);
High Z (I/O8 I/O15)
Read
Active (I
CC
)
L
H
H
L
L
H
High Z (I/O0 I/O7);
Data Out (I/O8 I/O15)
Read
Active (I
CC
)
L
H
H
H
L
H
High Z
Output Disabled
Active (I
CC
)
L
H
H
H
H
L
High Z
Output Disabled
Active (I
CC
)
L
H
H
H
L
L
High Z
Output Disabled
Active (I
CC
)
L
H
L
X
L
L
Data In (I/O0 I/O15)
Write
Active (I
CC
)
L
H
L
X
H
L
Data In (I/O0 I/O7);
High Z (I/O8 I/O15)
Write
Active (I
CC
)
40
45
35
20
15
10
2.0
2.4
2.8
3.7
5
30
I
SB
(
A)
1.2
1.4
1.0
0.6
0.4
0.2
1.7
2.2
2.7
3.2
3.7
0.0
0.8
I
CC
70
80
60
40
30
20
2.0
2.4
2.8
3.7
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
10
50
T
AA
(
n
s
)
Normalized Operating Current
Standby Current vs. Supply Voltage
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
MoBL
MoBL
MoBL
vs. Supply Voltage
2.7
2.7
WCMA4016U1X
8
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
70
WCMA4016U1X-FF70
BA48
48-Ball Fine Pitch BGA
Industrial
Package Diagrams
48-Ball (7.00 mm x 8.5 mm x 1.2 mm) FBGA BA48B
51-85106-*D
WCMA4016U1X
9
Document History Page
Document Title: WCMA4016U1X 256K x 16 STATIC RAM
Document Number:
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
See ECN
AJU
New Data Sheet
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