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Электронный компонент: WCSN0436V1P-100AI

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128Kx36 Pipelined SRAM with NoBLTM Architecture
WCSN0436V1P
Document#: 38-05246
Revised Jan 06,2002
Y7C1350B
Features
Pin compatible and functionally equivalent to ZBTTM
devices IDT71V546, MT55L128L36P, and MCM63Z736
Supports 166-MHz bus operations with zero wait states
-- Data is transferred on every clock
Internally self-timed output buffer control to eliminate
the need to use OE
Fully registered (inputs and outputs) for pipelined
operation
Byte Write capability
128K x 36 common I/O architecture
Single 3.3V power supply
Fast clock-to-output times
-- 3.5 ns (for 166-MHz device)
-- 3.8 ns (for 150-MHz device)
-- 4.0 ns (for 143-MHz device)
-- 4.2 ns (for 133-MHz device)
-- 5.0 ns (for 100-MHz device)
-- 7.0 ns (for 80-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100 TQFP package
Burst Capability--linear or interleaved burst order
Low standby power (17.325 mW max.)
Functional Description
The WCSN0436V1P is a 3.3V, 128K by 36 synchronous-pipe-
lined Burst SRAM designed specifically to support unlimited
true back-to-back Read/Write operations without the insertion
of wait states. The WCSN0436V1P is equipped with the ad-
vanced No Bus LatencyTM (NoBLTM) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.The WCSN0436V1P is
pin/functionally compatible to ZBT SRAMsIDT71V546,
MT55L128L36P, and MCM63Z736.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS
[3:0]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
.
.
CLK
A
[16:0]
CEN
WE
BWS
[3:0]
CE1
CE
CE2
OE
OOUTP
U
T
128Kx36
MEMORY
ARRAY
CLK
Logic Block Diagram
DQ
[31:0]
Data-In REG.
Q
D
CE
CONTROL
and WRITE
LOGIC
3
RE
G
I
S
T
E
R
S
and LO
G
I
C
ADV/LD
36
36
36
17
17
36
DP
[3:0]
MODE
Selection Guide
-166
-150
-143
-133
-100
-80
Maximum Access Time (ns)
3.5
3.8
4.0
4.2
5.0
7.0
Maximum Operating Current (mA)
Commercial
400
375
350
300
250
200
Maximum CMOS Standby Current (mA)
Commercial
5
5
5
5
5
5
.
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 2 of 14
Pin Configuration
A
5
A
4
A
3
A
2
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
A
10
A
11
A
12
A
13
A
14
A
16
DP
1
DQ
15
DQ
14
V
DDQ
V
SS
DQ
13
DQ
12
DQ
11
DQ
10
V
SS
V
DDQ
DQ
9
DQ
8
V
SS
V
DD
V
DD
DQ
7
DQ
6
V
DDQ
V
SS
DQ
5
DQ
4
DQ
3
DQ
2
V
SS
V
DDQ
DQ
1
DQ
0
DP
0
DP
2
DQ
16
DQ
17
V
DDQ
V
SS
DQ
18
DQ
19
DQ
20
DQ
21
V
SS
V
DDQ
DQ
22
DQ
23
V
DDQ
V
DD
V
DD
V
SS
DQ
24
DQ
25
V
DDQ
V
SS
DQ
26
DQ
27
DQ
28
DQ
29
V
SS
V
DDQ
DQ
30
DQ
31
DP
3
A6
A7
CE
1
CE
2
BW
S
3
BW
S
2
BW
S
1
BW
S
0
CE
3
V
DD
V
SS
CLK
WE
CE
N
OE
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
15
AD
V/
LD
V
SS
MO
D
E
DNU
NC
NC
WCSN0436V1P
100-Pin TQFP
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 3 of 14
Pin Definitions
Pin Number
Name
I/O
Description
5044,
8182, 99,
100, 3237
A
[16:0]
Input-
Synchronous
Address Inputs used to select one of the 131,072 address locations. Sampled at
the rising edge of the CLK.
9693
BWS
[3:0]
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
0
controls DQ
[7:0]
and DP
0
, BWS
1
controls DQ
[15:8]
and DP
1
, BWS
2
controls DQ
[23:16]
and DP
2
, BWS
3
controls
DQ
[31:24]
and DP
3
. See Write Cycle Description table for details.
88
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
85
ADV/LD
Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
89
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
98
CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
, and CE
3
to select/deselect the device.
97
CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
92
CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and
CE
2
to select/deselect the device.
86
OE
Input-
Asynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the data portion of a write sequence, during
the first clock when emerging from a deselected state, when the device has been
deselected.
87
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
2928,
2522,
1918,
1312, 96,
32, 7978,
7572,
6968, 6362
5956, 5352
DQ
[31:0]
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A
[16:0]
during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ
[31:0]
are placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless
of the state of OE.
30, 1, 80 51
DP
[3:0]
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ
[31:0]
. During write sequences, DP
0
is controlled by BWS
0
, DP
1
is controlled by
BWS
1
, DP
2
is controlled by BWS
2
, and DP
3
is controlled by BWS
3
.
31
MODE
Input Strap pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the inter-
leaved burst order. Pulled LOW selects the linear burst order. MODE should not
change states during operation. When left floating MODE will default HIGH, to an
interleaved burst order.
15, 16, 41, 65,
66, 91
V
DD
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
4, 11, 14, 20,
27, 54, 61, 70,
77
V
DDQ
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 4 of 14
Introduction
Functional Overview
The WCSN0436V1P is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (t
CO
) is 3.5 ns (166-MHz de-
vice).
Accesses can be initiated by asserting all three Chip Enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The ac-
cess can either be a read or write operation, depending on the
status of the Write Enable (WE). BWS
[3:0]
can be used to con-
duct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs (A
0
-
A
16
)
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the input of the output register. At the
rising edge of the next clock the requested data is allowed to
propagate through the output register and onto the data bus
within 3.5 ns (166-MHz device) provided OE is active LOW.
After the first clock of the read access the output buffers are
controlled by OE and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. During the second clock, a subsequent operation
(Read/Write/Deselect) can be initiated. Deselecting the device
is also pipelined. Therefore, when the SRAM is deselected at
clock rise by one of the chip enable signals, its output will
three-state following the next clock rise.
Burst Read Accesses
The WCSN036V1p has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A
0
-
A
16
is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ
[31:0]
and
DP
[3:0]
. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ
[31:0]
and
DP
[3:0]
(or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete.
The data written during the Write operation is controlled by
BWS
[3:0]
signals. The WCSN0436V1P provides byte write ca-
pability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BWS
[3:0]
) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.
Because the WCSN0436V1P is a common I/O device, data
should not be driven into the device while the outputs are ac-
tive. The Output Enable (OE) can be deasserted HIGH before
presenting data to the DQ
[31:0]
and DP
[3:0]
inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ
[31:0]
5, 10, 17, 21,
26, 40, 55, 60,
64, 67, 71, 76,
90
V
SS
Ground
Ground for the device. Should be connected to ground of the system.
83, 84
NC
-
No connects. Reserved for address inputs for depth expansion. Pin 83 and 84 will
be used for 256K and 512K depths respectively.
38, 39, 42, 43 DNU
-
Do Not Use pins. These pins should be left floating or tied to V
SS
.
Pin Definitions
(continued)
Pin Number
Name
I/O
Description
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 5 of 14
and DP
[3:0]
are automatically three-stated during the data por-
tion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The WCSN0436V1p has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four WRITE operations without reasserting the address in-
puts. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE
1
, CE
2
, and CE
3
) and WE inputs are
ignored and the burst counter is incremented. The correct
BWS
[3:0]
inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Cycle Description Truth Table
[
1, 2, 3, 4, 5, 6
]
Operation
Address
Used
CE
CEN
ADV/
LD/
WE
BWS
x
CLK
Comments
Deselected
External
1
0
L
X
X
L-H
I/Os three-state following next rec-
ognized clock.
Suspend
-
X
1
X
X
X
L-H
Clock ignored, all operations sus-
pended.
Begin Read
External
0
0
0
1
X
L-H
Address latched.
Begin Write
External
0
0
0
0
Valid
L-H
Address latched, data presented
two valid clocks later.
Burst Read
Operation
Internal
X
0
1
X
X
L-H
Burst Read operation. Previous ac-
cess was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE.
Burst Write
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous ac-
cess was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE. Bytes written are deter-
mined by BWS
[3:0]
.
Notes:
1.
X="Don't Care", 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx =
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2.
Write is defined by WE and BWS[3:0]. See Write Cycle Description table for details.
3.
The DQ and DP pins are controlled by the current cycle and the OE signal.
4.
CEN=1 inserts wait states.
5.
Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6.
OE assumed LOW.
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 6 of 14
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................
-
65C to +150C
Ambient Temperature with
Power Applied
.................................................. -
55C to +125C
Supply Voltage on V
DD
Relative to GND
.........-
0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[9]
.....................................-
0.5V to V
DDQ
+ 0.5V
DC Input Voltage
[9]
..................................-
0.5V to V
DDQ
+ 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Notes:
7.
X="Don't Care", 1=Logic HIGH, 0=Logic LOW.
8.
Write is initiated by the combination of WE and BWS
x
. Bytes written are determined by BWS
[3:0]
. Bytes not selected during byte writes remain unaltered. All
I/Os are three-stated during byte writes.
9.
Minimum voltage equals 2.0V for pulse duration less than 20 ns.
10. T
A
is the case temperature.
Write Cycle Description
[7, 8]
Function
WE
BWS
3
BWS
2
BWS
1
BWS
0
Read
1
X
X
X
X
Write
-
No bytes written
0
1
1
1
1
Write Byte 0
-
(DQ
[7:0]
and
DP
0
)
0
1
1
1
0
Write Byte 1
-
(DQ
[15:8]
and
DP
1
)
0
1
1
0
1
Write Bytes 1, 0
0
1
1
0
0
Write Byte 2
-
(DQ
[23:16]
and
DP
2
)
0
1
0
1
1
Write Bytes 2, 0
0
1
0
1
0
Write Bytes 2, 1
0
1
0
0
1
Write Bytes 2, 1, 0
0
1
0
0
0
Write Byte 3
-
(DQ
[31:24]
and
DP
3
)
0
0
1
1
1
Write Bytes 3, 0
0
0
1
1
0
Write Bytes 3, 1
0
0
1
0
1
Write Bytes 3, 1, 0
0
0
1
0
0
Write Bytes 3, 2
0
0
0
1
1
Write Bytes 3, 2, 0
0
0
0
1
0
Write Bytes 3, 2, 1
0
0
0
0
1
Write All Bytes
0
0
0
0
0
Operating Range
Range
Ambient
Temperature
[10]
V
DD
/V
DDQ
Com'l
0C to +70C
3.3V 5%
Ind'l
40C to +85C
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 7 of 14
Electrical Characteristics
Over the Operating Range
Parame-
ter
Description
Test Conditions
Min.
Max.
Unit
V
DD
Power Supply Voltage
3.135
3.465
V
V
DDQ
I/O Supply Voltage
3.135
3.465
V
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
=
4.0 mA
[11]
2.4
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 8.0 mA
[11]
0.4
V
V
IH
Input HIGH Voltage
2.0
V
DD
+
0.3V
V
V
IL
Input LOW Voltage
[9]
-
0.3
0.8
V
I
X
Input Load Current
GND
V
I
V
DDQ
-
5
5
A
Input Current of
MODE
-
30
30
A
I
OZ
Output Leakage
Current
GND
V
I
V
DDQ,
Output Disabled
-
5
5
A
I
CC
V
DD
Operating
Supply
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
5.0-ns cycle, 166 MHz
400
mA
6.6-ns cycle, 150 MHz
375
mA
7.0-ns cycle, 143 MHz
350
mA
7.5-ns cycle, 133 MHz
300
mA
10.0-ns cycle, 100 MHz
250
mA
12.5-ns cycle, 80 MHz
200
mA
I
SB1
Automatic CE
Power-Down
Current--TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
f = f
MAX
= 1/t
CYC
5.0-ns cycle, 166 MHz
80
mA
6.6-ns cycle, 150 MHz
70
mA
7.0-ns cycle, 143 MHz
60
mA
7.5-ns cycle, 133 MHz
50
mA
10.0-ns cycle, 100 MHz
40
mA
12.5-ns cycle, 80 MHz
35
mA
I
SB2
Automatic CE
Power-Down
Current--CMOS
Inputs
Max. V
DD
, Device Deselected,
V
IN
0.3V or V
IN
>
V
DDQ
0.3V, f = 0
All speed grades
5
mA
I
SB3
Automatic CE
Power-Down
Current--CMOS
Inputs
Max. V
DD
, Device Deselected, or
V
IN
0.3V or V
IN
> V
DDQ
0.3V
f = f
MAX
= 1/t
CYC
5.0-ns cycle, 166 MHz
70
mA
6.6-ns cycle, 150 MHz
60
mA
7.0-ns cycle, 143 MHz
50
mA
7.5-ns cycle, 133 MHz
40
mA
10.0-ns cycle, 100 MHz
30
mA
12.5-ns cycle, 80 MHz
25
mA
Note:
11. The load used for V
OH
and V
OL
testing is shown in Figure (b) of the AC Test Loads.
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 8 of 14
Capacitance
[12]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz,
V
DD
= 3.3V,
V
DDQ
= 3.3V
4
pF
C
CLK
Clock Input Capacitance
4
pF
C
I/O
Input/Output Capacitance
4
pF
AC Test Loads and Waveforms
Thermal Resistance
Description
Test Conditions
Symbol
TQFP Typ.
Units
Notes
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board
JA
28
C/W
12
Thermal Resistance
(Junction to Case)
JC
4
C/W
12
Notes:
12. Tested initially and after any design or process change that may affect these parameters.
13. A/C test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in
part (a) of AC Test Loads.
3.0V
GND
OUTPUT
R=317
R=351
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
ALL INPUT PULSES
1350B-2
OUTPUT
R
L
=50
Z
0
=50
V
L
= 1.5V
3.3V
[13]
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 9 of 14
Switching Characteristics
Over the Operating Range
[13, 14, 15]
-166
-150
-143
-133
-100
-80
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
CYC
Clock Cycle Time
5.0
6.6
7.0
7.5
10
12.5
ns
t
CH
Clock HIGH
1.4
2.5
2.8
3.0
4.0
4.0
ns
t
CL
Clock LOW
1.4
2.5
2.8
3.0
4.0
4.0
ns
t
AS
Address Set-Up Before CLK
Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
t
AH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
t
CO
Data Output Valid After CLK
Rise
3.5
3.8
4.0
4.2
5.0
7.0
ns
t
DOH
Data Output Hold After CLK
Rise
1.5
1.5
1.5
1.5
1.5
ns
t
CENS
CEN Set-Up Before CLK Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
t
CENH
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
t
WES
GW, BWS
[3:0]
Set-Up Before
CLK Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
t
WEH
GW, BWS
[3:0]
Hold After CLK
Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
t
ALS
ADV/LD Set-Up Before CLK
Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
t
ALH
ADV/LD Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
t
DS
Data Input Set-Up Before CLK
Rise
1.5
1.5
1.7
1.7
2.0
2.5
ns
t
DH
Data Input Hold After CLK Rise 0.5
0.5
0.5
0.5
0.5
1.0
ns
t
CES
Chip Enable Set-Up Before
CLK Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
t
CEH
Chip Enable Hold After CLK
Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
t
CHZ
Clock to High-Z
[12, 14, 15, 16]
1.5
3.2
1.5
3.2
1.5
3.5
1.5
3.5
1.5
3.5
1.5
5.0
ns
t
CLZ
Clock to Low-Z
[12, 14, 15, 16]
1.5
1.5
1.5
1.5
1.5
1.5
ns
t
EOHZ
OE HIGH to Output High-Z
[12,
14, 15, 16]
3.0
3.0
4.0
4.2
5.0
7.0
ns
t
EOLZ
OE LOW to Output Low-Z
[12,
14, 15, 16]
0.0
0
0
0
0
0
ns
t
EOV
OE LOW to Output Valid
[14]
3.2
3.5
4.0
4.2
5.0
7.0
ns
Notes:
14. t
CHZ
, t
CLZ
, t
OEV
, t
EOLZ
, and t
EOHZ
are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured
200 mV from steady-state
voltage.
15. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 10 of 14
Switching Waveforms
CEN
CLK
ADDRESS
CE
WE &
Data-
In/Out
t
CYC
t
CH
t
CL
RA1
t
AH
t
AS
t
WS
t
WH
t
CES
t
CEH
t
CO
Q4
Q1
= DON'T CARE
= UNDEFINED
The combination of WE & BWS
[3:0]
define a write cycle (see Write Cycle Description table).
Out
D2
In
D5
In
Out
READ
WRI
T
E
DES
E
L
E
CT
WRI
T
E
REA
D
READ
READ
S
U
SPEND
READ
DESEL
ECT
DESEL
ECT
WA2
RA3
RA4
WA5
RA6
RA7
t
CLZ
t
DOH
Q3
Out
t
CHZ
CE is the combination of CE
1
, CE
2
, and CE
3
. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for
Device
originally
deselected
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW.
Q7
Out
t
CHZ
t
CENS
t
CENH
t
DOH
BWS
[3:0]
READ/WRITE/DESELECT Sequence
CEN HIGH blocks
Q6
Out
all synchronous inputs
t
DS
t
DH
OE held LOW.
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 11 of 14
Switching Waveforms
(continued)
ADV/LD
CLK
ADDRESS
CE
Data-
In/Out
t
CYC
t
CH
t
CL
t
ALS
t
ALH
RA1
t
AH
t
AS
t
CES
t
CEH
t
CO
Q1
= DON'T CARE
= UNDEFINED
The combination of WE & BWS
[3:0]
define a write cycle (see Write Cycle Description table).
Out
B
e
g
i
n R
e
ad
B
u
rst R
ead
t
CLZ
t
DOH
CE is the combination of CE
1
, CE
2,
and CE
3
. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Device
originally
deselected
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
WA2
Q1+1
Out
Q1+2
Out
Q1+3
Out
RA3
t
CLZ
t
CHZ
D2+1
In
D2+2
In
D2+3
In
D2
In
t
CO
Q3
Out
t
DS
t
DH
Bu
r
s
t
Re
a
d
Bu
r
s
t
Re
a
d
B
e
gi
n W
r
i
t
e
Bu
r
s
t
Wr
it
e
Bu
r
s
t
Wr
it
e
Bu
r
s
t
Wr
it
e
B
e
g
i
n R
e
ad
Bu
r
s
t
Re
a
d
Bu
r
s
t
Re
a
d
Burst Sequences
BWS
[3:0]
t
WS
t
WH
WE
t
WS
t
WH
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS
[3:0]
input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 12 of 14
Switching Waveforms
(continued)
OE
Three-state
I/O's
OE Timing
t
EOHZ
t
EOV
t
EOLZ
Ordering Information
Speed
(MHz)
Ordering Code
Package
Name
Package Type
Operating
Range
166
WCSN0436V1P-166AC
A101
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
150
WCSN0436V1P-150AC
A101
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
143
WCSN0436V1P-143AC
A101
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
133
WCSN0436V1P-133AC
A101
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
WCSN0436V1P-133AI
A101
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Industrial
100
WCSN0436V1P-100AC
A101
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
WCSN0436V1P-100AI
A101
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Industrial
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 13 of 14
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
WCSN0436V1P
Document #: 38-05246 Rev. **
Page 14 of 14
Document Title: WCSN0436V1P 128K x 36 Pipelined SRAM with NoBLTM Architecture
Document Number: 38-05246
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
109953
01/07/02
SZV
Change from Spec number: 38-00910 to 38-05045
New
113259
02/03/02
GLC
Change from Spec number: 38-05045 to 38-05246