64K x 32 Synchronous-Pipelined Cache RAM

Revised: February 7, 2002

WCSS0232V1P

February 7, 2002

WCSS0232V1P

Features

· Supports 133-MHz bus for Pentium® and PowerPCTM

operations with zero wait states

· Fully registered inputs and outputs for pipelined

operation

· 64K x 32 common I/O architecture
· Single 3.3V power supply
· Fast clock-to-output times

-- 4.2 ns (for 133-MHz device)
-- 5.5 ns (for 100-MHz device)
-- 7.0 ns (for 75-MHz device

· User-selectable burst counter supporting Intel®

Pentium interleaved or linear burst sequences

· Separate processor and controller address strobes
· Synchronous self-timed writes
· Asynchronous output enable
· JEDEC-standard 100 TQFP pinout
· "ZZ" Sleep Mode option and Stop Clock option

Functional Description

The WCSS0232V1P is a 3.3V, 64K by 32 synchronous-pipe-

lined cache SRAM designed to support zero wait state sec-
ondary cache with minimal glue logic.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise is 4.2 ns (133-MHz

device).
The WCSS0232V1P supports either the interleaved burst se-

quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The

burst sequence is selected through the MODE pin. Accesses

can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at

clock rise. Address advancement through the burst sequence

is controlled by the ADV input. A 2-bit on-chip wraparound
burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.
Byte write operations are qualified with the four Byte Write

Select (BW

[3:0]

) inputs. A Global Write Enable (GW) overrides

all byte write inputs and writes data to all four bytes. All writes

are conducted with on-chip synchronous self-timed write cir-

cuitry.
Three synchronous Chip Selects (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-

er data during depth expansion, OE is masked during the first

clock of a read cycle when emerging from a deselected state.

Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.

CLK

ADV

ADSC

[15:0]

BWE

BURST

COUNTER

DQ[31:24]

BYTEWRITE

REGISTERS

ADDRESS

OUTPUT

REGISTERS

INPUT

REGISTERS

64KX32

MEMORY

ARRAY

CLK

CLR

SLEEP

CONTROL

DQ[23:16]

BYTEWRITE

REGISTERS

DQ[15:8]

BYTEWRITE

REGISTERS

DQ[7:0]

BYTEWRITE

REGISTERS

ENABLE

CLK

ENABLE DELAY

CLK

[1:0]

)

MODE

ADSP

Logic Block Diagram

[31:0]

WCSS0232V1P

Pin Configuration

NC
DQ

DDQ

SSQ

DDQ

NC
V

ZZ
DQ

DDQ

SSQ

DDQ

SSQ

DDQ

SSQ

DDQ

CLK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

BYTE0

BYTE1

BYTE3

BYTE2

100-Pin TQFP

WCSS0232V1P

Selection Guide

-133

-100

-75

Maximum Access Time (ns)

4.2

5.5

7.0

Maximum Operating Current (mA)

Commercial

325

310

260

Maximum CMOS Standby Current (mA)

Commercial

WCSS0232V1P

Pin Definitions

Pin Number

Name

I/O

Description

4944, 81,82,

99, 100,
3237

[15:0]

Input-

Synchronous

Address Inputs used to select one of the 64K address locations. Sampled at the

rising edge of the CLK if ADSP or ADSC is active LOW, and CE

, and

are sampled active. A

[1:0]

feed the 2-bit counter.

9693

[3:0]

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes

to the SRAM. Sampled on the rising edge of CLK.

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of

CLK, a global write is conducted (ALL bytes are written, regardless of the values

on BW

[3:0]

and BWE).

BWE

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This

signal must be asserted LOW to conduct a byte write.

CLK

Input-Clock

Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

and CE

to select/deselect the device. ADSP is ignored if

is HIGH.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

and

to select/deselect the device.

Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O

pins are three-stated, and act as input data pins. OE is masked during the first

clock of a read cycle when emerging from a deselected state.

ADV

Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK. When asserted, it auto-

matically increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK. When assert-
ed LOW, A

[15:0]

is captured in the address registers. A

[1:0]

are also loaded into the

burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

ASDP is ignored when CE

is deasserted HIGH.

ADSC

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK. When assert-

ed LOW, A

[15:0]

is captured in the address registers. A

[1:0]

are also loaded into the

burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

Input-

Asynchronous

ZZ "sleep" Input. This active HIGH input places the device in a non-time critical

"sleep" condition with data integrity preserved.

29, 28,
2522, 19,

18,13,12,

96, 3, 2, 79,
78, 7572,

69, 68, 63, 62

5956, 53, 52

[31:0]

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained

in the memory location specified by A

[15:0]

during the previous clock rise of the

read cycle. The direction of the pins is controlled by OE. When OE is asserted
LOW, the pins behave as outputs. When HIGH, DQ

[31:0]

are placed in a three-state

condition.

15, 41, 65, 91 V

Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power

supply.

17, 40, 67, 90 V

Ground

Ground for the core of the device. Should be connected to ground of the system.

4, 11, 20, 27,

54, 61, 70, 77

DDQ

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.

5, 10, 21, 26,
55, 60, 71, 76

SSQ

I/O Ground

Ground for the I/O circuitry. Should be connected to ground of the system.

MODE

Input-

Static

Selects burst order. When tied to GND selects linear burst sequence. When tied

to V

DDQ

or left floating selects interleaved burst sequence. This is a strap pin and

should remain static during device operation.

1, 14, 16, 30,

38, 39, 42, 43,
50, 51, 66, 80

No Connects.

WCSS0232V1P

Introduction

Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise (t

) is 4.2 ns (133-MHz

device).
The WCSS0232V1P supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The in-

terleaved burst order supports Pentium and i486 processors.

The linear burst sequence is suited for processors that utilize
a linear burst sequence. The burst order is user selectable,

and is determined by sampling the MODE input. Accesses can

be initiated with either the Processor Address Strobe (ADSP)
or the Controller Address Strobe (ADSC). Address advance-

ment through the burst sequence is controlled by the ADV in-

put. A two-bit on-chip wraparound burst counter captures the
first address in a burst sequence and automatically increments

the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW

[3:0]

) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-

nous self-timed write circuitry.
Three synchronous Chip Selects (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. ADSP is ignored if CE

is HIGH.

Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

, CE

are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE

is HIGH. The address presented to the address inputs (A

[15:0]

)

is stored into the address advancement logic and the Address

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto
the data bus within 4.2 ns (133-MHz device) if OE is active

LOW. The only exception occurs when the SRAM is emerging

from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After

the first cycle of the access, the outputs are controlled by the

OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select

and either ADSP or ADSC signals, its output will three-state

immediately.

Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE

, CE

are all asserted active. The address presented

to A

[15:0]

is loaded into the address register and the address

advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW

) and ADV inputs are

ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQ

[31:0]

inputs is written into the corre-

sponding address location in the RAM core. If GW is HIGH,

then the write operation is controlled by BWE and BW

[3:0]

sig-

nals. The WCSS0232V1P provides byte write capability that is

described in the Write Cycle Description table. Asserting the

Byte Write Enable input (BWE) with the selected Byte Write
(BW

[3:0]

) input will selectively write to only the desired bytes.

Bytes not selected during a byte write operation will remain

unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the WCSS0232V1P is a common I/O device, the
Output Enable (OE) must be deasserted HIGH before present-

ing data to the DQ

[31:0]

inputs. Doing so will three-state the

output drivers. As a safety precaution, DQ

[31:0]

are automati-

cally three-stated whenever a write cycle is detected, regard-

less of the state of OE.

Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) CE

, CE

are all asserted active,

and (4) the appropriate combination of the write inputs (GW,

BWE, and BW

[3:0]

) are asserted active to conduct a write to

the desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented to

[15:0]

is loaded into the address register and the address ad-

vancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is con-

ducted, the data presented to the DQ

[31:0]

is written into the

corresponding address location in the RAM core. If a byte write
is conducted, only the selected bytes are written. Bytes not

selected during a byte write operation will remain unaltered. A

Synchronous self-timed write mechanism has been provided
to simplify the write operations.
Because the WCSS0232V1P is a common I/O device, the
Output Enable (OE) must be deasserted HIGH before present-

ing data to the DQ

[31:0]

inputs. Doing so will three-state the

output drivers. As a safety precaution, DQ

[31:0]

are automati-

cally three-stated whenever a write cycle is detected, regard-

less of the state of OE.

Burst Sequences

The WCSS0232V1P provides a two-bit wraparound counter,

fed by A

[1:0]

, that implements either an interleaved or linear

burst sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear

burst sequence is designed to support processors that follow

a linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

Interleaved Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

[1:0]

WCSS0232V1P

Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-

es the SRAM in a power conservation "sleep" mode. Two clock

cycles are required to enter into or exit from this "sleep" mode.
While in this mode, data integrity is guaranteed. Accesses

pending when entering the "sleep" mode are not considered

valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the "sleep" mode.

, CE

ADSP, and ADSC must remain inactive for the

duration of t

ZZREC

after the ZZ input returns LOW.

Linear Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

[1:0]

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

DDZZ

Snooze mode

standby current

ZZ > V

0.2V

ZZS

Device operation to

ZZ > V

0.2V

CYC

ZZREC

ZZ recovery time

ZZ < 0.2V

CYC

Cycle Descriptions

[1,2,3]

Next Cycle

Add. Used

ADSP

ADSC

ADV

Write

Unselected

None

Hi-Z

Unselected

None

Hi-Z

Unselected

None

Hi-Z

Unselected

None

Hi-Z

Unselected

None

Hi-Z

Begin Read

External

Hi-Z

Begin Read

External

Hi-Z

read

Continue Read

Hi-Z

read

Continue Read

read

Continue Read

Hi-Z

read

Continue Read

read

Suspend Read

Current

Hi-Z

read

Suspend Read

Current

read

Suspend Read

Current

Hi-Z

read

Suspend Read

Current

read

Begin Write

Current

Hi-Z

write

Begin Write

Current

Hi-Z

write

Begin Write

External

Hi-Z

write

Continue Write

Hi-Z

write

Continue Write

Hi-Z

write

Suspend Write

Current

Hi-Z

write

Suspend Write

Current

Hi-Z

write

ZZ "sleep"

None

Hi-Z

Notes:

X="Don't Care", 1=HIGH, 0=LOW.

Write is defined by BWE, BW

[3:0]

, and GW. See Write Cycle Descriptions table.

The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

WCSS0232V1P

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)
Storage Temperature

..................................... -

65°C to +150°C

Ambient Temperature with

Power Applied

.................................................. -

55°C to +125°C

Supply Voltage on V

Relative to GND

.........-

0.5V to +4.6V

DC Voltage Applied to Outputs
in High Z State

[7]

.....................................-

0.5V to V

DDQ

+ 0.5V

DC Input Voltage

[7]

..................................-

0.5V to V

DDQ

+ 0.5V

Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage .......................................... >2001V

(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA

Notes:

X="Don't Care", 1=Logic HIGH, 0=Logic LOW.

The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW

[3:0]

Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is

a "don't care" for the remainder of the write cycle.

OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ=High-Z when OE is inactive or

when the device is deselected, and DQ=data when OE is active.

Minimum voltage equals 2.0V for pulse durations of less than 20 ns.

is the case temperature.

Write Cycle Descriptions

[4,5,6]

Function

BWE

Read

Write Byte 0 - DQ

[7:0]

Write Byte 1 - DQ

[15:8]

Write Bytes 1, 0

Write Byte 2 - DQ

[23:16]

Write Bytes 2, 0

Write Bytes 2, 1

Write Bytes 2, 1, 0

Write Byte 3 - DQ

[31:24]

Write Bytes 3, 0

Write Bytes 3, 1

Write Bytes 3, 1, 0

Write Bytes 3, 2

Write Bytes 3, 2, 0

Write Bytes 3, 2, 1

Write All Bytes

Operating Range

Range

Ambient

Temperature

[8]

DDQ

Com'l

0°C to +70°C

3.3V

5%/+10%

3.3V

5%/+10%

WCSS0232V1P

Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

Min.

Max.

Unit

Power Supply Voltage

3.3V

5%/+10%

3.135

3.6

DDQ

I/O Supply Voltage

3.3V

5%/+10%

3.135

3.6

Output HIGH Voltage

= Min., I

4.0 mA

2.4

Output LOW Voltage

= Min., I

= 8.0 mA

0.4

Input HIGH Voltage

2.0

DDQ

0.3V

Input LOW Voltage

[7]

0.3

0.8

Input Load Current

except ZZ and MODE

GND

DDQ

Input Current of MODE Input = V

Input = V

DDQ

Input Current of ZZ

Input = V

DDQ

Output Leakage
Current

GND

DDQ,

Output Disabled

Operating Supply

Current

= Max., I

OUT

= 0 mA,

f = f

MAX

= 1/t

CYC

7.5-ns cycle, 133 MHz

325

10-ns cycle, 100 MHz

260

13.3-ns cycle, 75 MHz

260

SB1

Automatic CS

Power-Down

Current--TTL Inputs

Max. V

, Device Deselected,

or V

f = f

MAX

= 1/t

CYC

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

13.3-ns cycle, 75 MHz

SB2

Automatic CS

Power-Down

Current--CMOS Inputs

Max. V

, Device Deselected,

0.3V or V

> V

DDQ

0.3V,

f = 0

All speeds

SB3

Automatic CS
Power-Down

Current--CMOS Inputs

Max. V

, Device Deselected, or

0.3V or V

> V

DDQ

0.3V

f = f

MAX

= 1/t

CYC

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

13.3-ns cycle, 75 MHz

SB4

Automatic CS
Power-Down

Current--TTL Inputs

Max. V

, Device Deselected,

or V

, f = 0

Capacitance

[9]

Parameter

Description

Test Conditions

Max.

Unit

Input Capacitance

= 25

C, f = 1 MHz,

= 3.3V,

DDQ

= 3.3V

CLK

Clock Input Capacitance

I/O

Input/Output Capacitance

Note:

Tested initially and after any design or process changes that may affect these parameters.

WCSS0232V1P

AC Test Loads and Waveforms

Switching Characteristics

Over the Operating Range

[11,12,13]

-133

-100

-75

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

CYC

Clock Cycle Time

7.5

13.3

Clock HIGH

1.9

3.2

5.0

Clock LOW

1.9

3.2

5.0

Address Set-Up Before CLK Rise

2.5

Address Hold After CLK Rise

0.5

Data Output Valid After CLK Rise

4.2

5.0

7.0

DOH

Data Output Hold After CLK Rise

1.5

2.0

ADS

ADSP, ADSC Set-Up Before CLK Rise

2.5

ADH

ADSP, ADSC Hold After CLK Rise

0.5

WES

BWE, GW, BW[3:0] Set-Up Before CLK Rise

2.5

WEH

BWE, GW, BW[3:0] Hold After CLK Rise

0.5

ADVS

ADV Set-Up Before CLK Rise

2.5

ADVH

ADV Hold After CLK Rise

0.5

Data Input Set-Up Before CLK Rise

2.5

Data Input Hold After CLK Rise

0.5

CES

Chip Select Set-Up

2.5

CEH

Chip Select Hold After CLK Rise

0.5

CHZ

Clock to High-Z

[12]

1.5

3.5

1.5

CLZ

Clock to Low-Z

[12]

EOHZ

OE HIGH to Output High-Z

[12, 13]

3.5

5.5

EOLZ

OE LOW to Output Low-Z

[12, 13]

EOV

OE LOW to Output Valid

[12]

4.2

5.0

Notes:

10. Input waveform should have a slew rate of 1V/ns.

11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output

loading of the specified I

and load capacitance. Shown in (a) and (b) of AC Test Loads.

12. t

CHZ

, t

CLZ

, t

EOV

, t

EOLZ

, and t

EOHZ

are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured

200 mV from

steady-state voltage.

13. At any given voltage and temperature, t

EOHZ

is less than t

EOLZ

and t

CHZ

is less than t

CLZ

OUTPUT

R=317

R=351

5 pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

=50

= 1.5V

3.3V

ALL INPUT PULSES

[10]

3.3V

GND

90%

10%

90%

10%

< 3.3 ns

(c)

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