256K x 18 Synchronous

3.3V Cache RAM

WCSS0418V1F

Document #: 38-05245 Rev. **

Revised Jan 05,2002

Y7C1032

Features

· Supports 117-MHz microprocessor cache systems with

zero wait states

· 256K by 18 common I/O
· Fast clock-to-output times

-- 7.5 ns (117-MHz version)

· Two-bit wrap-around counter supporting either inter-

leaved or linear burst sequence

· Separate processor and controller address strobes

provide direct interface with the processor and external

cache controller

· Synchronous self-timed write
· Asynchronous output enable
· I/Os capable of 2.53.3V operation
· JEDEC-standard pinout
· 100-pin TQFP packaging
· ZZ "sleep" mode

Functional Description

The WCSS0418V1F is a 3.3V, 256K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors

with minimum glue logic. Maximum access delay from clock

rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address

automatically for the rest of the burst access.
The allows WCSS0418V1F both interleaved or linear burst se-

quences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor

Address Strobe (ADSP) or the Cache Controller Address

Strobe (ADSC) inputs. Address advancement is controlled by
the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and

an asynchronous output enable input provide easy control for

bank selection and output three-state control.

CLK

ADV

ADSC

[17:0]

BWE

BURST

COUNTER

ADDRESS

INPUT

REGISTERS

256K X 18

MEMORY

ARRAY

CLK

CLR

SLEEP

CONTROL

DQ[15:8]

BYTEWRITE

REGISTERS

DQ[7:0]

BYTEWRITE

REGISTERS

ENABLE

CLK

) 2

MODE

ADSP

Logic Block Diagram

[15:0]

[1:0]

Selection Guide

WCSS0418V1F-117

WCSS0418V1F-100

Maximum Access Time (ns)

7.5

8.0

Maximum Operating Current (mA)

350

325

Maximum Standby Current (mA)

10.0

Intel and Pentium are registered trademarks of Intel Corporation.

WCSS0418V1F

Document #: 38-05245 Rev. **

Page 3 of 18

Pin Configurations

(continued)

A
B
C
D
E

G
H

P
R
T
U

DDQ

NC
NC

ADSP

DDQ

NC
NC
NC

DDQ

CLK

NC
NC

DDQ

ADSC

ADV

MODE

DQP

BWE

119-Ball BGA

Pin Descriptions

Name

I/O

Description

ADSC

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A

[17:0]

is captured in the address registers. A

[1:0]

are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized.

ADSP

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A

[17:0]

is captured in the address registers. A

[1:0]

are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE

is deasserted HIGH.

[1:0]

Input-

Synchronous

, A

address inputs, These inputs feed the on-chip burst counter as the LSBs as well as being

used to access a particular memory location in the memory array.

[17:2]

Input-

Synchronous

Address Inputs used in conjunction with A

[1:0]

to select one of the 256K address locations. Sampled

at the rising edge of the CLK, if CE

and CE

are sampled active, and ADSP or ADSC is

active LOW.

BWS

[1:0]

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the

rising edge. BWS

controls DQ

[7:0]

and DP

, BWS

controls DQ

[15:8]

and DP

. See Write Cycle

Descriptions table for further details.

ADV

Input-

Synchronous

Advance input used to advance the on-chip address counter. When LOW the internal burst counter

is advanced in a burst sequence. The burst sequence is selected using the MODE input.

BWE

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be

asserted LOW to conduct a byte write.

Input-

Synchronous

Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct
a global write, independent of the state of BWE and BWS

[1:0]

. Global writes override byte writes.

CLK

Input-Clock

Clock input. Used to capture all synchronous inputs to the device.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE

to select/deselect the device. CE

gates ADSP.

WCSS0418V1F

Document #: 38-05245 Rev. **

Page 4 of 18

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. Maximum access delay from

the clock rise (t

CDV

) is 7.5 ns (117-MHz device).

The WCSS0418V1F supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The in-
terleaved burst order supports Pentium and i486 processors.

The linear burst sequence is suited for processors that utilize

a linear burst sequence. The burst order is user selectable,
and is determined by sampling the MODE input. Accesses can

be initiated with either the Processor Address Strobe (ADSP)

or the Controller Address Strobe (ADSC). Address advance-
ment through the burst sequence is controlled by the ADV in-

put. A two-bit on-chip wraparound burst counter captures the

first address in a burst sequence and automatically increments
the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW

[3:0]

) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
Three synchronous Chip Selects (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. ADSP is ignored if CE

is HIGH.

Single Read Accesses
A single read access is initiated when the following conditions

are satisfied at clock rise: (1) CE

, CE

, and CE

are all as-

serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deassert-

ed during this first cycle). The address presented to the ad-

dress inputs is latched into the address register and the burst
counter/control logic and presented to the memory core. If the

OE input is asserted LOW, the requested data will be available

at the data outputs a maximum to t

CDV

after clock rise. ADSP

is ignored if CE

is HIGH.

Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are sat-

isfied at clock rise: (1) CE

, CE

, and CE

are all asserted

active, and (2) ADSP is asserted LOW. The addresses pre-

sented are loaded into the address register and the burst

counter/control logic and delivered to the RAM core. The write
inputs (GW, BWE, and BWS

[1:0]

) are ignored during this first

clock cycle. If the write inputs are asserted active (see Write

Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be

latched and written into the device. Byte writes are allowed.

During byte writes, BWS

controls DQ

[7:0]

and DP

while

BWS

controls DQ

[15:8]

and DP

. All I/Os are three-stated dur-

ing a byte write. Since these are common I/O devices, the

asynchronous OE input signal must be deasserted and the

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE

to select/deselect the device.

Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,

the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins.

Input-

Asynchronous

Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power standby

mode in which all other inputs are ignored, but the data in the memory array is maintained. Leaving

ZZ floating or NC will default the device into an active state. ZZ pin has an internal pull-down.

MODE

Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. When left floating or NC, defaults to interleaved burst

order. Mode pin has an internal pull-up.

[15:0]

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A

[17:0]

during the previous clock rise of the read cycle. The direction of the pins is controlled by

OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as

outputs. When HIGH, DQ

[15:0]

and DP

[1:0]

are placed in a three-state condition. The outputs are

automatically three-stated when a WRITE cycle is detected.

[1:0]

I/O-

Synchronous

Bidirectional Data Parity lines. These behave identical to DQ

[15:0]

described above. These signals

can be used as parity bits for bytes 0 and 1 respectively.

Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply.

Ground

Ground for the device. Should be connected to ground of the system.

DDQ

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 2.5 or 3.3V power supply.

No connects.

DNU

Do not use pins. Should be left unconnected or tied LOW.

Pin Descriptions

(continued)

Name

I/O

Description

WCSS0418V1F

Document #: 38-05245 Rev. **

Page 5 of 18

I/Os must be three-stated prior to the presentation of data to

[15:0]

and DP

[1:0]

. As a safety precaution, the data lines are

three-stated once a write cycle is detected, regardless of the

state of OE.

Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are

satisfied at clock rise: (1) CE

, CE

, and CE

are all asserted

active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWS

[1:0]

)

indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register,

burst counter/control logic and delivered to the RAM core. The

information presented to DQ

[15:0]

and DP

[1:0]

will be written

into the specified address location. Byte writes are allowed,

with BWS

controlling DQ

[7:0]

and DP

while BWS

controlling

[15:8]

and DP

. All I/Os are three-stated when a write is

detected, even a byte write. Since these are common I/O de-

vices, the asynchronous OE input signal must be deasserted

and the I/Os must be three-stated prior to the presentation of
data to DQ

[15:0]

and DP

[1:0]

. As a safety precaution, the data

lines are three-stated once a write cycle is detected, regard-

less of the state of OE.

Burst Sequences

This family of devices provides a 2-bit wrap-around burst

counter inside the SRAM. The burst counter is fed by A

[1:0]

and can follow either a linear or interleaved burst order. The

burst order is determined by the state of the MODE input. A

LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE

unconnected will cause the device to default to an interleaved

burst sequence.

Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation "sleep" mode. Two

clock cycles are required to enter into or exit from this "sleep"

mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when entering the "sleep" mode are not con-

sidered valid nor is the completion of the operation guaran-

teed. The device must be deselected prior to entering the
"sleep" mode. CE

, CE

, ADSP, and ADSC must remain

inactive for the duration of t

ZZREC

after the ZZ input returns

LOW.

Table 1. Counter Implementation for the Intel®
Pentium®/80486 Processor's Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

X + 1

Table 2. Counter Implementation for a Linear Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

X + 1

, A

X + 1

, A

X + 1

, A

X + 1

, A

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